1 /*
2 * Copyright 2017,2019 ,2021 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12 /*
13 * How to setup clock using clock driver functions:
14 *
15 * 1. call CLOCK_SetSimSafeDivs() to set the system clock dividers in SIM to safe value.
16 *
17 * 2. If external oscillator is used Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings and
18 * call CLOCK_InitOsc0() to init the OSC.
19 *
20 * 3. Call CLOCK_BootToXxxMode()/CLOCK_SetXxxMode() to set ICS run at the target mode.
21 *
22 * 4. If ICSIRCLK is needed, call CLOCK_SetInternalRefClkConfig() to enable the clock.
23 *
24 * 5. call CLOCK_SetSimConfig() to configure the divider in sim.
25 */
26
27 /* clang-format off */
28 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
29 !!GlobalInfo
30 product: Clocks v7.0
31 processor: MKE06Z128xxx4
32 package_id: MKE06Z128VLK4
33 mcu_data: ksdk2_0
34 processor_version: 9.0.0
35 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
36 /* clang-format on */
37
38 #include "clock_config.h"
39
40 /*******************************************************************************
41 * Definitions
42 ******************************************************************************/
43
44 /*******************************************************************************
45 * Variables
46 ******************************************************************************/
47 /* System clock frequency. */
48 extern uint32_t SystemCoreClock;
49
50 /*******************************************************************************
51 ************************ BOARD_InitBootClocks function ************************
52 ******************************************************************************/
BOARD_InitBootClocks(void)53 void BOARD_InitBootClocks(void)
54 {
55 BOARD_BootClockRUN();
56 }
57
58 /*******************************************************************************
59 ********************** Configuration BOARD_BootClockRUN ***********************
60 ******************************************************************************/
61 /* clang-format off */
62 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
63 !!Configuration
64 name: BOARD_BootClockRUN
65 called_from_default_init: true
66 outputs:
67 - {id: Bus_clock.outFreq, value: 20 MHz}
68 - {id: Core_clock.outFreq, value: 40 MHz}
69 - {id: Flash_clock.outFreq, value: 20 MHz}
70 - {id: ICSFF_clock.outFreq, value: 31.25 kHz}
71 - {id: ICSIR_clock.outFreq, value: 37.5 kHz}
72 - {id: LPO_clock.outFreq, value: 1 kHz}
73 - {id: OSCER_clock.outFreq, value: 8 MHz}
74 - {id: Plat_clock.outFreq, value: 40 MHz}
75 - {id: System_clock.outFreq, value: 40 MHz}
76 - {id: Timer_clock.outFreq, value: 20 MHz}
77 settings:
78 - {id: ICSMode, value: FEE}
79 - {id: ICS.BDIV.scale, value: '1', locked: true}
80 - {id: ICS.IREFS.sel, value: ICS.RDIV}
81 - {id: ICS.RDIV.scale, value: '256'}
82 - {id: ICS_C1_IRCLKEN_CFG, value: Enabled}
83 - {id: OSC_CR_OSCEN_CFG, value: Enabled}
84 - {id: OSC_CR_OSC_MODE_CFG, value: ModeOscLowPower}
85 - {id: OSC_CR_RANGE_CFG, value: High}
86 - {id: OSC_CR_RANGE_RDIV_CFG, value: High}
87 - {id: SIM.DIV2.scale, value: '2'}
88 - {id: SIM.DIV3.scale, value: '2', locked: true}
89 sources:
90 - {id: OSC.OSC.outFreq, value: 8 MHz, enabled: true}
91 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
92 /* clang-format on */
93
94 /*******************************************************************************
95 * Variables for BOARD_BootClockRUN configuration
96 ******************************************************************************/
97 const ics_config_t icsConfig_BOARD_BootClockRUN =
98 {
99 .icsMode = kICS_ModeFEE, /* FEE - FLL Engaged External */
100 .irClkEnableMode = kICS_IrclkEnable, /* ICSIRCLK enabled, ICSIRCLK disabled in STOP mode */
101 .bDiv = 0x0U, /* Bus clock divider: divided by 1 */
102 .rDiv = 0x3U, /* FLL external reference clock divider: divided by 256 */
103 };
104 const sim_clock_config_t simConfig_BOARD_BootClockRUN =
105 {
106 .outDiv1 = 0x0U, /* DIV1 clock divider: divided by 1 */
107 .outDiv2 = 0x1U, /* DIV2 clock divider: divided by 2 */
108 .outDiv3 = 0x1U, /* DIV3 clock divider: divided by 2 */
109 .busClkPrescaler = 0x0U, /* bus clock optional prescaler */
110 };
111 const osc_config_t oscConfig_BOARD_BootClockRUN =
112 {
113 .freq = 8000000U, /* Oscillator frequency: 8000000Hz */
114 .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
115 .enableMode = kOSC_Enable, /* Enable external reference clock, disable external reference clock in STOP mode */
116 };
117
118 /*******************************************************************************
119 * Code for BOARD_BootClockRUN configuration
120 ******************************************************************************/
BOARD_BootClockRUN(void)121 void BOARD_BootClockRUN(void)
122 {
123 /* Set the system clock dividers in SIM to safe value. */
124 CLOCK_SetSimSafeDivs();
125 /* Initializes OSC0 according to board configuration. */
126 CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
127 CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
128 /* Set ICS to FEE mode. */
129 CLOCK_BootToFeeMode(icsConfig_BOARD_BootClockRUN.bDiv,
130 icsConfig_BOARD_BootClockRUN.rDiv);
131 /* Configure the Internal Reference clock (ICSIRCLK). */
132 CLOCK_SetInternalRefClkConfig(icsConfig_BOARD_BootClockRUN.irClkEnableMode);
133 /* Set the clock configuration in SIM module. */
134 CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
135 /* Set SystemCoreClock variable. */
136 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
137 }
138
139
