1 /*
2 * Copyright 2018-2019 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /* clang-format off */
9 /*
10 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
11 !!GlobalInfo
12 product: Pins v5.0
13 processor: MK66FN2M0xxx18
14 package_id: MK66FN2M0VMD18
15 mcu_data: ksdk2_0
16 processor_version: 0.0.19
17 board: FRDM-K66F
18 pin_labels:
19 - {pin_num: A1, pin_signal: PTD7/CMT_IRO/UART0_TX/FTM0_CH7/SDRAM_CKE/FTM0_FLT1/SPI1_SIN, label: 'J6[7]/SPI1_SIN/MISO'}
20 - {pin_num: B1, pin_signal: PTD12/SPI2_SCK/FTM3_FLT0/SDHC0_D4/FB_A20, label: 'J2[19]/FB_A20', identifier: FB_A20}
21 - {pin_num: C1, pin_signal: PTD15/SPI2_PCS1/SDHC0_D7/FB_A23, label: NC}
22 - {pin_num: D1, pin_signal: ADC1_SE6a/PTE2/LLWU_P1/SPI1_SCK/UART1_CTS_b/SDHC0_DCLK/TRACE_D2, label: SDHC0_DCLK, identifier: SDHC0_DCLK}
23 - {pin_num: E1, pin_signal: PTE6/LLWU_P16/SPI1_PCS3/UART3_CTS_b/I2S0_MCLK/FTM3_CH1/USB0_SOF_OUT, label: LEDRGB_GREEN, identifier: LED_GREEN}
24 - {pin_num: F1, pin_signal: PTE10/LLWU_P18/I2C3_SDA/I2S0_TXD0/LPUART0_CTS_b/FTM3_CH5/USB1_ID, label: USB_ID, identifier: USB_ID}
25 - {pin_num: G1, pin_signal: VREG_OUT, label: C81, identifier: C81}
26 - {pin_num: J1, pin_signal: USB1_DP/LLWU_P30, label: K66_MICRO_USB_DP, identifier: K66_MICRO_USB_DP_DCD;K66_MICRO_USB_DP_PHY}
27 - {pin_num: H1, pin_signal: USB0_DP, label: NC}
28 - {pin_num: K1, pin_signal: USB1_DM/LLWU_P31, label: K66_MICRO_USB_DN, identifier: K66_MICRO_USB_DN_DCD;K66_MICRO_USB_DN_PHY}
29 - {pin_num: L1, pin_signal: USB1_VBUS/LLWU_P29, label: P5V_K66_USB, identifier: P5V_K66_USB}
30 - {pin_num: M1, pin_signal: ADC1_DP0/ADC0_DP3, label: 'J4[1]/DIFF_ADC1_DP0', identifier: DIFF_ADC1_DP0}
31 - {pin_num: A2, pin_signal: ADC0_SE7b/PTD6/LLWU_P15/SPI0_PCS3/UART0_RX/FTM0_CH6/FB_AD0/FTM0_FLT0/SPI1_SOUT, label: 'J6[6]/SPI1_SOUT/MOSI'}
32 - {pin_num: B2, pin_signal: PTD11/LLWU_P25/SPI2_PCS0/SDHC0_CLKIN/LPUART0_CTS_b/FB_A19, label: SW2, identifier: SW2}
33 - {pin_num: C2, pin_signal: PTD14/SPI2_SIN/SDHC0_D6/FB_A22, label: NC}
34 - {pin_num: D2, pin_signal: ADC1_SE5a/PTE1/LLWU_P0/SPI1_SOUT/UART1_RX/SDHC0_D0/TRACE_D3/I2C1_SCL/SPI1_SIN, label: SDHC0_D0, identifier: SDHC0_D0}
35 - {pin_num: E2, pin_signal: PTE5/SPI1_PCS2/UART3_RX/SDHC0_D2/FTM3_CH0, label: SDHC0_D2, identifier: SDHC0_D2}
36 - {pin_num: F2, pin_signal: PTE9/LLWU_P17/I2S0_TXD1/I2S0_RX_BCLK/LPUART0_RX/FTM3_CH4, label: 'J30[3]/U22[3]/I2S_RX_BCLK', identifier: I2S_RX_BCLK}
37 - {pin_num: G2, pin_signal: VREG_IN0, label: VREGIN_K66}
38 - {pin_num: J2, pin_signal: VREG_IN1, label: VREGIN_K66}
39 - {pin_num: H2, pin_signal: USB0_DM, label: NC}
40 - {pin_num: K2, pin_signal: USB1_VSS, label: GND}
41 - {pin_num: L2, pin_signal: ADC0_DM0/ADC1_DM3, label: 'J2[3]/ADC0_DM0_RC', identifier: ADC0_DM0_RC}
42 - {pin_num: M2, pin_signal: ADC1_DM0/ADC0_DM3, label: 'J4[3]/DIFF_ADC1_DM0', identifier: DIFF_ADC1_DM0}
43 - {pin_num: A3, pin_signal: ADC0_SE6b/PTD5/SPI0_PCS2/UART0_CTS_b/UART0_COL_b/FTM0_CH5/FB_AD1/SDRAM_A9/EWM_OUT_b/SPI1_SCK, label: 'J6[7]/SPI1_SCK/SCK'}
44 - {pin_num: B3, pin_signal: PTD10/LPUART0_RTS_b/FB_A18, label: SD_CARD_DETECT, identifier: SDCARD_CARD_DETECTION}
45 - {pin_num: C3, pin_signal: PTD13/SPI2_SOUT/SDHC0_D5/FB_A21, label: 'J2[17]/FB_A21', identifier: FB_A21}
46 - {pin_num: D3, pin_signal: ADC1_SE4a/PTE0/SPI1_PCS1/UART1_TX/SDHC0_D1/TRACE_CLKOUT/I2C1_SDA/RTC_CLKOUT, label: SDHC0_D1, identifier: SDHC0_D1}
47 - {pin_num: E3, pin_signal: PTE4/LLWU_P2/SPI1_PCS0/UART3_TX/SDHC0_D3/TRACE_D0, label: SDHC0_D3, identifier: SDHC0_D3}
48 - {pin_num: F3, pin_signal: PTE8/I2S0_RXD1/I2S0_RX_FS/LPUART0_TX/FTM3_CH3, label: 'J1[13]/J34[3]/J38[1]/I2S_RX_WCLK/I2S_RXD1', identifier: I2S_RX_WCLK_RXD1}
49 - {pin_num: G3, pin_signal: PTE12/I2S0_TX_BCLK/FTM3_CH7, label: 'J1[1]/J37[3]/I2S_TX_BCLK', identifier: I2S_TX_BCLK}
50 - {pin_num: H3, pin_signal: VSS6, label: GND}
51 - {pin_num: J3, pin_signal: ADC0_SE16/CMP1_IN2/ADC0_SE21, label: 'J4[5]/ADC0', identifier: ADC0_SE16}
52 - {pin_num: K3, pin_signal: ADC1_SE16/CMP2_IN2/ADC0_SE22, label: 'J4[7]/ADC1', identifier: ADC1_SE16}
53 - {pin_num: L3, pin_signal: DAC0_OUT/CMP1_IN3/ADC0_SE23, label: 'J4[11]/DAC_OUT', identifier: DAC0_OUT}
54 - {pin_num: M3, pin_signal: VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18, label: 'J2[1]/ADC1_SE18_RC', identifier: ADC1_SE18_RC}
55 - {pin_num: A4, pin_signal: PTD4/LLWU_P14/SPI0_PCS1/UART0_RTS_b/FTM0_CH4/FB_AD2/SDRAM_A10/EWM_IN/SPI1_PCS0, label: 'J6[4]/SPI1_PCS0/CS'}
56 - {pin_num: B4, pin_signal: PTD3/SPI0_SIN/UART2_TX/FTM3_CH3/FB_AD3/SDRAM_A11/I2C0_SDA, label: 'J2[10]/SPI0_SIN/FB_AD3', identifier: SPI0_SIN}
57 - {pin_num: C4, pin_signal: PTD2/LLWU_P13/SPI0_SOUT/UART2_RX/FTM3_CH2/FB_AD4/SDRAM_A12/I2C0_SCL, label: 'J2[8]/SPI0_SOUT/FB_AD4', identifier: SPI0_SOUT}
58 - {pin_num: D4, pin_signal: ADC0_SE5b/PTD1/SPI0_SCK/UART2_CTS_b/FTM3_CH1/FB_CS0_b, label: 'J2[12]/SPI0_SCK/FB_CS0_B', identifier: SPI0_SCK}
59 - {pin_num: E4, pin_signal: ADC1_SE7a/PTE3/SPI1_SIN/UART1_RTS_b/SDHC0_CMD/TRACE_D1/SPI1_SOUT, label: SDHC0_CMD, identifier: SDHC0_CMD}
60 - {pin_num: F4, pin_signal: PTE7/UART3_RTS_b/I2S0_RXD0/FTM3_CH2, label: 'J1[15]/J34[1]/U20[C7]/I2S_RXD0', identifier: I2S_RXD0}
61 - {pin_num: G4, pin_signal: PTE11/I2C3_SCL/I2S0_TX_FS/LPUART0_RTS_b/FTM3_CH6, label: 'J1[3]/J38[3]/I2S_TX_WCLK', identifier: I2S_TX_WCLK}
62 - {pin_num: H4, pin_signal: PTE28, label: 'J14[1]/ETHERNET_RST/PET_1_RST_B'}
63 - {pin_num: J4, pin_signal: PTE27/UART4_RTS_b, label: NC}
64 - {pin_num: K4, pin_signal: PTE26/ENET_1588_CLKIN/UART4_CTS_b/RTC_CLKOUT/USB0_CLKIN, label: 'U13[16]/ETHERNET_CLOCK', identifier: ETHERNET_CLOCK;ENET_1588_CLKIN}
65 - {pin_num: L4, pin_signal: DAC1_OUT/CMP0_IN4/CMP2_IN3/ADC1_SE23, label: 'J2[5]/ADC1_SE23_RC', identifier: ADC1_SE23_RC}
66 - {pin_num: M4, pin_signal: ADC0_SE17/PTE24/CAN1_TX/UART4_TX/I2C0_SCL/EWM_OUT_b, label: 'J2[13]/ADC0_SE17', identifier: ADC0_SE17}
67 - {pin_num: A5, pin_signal: PTD0/LLWU_P12/SPI0_PCS0/UART2_RTS_b/FTM3_CH0/FB_ALE/FB_CS1_b/FB_TS_b, label: 'J2[6]/SPI0_PCS0/FTM3_CH0', identifier: SPI0_PCS0}
68 - {pin_num: C5, pin_signal: PTC18/UART3_RTS_b/ENET0_1588_TMR2/FB_TBST_b/FB_CS2_b/FB_BE15_8_BLS23_16_b/SDRAM_DQM1, label: 'J6[8]/RF_WIFI_IRQ'}
69 - {pin_num: B5, pin_signal: PTC19/UART3_CTS_b/ENET0_1588_TMR3/FB_CS3_b/FB_BE7_0_BLS31_24_b/SDRAM_DQM0/FB_TA_b, label: NC}
70 - {pin_num: D5, pin_signal: PTC17/CAN1_TX/UART3_TX/ENET0_1588_TMR1/FB_CS4_b/FB_TSIZ0/FB_BE31_24_BLS7_0_b/SDRAM_DQM3, label: 'U8[11]/FXOS8700CQ_INT1', identifier: ACCEL_INT1}
71 - {pin_num: E5, pin_signal: VDD5, label: P3V3_K66F}
72 - {pin_num: F5, pin_signal: VDD126, label: P3V3_K66F}
73 - {pin_num: G5, pin_signal: VREFH, label: VREFH}
74 - {pin_num: H5, pin_signal: VDDA, label: P3V3_K66F}
75 - {pin_num: J5, pin_signal: TSI0_CH1/PTA0/UART0_CTS_b/UART0_COL_b/FTM0_CH5/LPUART0_CTS_b/JTAG_TCLK/SWD_CLK/EZP_CLK, label: 'J8[2]/J9[4]/JTAG_TCLK/SWD_CLK/EZP_CLK',
76 identifier: SWD_CLK}
77 - {pin_num: K5, pin_signal: ADC0_SE18/PTE25/LLWU_P21/CAN1_RX/UART4_RX/I2C0_SDA/EWM_IN, label: 'J2[15]/ADC0_SE18', identifier: ADC0_SE18}
78 - {pin_num: L5, pin_signal: RTC_WAKEUP_B, label: RTC_WAKEUP/TP18}
79 - {pin_num: M5, pin_signal: NC184, label: NC}
80 - {pin_num: A6, pin_signal: PTC16/CAN1_RX/UART3_RX/ENET0_1588_TMR0/FB_CS5_b/FB_TSIZ1/FB_BE23_16_BLS15_8_b/SDRAM_DQM2, label: 'J1[6]/ENET0_1588_TMR0', identifier: ENET0_1588_TMR0}
81 - {pin_num: B6, pin_signal: PTC15/UART4_TX/FB_AD24/SDRAM_D24, label: 'J199[4]/K66F_UART4_TX', identifier: K66F_UART4_TX}
82 - {pin_num: C6, pin_signal: PTC14/UART4_RX/FB_AD25/SDRAM_D25, label: 'J199[3]/K66F_UART4_RX', identifier: K66F_UART4_RX}
83 - {pin_num: D6, pin_signal: PTC13/UART4_CTS_b/FTM_CLKIN1/FB_AD26/SDRAM_D26/TPM_CLKIN1, label: 'U8[9]/FXOS8700CQ_INT2', identifier: ACCEL_INT2}
84 - {pin_num: E6, pin_signal: VDD16, label: P3V3_K66F}
85 - {pin_num: F6, pin_signal: VSS22, label: GND}
86 - {pin_num: G6, pin_signal: VREFL, label: GND}
87 - {pin_num: H6, pin_signal: VSSA, label: GND}
88 - {pin_num: J6, pin_signal: TSI0_CH2/PTA1/UART0_RX/FTM0_CH6/I2C3_SDA/LPUART0_RX/JTAG_TDI/EZP_DI, label: 'J3[15]/FTM0_CH6', identifier: FTM0_CH6}
89 - {pin_num: K6, pin_signal: TSI0_CH3/PTA2/UART0_TX/FTM0_CH7/I2C3_SCL/LPUART0_TX/JTAG_TDO/TRACE_SWO/EZP_DO, label: 'J9[6]/JTAG_TDO/TRACE_SWO/EZP_DO', identifier: TRACE_SWO}
90 - {pin_num: L6, pin_signal: VBAT, label: VBAT}
91 - {pin_num: M6, pin_signal: EXTAL32, label: 'Y3[2]', identifier: EXTAL32K}
92 - {pin_num: A7, pin_signal: PTC12/UART4_RTS_b/FTM_CLKIN0/FB_AD27/SDRAM_D27/FTM3_FLT0/TPM_CLKIN0, label: 'J1[10]/FB_AD27', identifier: FB_AD27}
93 - {pin_num: B7, pin_signal: ADC1_SE7b/PTC11/LLWU_P11/I2C1_SDA/FTM3_CH7/I2S0_RXD1/FB_RW_b, label: 'J2[18]/U20[C9]/I2C1_SDA/DA7212_SDA', identifier: I2C1_SDA}
94 - {pin_num: C7, pin_signal: ADC1_SE6b/PTC10/I2C1_SCL/FTM3_CH6/I2S0_RX_FS/FB_AD5/SDRAM_A13, label: 'J2[20]/U20[D8]/I2C1_SCL/DA7212_CLK', identifier: I2C1_SCL}
95 - {pin_num: D7, pin_signal: ADC1_SE5b/CMP0_IN3/PTC9/FTM3_CH5/I2S0_RX_BCLK/FB_AD6/SDRAM_A14/FTM2_FLT0, label: LEDRGB_RED, identifier: LED_RED}
96 - {pin_num: E7, pin_signal: VDD80, label: P3V3_K66F}
97 - {pin_num: F7, pin_signal: VSS17, label: GND}
98 - {pin_num: G7, pin_signal: VSS81, label: GND}
99 - {pin_num: H7, pin_signal: VSS125, label: GND}
100 - {pin_num: J7, pin_signal: PTA6/FTM0_CH3/CLKOUT/TRACE_CLKOUT, label: 'J3[7]/CLKOUT', identifier: CLKOUT}
101 - {pin_num: K7, pin_signal: TSI0_CH4/PTA3/UART0_RTS_b/FTM0_CH0/LPUART0_RTS_b/JTAG_TMS/SWD_DIO, label: 'J9[2]/J12[2]/JTAG_TMS/SWD_DIO', identifier: SWD_DIO}
102 - {pin_num: L7, pin_signal: TSI0_CH5/PTA4/LLWU_P3/FTM0_CH1/NMI_b/EZP_CS_b, label: 'J3[5]/LLWU_P3/FTM0_CH1/NMI', identifier: NMI}
103 - {pin_num: M7, pin_signal: XTAL32, label: 'Y3[1]', identifier: XTAL32K}
104 - {pin_num: A8, pin_signal: ADC1_SE4b/CMP0_IN2/PTC8/FTM3_CH4/I2S0_MCLK/FB_AD7/SDRAM_A15, label: 'J1[8]/FTM3_CH4/ADC1_SE4b', identifier: FTM3_CH4}
105 - {pin_num: B8, pin_signal: CMP0_IN1/PTC7/SPI0_SIN/USB0_SOF_OUT/I2S0_RX_FS/FB_AD8/SDRAM_A16, label: 'J1[11]/USB0_SOF_OUT/I2S0_RX_FS/FB_AD8', identifier: USB_SOF_OUT}
106 - {pin_num: C8, pin_signal: CMP0_IN0/PTC6/LLWU_P10/SPI0_SOUT/PDB0_EXTRG/I2S0_RX_BCLK/FB_AD9/SDRAM_A17/I2S0_MCLK, label: 'J1[9]/LLWU_P10/FB_AD9/I2S0_MCLK', identifier: I2S_MCLK}
107 - {pin_num: D8, pin_signal: PTC5/LLWU_P9/SPI0_SCK/LPTMR0_ALT2/I2S0_RXD0/FB_AD10/SDRAM_A18/CMP0_OUT/FTM0_CH2, label: 'J1[12]/I2S0_RXD0/FB_AD10/FTM0_CH2', identifier: FB_AD10}
108 - {pin_num: E8, pin_signal: VDD94, label: P3V3_K66F}
109 - {pin_num: F8, pin_signal: VDD173, label: P3V3_K66F}
110 - {pin_num: G8, pin_signal: VSS95, label: GND}
111 - {pin_num: H8, pin_signal: VSS139, label: GND}
112 - {pin_num: J8, pin_signal: ADC0_SE10/PTA7/FTM0_CH4/RMII0_MDIO/MII0_MDIO/TRACE_D3, label: 'J3[9]/FTM0_CH4/TRACE_D3', identifier: FTM0_CH4}
113 - {pin_num: K8, pin_signal: ADC0_SE11/PTA8/FTM1_CH0/RMII0_MDC/MII0_MDC/FTM1_QD_PHA/TPM1_CH0/TRACE_D2, label: 'J3[11]/FTM1_CH0/TRACE_D2', identifier: FTM1_CH0}
114 - {pin_num: L8, pin_signal: PTA9/FTM1_CH1/MII0_RXD3/FTM1_QD_PHB/TPM1_CH1/TRACE_D1, label: 'J3[13]/FTM1_CH1/TRACE_D1', identifier: FTM1_CH1}
115 - {pin_num: M8, pin_signal: PTA5/USB0_CLKIN/FTM0_CH2/RMII0_RXER/MII0_RXER/CMP2_OUT/I2S0_TX_BCLK/JTAG_TRST_b, label: 'U13[17]/RMII0_RXER', identifier: RMII0_RXER}
116 - {pin_num: A9, pin_signal: PTC4/LLWU_P8/SPI0_PCS0/UART1_TX/FTM0_CH3/FB_AD11/SDRAM_A19/CMP1_OUT, label: 'J1[4]/UART1_TX/FTM0_CH3/FB_AD11', identifier: UART1_TX}
117 - {pin_num: B9, pin_signal: PTD9/I2C0_SDA/LPUART0_TX/FB_A17, label: 'U8[6]/U19[12]/I2C0_SDA', identifier: ACCEL_SDA;GYRO_SDA}
118 - {pin_num: C9, pin_signal: PTD8/LLWU_P24/I2C0_SCL/LPUART0_RX/FB_A16, label: 'U8[4]/U19[11]/I2C0_SCL', identifier: ACCEL_SCL;GYRO_SCL}
119 - {pin_num: D9, pin_signal: PTB21/SPI2_SCK/FB_AD30/SDRAM_D30/CMP1_OUT, label: NC}
120 - {pin_num: E9, pin_signal: TSI0_CH10/PTB17/SPI1_SIN/UART0_TX/FTM_CLKIN1/FB_AD16/SDRAM_D16/EWM_OUT_b/TPM_CLKIN1, label: 'U10[1]/UART0_TX', identifier: DEBUG_UART_TX}
121 - {pin_num: F9, pin_signal: PTB9/SPI1_PCS1/UART3_CTS_b/FB_AD20/SDRAM_D20, label: NC}
122 - {pin_num: G9, pin_signal: ADC1_SE11/PTB5/ENET0_1588_TMR3/FTM2_FLT0, label: 'J4[6]/ADC1_SE11', identifier: ADC1_SE11}
123 - {pin_num: H9, pin_signal: ADC0_SE9/ADC1_SE9/TSI0_CH6/PTB1/I2C0_SDA/FTM1_CH1/RMII0_MDC/MII0_MDC/SDRAM_RAS_b/FTM1_QD_PHB/TPM1_CH1, label: 'U13[11]/RMII0_MDC', identifier: RMII0_MDC}
124 - {pin_num: J9, pin_signal: CMP2_IN1/PTA13/LLWU_P4/CAN0_RX/FTM1_CH1/RMII0_RXD0/MII0_RXD0/I2C2_SDA/I2S0_TX_FS/FTM1_QD_PHB/TPM1_CH1, label: 'U13[13]/RMII0_RXD0', identifier: RMII0_RXD0}
125 - {pin_num: K9, pin_signal: CMP2_IN0/PTA12/CAN0_TX/FTM1_CH0/RMII0_RXD1/MII0_RXD1/I2C2_SCL/I2S0_TXD0/FTM1_QD_PHA/TPM1_CH0, label: 'U13[12]/RMII0_RXD1', identifier: RMII0_RXD1}
126 - {pin_num: L9, pin_signal: PTA11/LLWU_P23/FTM2_CH1/MII0_RXCLK/I2C2_SDA/FTM2_QD_PHB/TPM2_CH1, label: LEDRGB_BLUE, identifier: LED_BLUE}
127 - {pin_num: M9, pin_signal: PTA10/LLWU_P22/FTM2_CH0/MII0_RXD2/FTM2_QD_PHA/TPM2_CH0/TRACE_D0, label: SW3, identifier: SW3}
128 - {pin_num: A10, pin_signal: NC185, label: NC}
129 - {pin_num: B10, pin_signal: NC186, label: NC}
130 - {pin_num: C10, pin_signal: NC187, label: NC}
131 - {pin_num: D10, pin_signal: PTB20/SPI2_PCS0/FB_AD31/SDRAM_D31/CMP0_OUT, label: 'J6[3]/RF_WIFI_CE'}
132 - {pin_num: E10, pin_signal: TSI0_CH9/PTB16/SPI1_SOUT/UART0_RX/FTM_CLKIN0/FB_AD17/SDRAM_D17/EWM_IN/TPM_CLKIN0, label: 'U7[4]/UART0_RX', identifier: DEBUG_UART_RX}
133 - {pin_num: F10, pin_signal: PTB8/UART3_RTS_b/FB_AD21/SDRAM_D21, label: NC}
134 - {pin_num: G10, pin_signal: ADC1_SE10/PTB4/ENET0_1588_TMR2/SDRAM_CS1_b/FTM1_FLT0, label: 'J4[8]/ADC1_SE10', identifier: ADC1_SE10}
135 - {pin_num: H10, pin_signal: ADC0_SE8/ADC1_SE8/TSI0_CH0/PTB0/LLWU_P5/I2C0_SCL/FTM1_CH0/RMII0_MDIO/MII0_MDIO/SDRAM_CAS_b/FTM1_QD_PHA/TPM1_CH0, label: 'U13[10]/RMII0_MDIO',
136 identifier: RMII0_MDIO}
137 - {pin_num: J10, pin_signal: PTA27/MII0_CRS/FB_A26, label: 'J3[1]/FB_A26', identifier: FB_A26}
138 - {pin_num: K10, pin_signal: CMP3_IN2/PTA16/SPI0_SOUT/UART0_CTS_b/UART0_COL_b/RMII0_TXD0/MII0_TXD0/I2S0_RX_FS/I2S0_RXD1, label: 'U13[20]/RMII0_TXD_0', identifier: RMII0_TXD_0}
139 - {pin_num: L10, pin_signal: PTA14/SPI0_PCS0/UART0_TX/RMII0_CRS_DV/MII0_RXDV/I2C2_SCL/I2S0_RX_BCLK/I2S0_TXD1, label: 'U13[15]/RMII0_CRS_DV', identifier: RMII0_CRS_DV}
140 - {pin_num: M10, pin_signal: VSS172, label: GND}
141 - {pin_num: A11, pin_signal: CMP1_IN1/PTC3/LLWU_P7/SPI0_PCS1/UART1_RX/FTM0_CH2/CLKOUT/I2S0_TX_BCLK, label: 'J1[2]/UART1_RX/FTM0_CH2/CLKOUT', identifier: UART1_RX}
142 - {pin_num: B11, pin_signal: ADC0_SE15/TSI0_CH14/PTC1/LLWU_P6/SPI0_PCS3/UART1_RTS_b/FTM0_CH0/FB_AD13/SDRAM_A21/I2S0_TXD0, label: 'J1[5]/U20[C5]/I2S_TXD', identifier: I2S_TXD}
143 - {pin_num: C11, pin_signal: PTB23/SPI2_SIN/SPI0_PCS5/FB_AD28/SDRAM_D28/CMP3_OUT, label: 'J3[9]/CMP3_OUT', identifier: CMP_OUT}
144 - {pin_num: D11, pin_signal: TSI0_CH12/PTB19/CAN0_RX/FTM2_CH1/I2S0_TX_FS/FB_OE_b/FTM2_QD_PHB/TPM2_CH1, label: 'J2[4]/FTM2_CH1', identifier: FTM2_CH1}
145 - {pin_num: E11, pin_signal: ADC1_SE15/PTB11/SPI1_SCK/UART3_TX/FB_AD18/SDRAM_D18/FTM0_FLT2, label: 'J2[9]/PTB11_RC/ADC1_SE15', identifier: PTB11_RC}
146 - {pin_num: E12, pin_signal: ADC1_SE14/PTB10/SPI1_PCS0/UART3_RX/FB_AD19/SDRAM_D19/FTM0_FLT1, label: 'J2[7]/PTB10_RC/ADC1_SE14', identifier: PTB10_RC}
147 - {pin_num: F11, pin_signal: ADC1_SE13/PTB7/FB_AD22/SDRAM_D22, label: 'J4[2]/ADC1_SE13', identifier: ADC1_SE13}
148 - {pin_num: G11, pin_signal: ADC0_SE13/TSI0_CH8/PTB3/I2C0_SDA/UART0_CTS_b/UART0_COL_b/ENET0_1588_TMR1/SDRAM_CS0_b/FTM0_FLT0, label: 'J4[10]/ADC0_SE13/I2C0_SDA', identifier: ADC0_SE13}
149 - {pin_num: G12, pin_signal: ADC0_SE12/TSI0_CH7/PTB2/I2C0_SCL/UART0_RTS_b/ENET0_1588_TMR0/SDRAM_WE/FTM0_FLT3, label: 'J4[12]/ADC0_SE12/I2C0_SCL', identifier: ADC0_SE12}
150 - {pin_num: H11, pin_signal: PTA29/MII0_COL/FB_A24, label: 'U19[3]/FXAS21002_INT1', identifier: GYRO_INT1}
151 - {pin_num: J11, pin_signal: PTA26/MII0_TXD3/FB_A27, label: 'J3[3]/FB_A27', identifier: FB_A27}
152 - {pin_num: K11, pin_signal: ADC1_SE17/PTA17/SPI0_SIN/UART0_RTS_b/RMII0_TXD1/MII0_TXD1/I2S0_MCLK, label: 'U13[21]/RMII0_TXD_1', identifier: RMII0_TXD_1}
153 - {pin_num: L11, pin_signal: CMP3_IN1/PTA15/SPI0_SCK/UART0_RX/RMII0_TXEN/MII0_TXEN/I2S0_RXD0, label: 'U13[19]/RMII0_TXEN', identifier: RMII0_TXEN}
154 - {pin_num: M11, pin_signal: XTAL0/PTA19/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1/TPM_CLKIN1, label: 'X501[3]', identifier: XTAL0}
155 - {pin_num: A12, pin_signal: ADC0_SE4b/CMP1_IN0/TSI0_CH15/PTC2/SPI0_PCS2/UART1_CTS_b/FTM0_CH1/FB_AD12/SDRAM_A20/I2S0_TX_FS, label: 'J1[14]/FTM0_CH1/CMP1_IN0/FB_AD12',
156 identifier: FTM0_CH1}
157 - {pin_num: B12, pin_signal: ADC0_SE14/TSI0_CH13/PTC0/SPI0_PCS4/PDB0_EXTRG/USB0_SOF_OUT/FB_AD14/SDRAM_A22/I2S0_TXD1, label: 'J2[11]/ADC0_SE14', identifier: ADC0_SE14}
158 - {pin_num: C12, pin_signal: PTB22/SPI2_SOUT/FB_AD29/SDRAM_D29/CMP2_OUT, label: NC}
159 - {pin_num: D12, pin_signal: TSI0_CH11/PTB18/CAN0_TX/FTM2_CH0/I2S0_TX_BCLK/FB_AD15/SDRAM_A23/FTM2_QD_PHA/TPM2_CH0, label: 'J2[2]/FTM2_CH0', identifier: FTM2_CH0}
160 - {pin_num: F12, pin_signal: ADC1_SE12/PTB6/FB_AD23/SDRAM_D23, label: 'J4[4]/ADC1_SE12', identifier: ADC1_SE12}
161 - {pin_num: H12, pin_signal: PTA28/MII0_TXER/FB_A25, label: 'U19[2]/FXAS21002_INT2', identifier: GYRO_INT2}
162 - {pin_num: J12, pin_signal: CMP3_IN5/PTA25/MII0_TXCLK/FB_A28, label: 'J1[16]/CMP3_IN5', identifier: CMP3_IN5}
163 - {pin_num: K12, pin_signal: CMP3_IN4/PTA24/MII0_TXD2/FB_A29, label: NC}
164 - {pin_num: L12, pin_signal: RESET_b, label: RESET}
165 - {pin_num: M12, pin_signal: EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0/TPM_CLKIN0, label: EXTAL0, identifier: EXTAL0}
166 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
167 */
168 /* clang-format on */
169
170 #include "fsl_common.h"
171 #include "fsl_port.h"
172 #include "fsl_gpio.h"
173 #include "pin_mux.h"
174
175 /* FUNCTION ************************************************************************************************************
176 *
177 * Function Name : BOARD_InitBootPins
178 * Description : Calls initialization functions.
179 *
180 * END ****************************************************************************************************************/
BOARD_InitBootPins(void)181 void BOARD_InitBootPins(void)
182 {
183 BOARD_InitPins();
184 BOARD_InitDEBUG_UARTPins();
185 }
186
187 /* clang-format off */
188 /*
189 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
190 BOARD_InitPins:
191 - options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
192 - pin_list:
193 - {pin_num: K6, peripheral: TPIU, signal: SWO, pin_signal: TSI0_CH3/PTA2/UART0_TX/FTM0_CH7/I2C3_SCL/LPUART0_TX/JTAG_TDO/TRACE_SWO/EZP_DO, pull_select: down, pull_enable: disable}
194 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
195 */
196 /* clang-format on */
197
198 /* FUNCTION ************************************************************************************************************
199 *
200 * Function Name : BOARD_InitPins
201 * Description : Configures pin routing and optionally pin electrical features.
202 *
203 * END ****************************************************************************************************************/
BOARD_InitPins(void)204 void BOARD_InitPins(void)
205 {
206 /* Port A Clock Gate Control: Clock enabled */
207 CLOCK_EnableClock(kCLOCK_PortA);
208
209 /* PORTA2 (pin K6) is configured as TRACE_SWO */
210 PORT_SetPinMux(BOARD_TRACE_SWO_PORT, BOARD_TRACE_SWO_PIN, kPORT_MuxAlt7);
211
212 PORTA->PCR[2] = ((PORTA->PCR[2] &
213 /* Mask bits to zero which are setting */
214 (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK)))
215
216 /* Pull Select: Internal pulldown resistor is enabled on the corresponding pin, if the
217 * corresponding PE field is set. */
218 | PORT_PCR_PS(kPORT_PullDown)
219
220 /* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
221 | PORT_PCR_PE(kPORT_PullDisable));
222 }
223
224 /* clang-format off */
225 /*
226 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
227 BOARD_InitBUTTONsPins:
228 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
229 - pin_list:
230 - {pin_num: B2, peripheral: GPIOD, signal: 'GPIO, 11', pin_signal: PTD11/LLWU_P25/SPI2_PCS0/SDHC0_CLKIN/LPUART0_CTS_b/FB_A19, direction: INPUT, gpio_interrupt: kPORT_InterruptFallingEdge,
231 pull_select: up, pull_enable: enable}
232 - {pin_num: M9, peripheral: GPIOA, signal: 'GPIO, 10', pin_signal: PTA10/LLWU_P22/FTM2_CH0/MII0_RXD2/FTM2_QD_PHA/TPM2_CH0/TRACE_D0, direction: INPUT, gpio_interrupt: kPORT_InterruptFallingEdge,
233 pull_select: up, pull_enable: enable}
234 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
235 */
236 /* clang-format on */
237
238 /* FUNCTION ************************************************************************************************************
239 *
240 * Function Name : BOARD_InitBUTTONsPins
241 * Description : Configures pin routing and optionally pin electrical features.
242 *
243 * END ****************************************************************************************************************/
BOARD_InitBUTTONsPins(void)244 void BOARD_InitBUTTONsPins(void)
245 {
246 /* Port A Clock Gate Control: Clock enabled */
247 CLOCK_EnableClock(kCLOCK_PortA);
248 /* Port D Clock Gate Control: Clock enabled */
249 CLOCK_EnableClock(kCLOCK_PortD);
250
251 gpio_pin_config_t SW3_config = {
252 .pinDirection = kGPIO_DigitalInput,
253 .outputLogic = 0U
254 };
255 /* Initialize GPIO functionality on pin PTA10 (pin M9) */
256 GPIO_PinInit(BOARD_SW3_GPIO, BOARD_SW3_PIN, &SW3_config);
257
258 gpio_pin_config_t SW2_config = {
259 .pinDirection = kGPIO_DigitalInput,
260 .outputLogic = 0U
261 };
262 /* Initialize GPIO functionality on pin PTD11 (pin B2) */
263 GPIO_PinInit(BOARD_SW2_GPIO, BOARD_SW2_PIN, &SW2_config);
264
265 /* PORTA10 (pin M9) is configured as PTA10 */
266 PORT_SetPinMux(BOARD_SW3_PORT, BOARD_SW3_PIN, kPORT_MuxAsGpio);
267
268 /* Interrupt configuration on PORTA10 (pin M9): Interrupt on falling edge */
269 PORT_SetPinInterruptConfig(BOARD_SW3_PORT, BOARD_SW3_PIN, kPORT_InterruptFallingEdge);
270
271 PORTA->PCR[10] = ((PORTA->PCR[10] &
272 /* Mask bits to zero which are setting */
273 (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK)))
274
275 /* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the
276 * corresponding PE field is set. */
277 | (uint32_t)(kPORT_PullUp));
278
279 /* PORTD11 (pin B2) is configured as PTD11 */
280 PORT_SetPinMux(BOARD_SW2_PORT, BOARD_SW2_PIN, kPORT_MuxAsGpio);
281
282 /* Interrupt configuration on PORTD11 (pin B2): Interrupt on falling edge */
283 PORT_SetPinInterruptConfig(BOARD_SW2_PORT, BOARD_SW2_PIN, kPORT_InterruptFallingEdge);
284
285 PORTD->PCR[11] = ((PORTD->PCR[11] &
286 /* Mask bits to zero which are setting */
287 (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK)))
288
289 /* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the
290 * corresponding PE field is set. */
291 | (uint32_t)(kPORT_PullUp));
292 }
293
294 /* clang-format off */
295 /*
296 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
297 BOARD_InitLEDsPins:
298 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
299 - pin_list:
300 - {pin_num: L9, peripheral: GPIOA, signal: 'GPIO, 11', pin_signal: PTA11/LLWU_P23/FTM2_CH1/MII0_RXCLK/I2C2_SDA/FTM2_QD_PHB/TPM2_CH1, direction: OUTPUT, gpio_init_state: 'true',
301 slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
302 - {pin_num: E1, peripheral: GPIOE, signal: 'GPIO, 6', pin_signal: PTE6/LLWU_P16/SPI1_PCS3/UART3_CTS_b/I2S0_MCLK/FTM3_CH1/USB0_SOF_OUT, direction: OUTPUT, gpio_init_state: 'true',
303 slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
304 - {pin_num: D7, peripheral: GPIOC, signal: 'GPIO, 9', pin_signal: ADC1_SE5b/CMP0_IN3/PTC9/FTM3_CH5/I2S0_RX_BCLK/FB_AD6/SDRAM_A14/FTM2_FLT0, direction: OUTPUT, gpio_init_state: 'true',
305 slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
306 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
307 */
308 /* clang-format on */
309
310 /* FUNCTION ************************************************************************************************************
311 *
312 * Function Name : BOARD_InitLEDsPins
313 * Description : Configures pin routing and optionally pin electrical features.
314 *
315 * END ****************************************************************************************************************/
BOARD_InitLEDsPins(void)316 void BOARD_InitLEDsPins(void)
317 {
318 /* Port A Clock Gate Control: Clock enabled */
319 CLOCK_EnableClock(kCLOCK_PortA);
320 /* Port C Clock Gate Control: Clock enabled */
321 CLOCK_EnableClock(kCLOCK_PortC);
322 /* Port E Clock Gate Control: Clock enabled */
323 CLOCK_EnableClock(kCLOCK_PortE);
324
325 gpio_pin_config_t LED_BLUE_config = {
326 .pinDirection = kGPIO_DigitalOutput,
327 .outputLogic = 1U
328 };
329 /* Initialize GPIO functionality on pin PTA11 (pin L9) */
330 GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_PIN, &LED_BLUE_config);
331
332 gpio_pin_config_t LED_RED_config = {
333 .pinDirection = kGPIO_DigitalOutput,
334 .outputLogic = 1U
335 };
336 /* Initialize GPIO functionality on pin PTC9 (pin D7) */
337 GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_PIN, &LED_RED_config);
338
339 gpio_pin_config_t LED_GREEN_config = {
340 .pinDirection = kGPIO_DigitalOutput,
341 .outputLogic = 1U
342 };
343 /* Initialize GPIO functionality on pin PTE6 (pin E1) */
344 GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_PIN, &LED_GREEN_config);
345
346 const port_pin_config_t LED_BLUE = {/* Internal pull-up/down resistor is disabled */
347 kPORT_PullDisable,
348 /* Fast slew rate is configured */
349 kPORT_FastSlewRate,
350 /* Passive filter is disabled */
351 kPORT_PassiveFilterDisable,
352 /* Open drain is disabled */
353 kPORT_OpenDrainDisable,
354 /* Low drive strength is configured */
355 kPORT_LowDriveStrength,
356 /* Pin is configured as PTA11 */
357 kPORT_MuxAsGpio,
358 /* Pin Control Register fields [15:0] are not locked */
359 kPORT_UnlockRegister};
360 /* PORTA11 (pin L9) is configured as PTA11 */
361 PORT_SetPinConfig(BOARD_LED_BLUE_PORT, BOARD_LED_BLUE_PIN, &LED_BLUE);
362
363 const port_pin_config_t LED_RED = {/* Internal pull-up/down resistor is disabled */
364 kPORT_PullDisable,
365 /* Fast slew rate is configured */
366 kPORT_FastSlewRate,
367 /* Passive filter is disabled */
368 kPORT_PassiveFilterDisable,
369 /* Open drain is disabled */
370 kPORT_OpenDrainDisable,
371 /* Low drive strength is configured */
372 kPORT_LowDriveStrength,
373 /* Pin is configured as PTC9 */
374 kPORT_MuxAsGpio,
375 /* Pin Control Register fields [15:0] are not locked */
376 kPORT_UnlockRegister};
377 /* PORTC9 (pin D7) is configured as PTC9 */
378 PORT_SetPinConfig(BOARD_LED_RED_PORT, BOARD_LED_RED_PIN, &LED_RED);
379
380 const port_pin_config_t LED_GREEN = {/* Internal pull-up/down resistor is disabled */
381 kPORT_PullDisable,
382 /* Fast slew rate is configured */
383 kPORT_FastSlewRate,
384 /* Passive filter is disabled */
385 kPORT_PassiveFilterDisable,
386 /* Open drain is disabled */
387 kPORT_OpenDrainDisable,
388 /* Low drive strength is configured */
389 kPORT_LowDriveStrength,
390 /* Pin is configured as PTE6 */
391 kPORT_MuxAsGpio,
392 /* Pin Control Register fields [15:0] are not locked */
393 kPORT_UnlockRegister};
394 /* PORTE6 (pin E1) is configured as PTE6 */
395 PORT_SetPinConfig(BOARD_LED_GREEN_PORT, BOARD_LED_GREEN_PIN, &LED_GREEN);
396 }
397
398 /* clang-format off */
399 /*
400 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
401 BOARD_InitACCEL_I2CPins:
402 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
403 - pin_list:
404 - {pin_num: C9, peripheral: I2C0, signal: SCL, pin_signal: PTD8/LLWU_P24/I2C0_SCL/LPUART0_RX/FB_A16, identifier: ACCEL_SCL, slew_rate: fast, open_drain: enable,
405 pull_select: down, pull_enable: disable, digital_filter: disable}
406 - {pin_num: B9, peripheral: I2C0, signal: SDA, pin_signal: PTD9/I2C0_SDA/LPUART0_TX/FB_A17, identifier: ACCEL_SDA, slew_rate: fast, open_drain: enable, pull_select: down,
407 pull_enable: disable, digital_filter: disable}
408 - {pin_num: D5, peripheral: GPIOC, signal: 'GPIO, 17', pin_signal: PTC17/CAN1_TX/UART3_TX/ENET0_1588_TMR1/FB_CS4_b/FB_TSIZ0/FB_BE31_24_BLS7_0_b/SDRAM_DQM3, direction: INPUT,
409 slew_rate: fast, open_drain: disable, pull_select: up, pull_enable: enable}
410 - {pin_num: D6, peripheral: GPIOC, signal: 'GPIO, 13', pin_signal: PTC13/UART4_CTS_b/FTM_CLKIN1/FB_AD26/SDRAM_D26/TPM_CLKIN1, direction: INPUT, slew_rate: fast,
411 open_drain: disable, pull_select: up, pull_enable: enable}
412 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
413 */
414 /* clang-format on */
415
416 /* FUNCTION ************************************************************************************************************
417 *
418 * Function Name : BOARD_InitACCEL_I2CPins
419 * Description : Configures pin routing and optionally pin electrical features.
420 *
421 * END ****************************************************************************************************************/
BOARD_InitACCEL_I2CPins(void)422 void BOARD_InitACCEL_I2CPins(void)
423 {
424 /* Port C Clock Gate Control: Clock enabled */
425 CLOCK_EnableClock(kCLOCK_PortC);
426 /* Port D Clock Gate Control: Clock enabled */
427 CLOCK_EnableClock(kCLOCK_PortD);
428
429 gpio_pin_config_t ACCEL_INT2_config = {
430 .pinDirection = kGPIO_DigitalInput,
431 .outputLogic = 0U
432 };
433 /* Initialize GPIO functionality on pin PTC13 (pin D6) */
434 GPIO_PinInit(BOARD_ACCEL_INT2_GPIO, BOARD_ACCEL_INT2_PIN, &ACCEL_INT2_config);
435
436 gpio_pin_config_t ACCEL_INT1_config = {
437 .pinDirection = kGPIO_DigitalInput,
438 .outputLogic = 0U
439 };
440 /* Initialize GPIO functionality on pin PTC17 (pin D5) */
441 GPIO_PinInit(BOARD_ACCEL_INT1_GPIO, BOARD_ACCEL_INT1_PIN, &ACCEL_INT1_config);
442
443 const port_pin_config_t ACCEL_INT2 = {/* Internal pull-up resistor is enabled */
444 kPORT_PullUp,
445 /* Fast slew rate is configured */
446 kPORT_FastSlewRate,
447 /* Passive filter is disabled */
448 kPORT_PassiveFilterDisable,
449 /* Open drain is disabled */
450 kPORT_OpenDrainDisable,
451 /* Low drive strength is configured */
452 kPORT_LowDriveStrength,
453 /* Pin is configured as PTC13 */
454 kPORT_MuxAsGpio,
455 /* Pin Control Register fields [15:0] are not locked */
456 kPORT_UnlockRegister};
457 /* PORTC13 (pin D6) is configured as PTC13 */
458 PORT_SetPinConfig(BOARD_ACCEL_INT2_PORT, BOARD_ACCEL_INT2_PIN, &ACCEL_INT2);
459
460 const port_pin_config_t ACCEL_INT1 = {/* Internal pull-up resistor is enabled */
461 kPORT_PullUp,
462 /* Fast slew rate is configured */
463 kPORT_FastSlewRate,
464 /* Passive filter is disabled */
465 kPORT_PassiveFilterDisable,
466 /* Open drain is disabled */
467 kPORT_OpenDrainDisable,
468 /* Low drive strength is configured */
469 kPORT_LowDriveStrength,
470 /* Pin is configured as PTC17 */
471 kPORT_MuxAsGpio,
472 /* Pin Control Register fields [15:0] are not locked */
473 kPORT_UnlockRegister};
474 /* PORTC17 (pin D5) is configured as PTC17 */
475 PORT_SetPinConfig(BOARD_ACCEL_INT1_PORT, BOARD_ACCEL_INT1_PIN, &ACCEL_INT1);
476 /* Configure digital filter */
477 PORT_EnablePinsDigitalFilter(
478 /* Digital filter is configured on port D */
479 PORTD,
480 /* Digital filter is configured for PORTD0 */
481 PORT_DFER_DFE_8_MASK
482 /* Digital filter is configured for PORTD1 */
483 | PORT_DFER_DFE_9_MASK,
484 /* Disable digital filter */
485 false);
486
487 const port_pin_config_t ACCEL_SCL = {/* Internal pull-up/down resistor is disabled */
488 kPORT_PullDisable,
489 /* Fast slew rate is configured */
490 kPORT_FastSlewRate,
491 /* Passive filter is disabled */
492 kPORT_PassiveFilterDisable,
493 /* Open drain is enabled */
494 kPORT_OpenDrainEnable,
495 /* Low drive strength is configured */
496 kPORT_LowDriveStrength,
497 /* Pin is configured as I2C0_SCL */
498 kPORT_MuxAlt2,
499 /* Pin Control Register fields [15:0] are not locked */
500 kPORT_UnlockRegister};
501 /* PORTD8 (pin C9) is configured as I2C0_SCL */
502 PORT_SetPinConfig(BOARD_ACCEL_SCL_PORT, BOARD_ACCEL_SCL_PIN, &ACCEL_SCL);
503
504 const port_pin_config_t ACCEL_SDA = {/* Internal pull-up/down resistor is disabled */
505 kPORT_PullDisable,
506 /* Fast slew rate is configured */
507 kPORT_FastSlewRate,
508 /* Passive filter is disabled */
509 kPORT_PassiveFilterDisable,
510 /* Open drain is enabled */
511 kPORT_OpenDrainEnable,
512 /* Low drive strength is configured */
513 kPORT_LowDriveStrength,
514 /* Pin is configured as I2C0_SDA */
515 kPORT_MuxAlt2,
516 /* Pin Control Register fields [15:0] are not locked */
517 kPORT_UnlockRegister};
518 /* PORTD9 (pin B9) is configured as I2C0_SDA */
519 PORT_SetPinConfig(BOARD_ACCEL_SDA_PORT, BOARD_ACCEL_SDA_PIN, &ACCEL_SDA);
520 }
521
522 /* clang-format off */
523 /*
524 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
525 BOARD_InitGYRO_I2CPins:
526 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
527 - pin_list:
528 - {pin_num: B9, peripheral: I2C0, signal: SDA, pin_signal: PTD9/I2C0_SDA/LPUART0_TX/FB_A17, identifier: GYRO_SDA, slew_rate: fast, open_drain: enable, pull_select: down,
529 pull_enable: disable, digital_filter: disable}
530 - {pin_num: C9, peripheral: I2C0, signal: SCL, pin_signal: PTD8/LLWU_P24/I2C0_SCL/LPUART0_RX/FB_A16, identifier: GYRO_SCL, slew_rate: fast, open_drain: enable,
531 pull_select: down, pull_enable: disable, digital_filter: disable}
532 - {pin_num: H11, peripheral: GPIOA, signal: 'GPIO, 29', pin_signal: PTA29/MII0_COL/FB_A24, direction: INPUT, slew_rate: fast, open_drain: enable, pull_select: up,
533 pull_enable: enable}
534 - {pin_num: H12, peripheral: GPIOA, signal: 'GPIO, 28', pin_signal: PTA28/MII0_TXER/FB_A25, direction: INPUT, slew_rate: fast, open_drain: enable, pull_select: up,
535 pull_enable: enable}
536 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
537 */
538 /* clang-format on */
539
540 /* FUNCTION ************************************************************************************************************
541 *
542 * Function Name : BOARD_InitGYRO_I2CPins
543 * Description : Configures pin routing and optionally pin electrical features.
544 *
545 * END ****************************************************************************************************************/
BOARD_InitGYRO_I2CPins(void)546 void BOARD_InitGYRO_I2CPins(void)
547 {
548 /* Port A Clock Gate Control: Clock enabled */
549 CLOCK_EnableClock(kCLOCK_PortA);
550 /* Port D Clock Gate Control: Clock enabled */
551 CLOCK_EnableClock(kCLOCK_PortD);
552
553 gpio_pin_config_t GYRO_INT2_config = {
554 .pinDirection = kGPIO_DigitalInput,
555 .outputLogic = 0U
556 };
557 /* Initialize GPIO functionality on pin PTA28 (pin H12) */
558 GPIO_PinInit(BOARD_GYRO_INT2_GPIO, BOARD_GYRO_INT2_PIN, &GYRO_INT2_config);
559
560 gpio_pin_config_t GYRO_INT1_config = {
561 .pinDirection = kGPIO_DigitalInput,
562 .outputLogic = 0U
563 };
564 /* Initialize GPIO functionality on pin PTA29 (pin H11) */
565 GPIO_PinInit(BOARD_GYRO_INT1_GPIO, BOARD_GYRO_INT1_PIN, &GYRO_INT1_config);
566
567 const port_pin_config_t GYRO_INT2 = {/* Internal pull-up resistor is enabled */
568 kPORT_PullUp,
569 /* Fast slew rate is configured */
570 kPORT_FastSlewRate,
571 /* Passive filter is disabled */
572 kPORT_PassiveFilterDisable,
573 /* Open drain is enabled */
574 kPORT_OpenDrainEnable,
575 /* Low drive strength is configured */
576 kPORT_LowDriveStrength,
577 /* Pin is configured as PTA28 */
578 kPORT_MuxAsGpio,
579 /* Pin Control Register fields [15:0] are not locked */
580 kPORT_UnlockRegister};
581 /* PORTA28 (pin H12) is configured as PTA28 */
582 PORT_SetPinConfig(BOARD_GYRO_INT2_PORT, BOARD_GYRO_INT2_PIN, &GYRO_INT2);
583
584 const port_pin_config_t GYRO_INT1 = {/* Internal pull-up resistor is enabled */
585 kPORT_PullUp,
586 /* Fast slew rate is configured */
587 kPORT_FastSlewRate,
588 /* Passive filter is disabled */
589 kPORT_PassiveFilterDisable,
590 /* Open drain is enabled */
591 kPORT_OpenDrainEnable,
592 /* Low drive strength is configured */
593 kPORT_LowDriveStrength,
594 /* Pin is configured as PTA29 */
595 kPORT_MuxAsGpio,
596 /* Pin Control Register fields [15:0] are not locked */
597 kPORT_UnlockRegister};
598 /* PORTA29 (pin H11) is configured as PTA29 */
599 PORT_SetPinConfig(BOARD_GYRO_INT1_PORT, BOARD_GYRO_INT1_PIN, &GYRO_INT1);
600 /* Configure digital filter */
601 PORT_EnablePinsDigitalFilter(
602 /* Digital filter is configured on port D */
603 PORTD,
604 /* Digital filter is configured for PORTD0 */
605 PORT_DFER_DFE_8_MASK
606 /* Digital filter is configured for PORTD1 */
607 | PORT_DFER_DFE_9_MASK,
608 /* Disable digital filter */
609 false);
610
611 const port_pin_config_t GYRO_SCL = {/* Internal pull-up/down resistor is disabled */
612 kPORT_PullDisable,
613 /* Fast slew rate is configured */
614 kPORT_FastSlewRate,
615 /* Passive filter is disabled */
616 kPORT_PassiveFilterDisable,
617 /* Open drain is enabled */
618 kPORT_OpenDrainEnable,
619 /* Low drive strength is configured */
620 kPORT_LowDriveStrength,
621 /* Pin is configured as I2C0_SCL */
622 kPORT_MuxAlt2,
623 /* Pin Control Register fields [15:0] are not locked */
624 kPORT_UnlockRegister};
625 /* PORTD8 (pin C9) is configured as I2C0_SCL */
626 PORT_SetPinConfig(BOARD_GYRO_SCL_PORT, BOARD_GYRO_SCL_PIN, &GYRO_SCL);
627
628 const port_pin_config_t GYRO_SDA = {/* Internal pull-up/down resistor is disabled */
629 kPORT_PullDisable,
630 /* Fast slew rate is configured */
631 kPORT_FastSlewRate,
632 /* Passive filter is disabled */
633 kPORT_PassiveFilterDisable,
634 /* Open drain is enabled */
635 kPORT_OpenDrainEnable,
636 /* Low drive strength is configured */
637 kPORT_LowDriveStrength,
638 /* Pin is configured as I2C0_SDA */
639 kPORT_MuxAlt2,
640 /* Pin Control Register fields [15:0] are not locked */
641 kPORT_UnlockRegister};
642 /* PORTD9 (pin B9) is configured as I2C0_SDA */
643 PORT_SetPinConfig(BOARD_GYRO_SDA_PORT, BOARD_GYRO_SDA_PIN, &GYRO_SDA);
644 }
645
646 /* clang-format off */
647 /*
648 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
649 BOARD_InitDEBUG_UARTPins:
650 - options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
651 - pin_list:
652 - {pin_num: E10, peripheral: UART0, signal: RX, pin_signal: TSI0_CH9/PTB16/SPI1_SOUT/UART0_RX/FTM_CLKIN0/FB_AD17/SDRAM_D17/EWM_IN/TPM_CLKIN0, slew_rate: fast, open_drain: disable,
653 pull_select: down, pull_enable: disable}
654 - {pin_num: E9, peripheral: UART0, signal: TX, pin_signal: TSI0_CH10/PTB17/SPI1_SIN/UART0_TX/FTM_CLKIN1/FB_AD16/SDRAM_D16/EWM_OUT_b/TPM_CLKIN1, direction: OUTPUT,
655 slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
656 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
657 */
658 /* clang-format on */
659
660 /* FUNCTION ************************************************************************************************************
661 *
662 * Function Name : BOARD_InitDEBUG_UARTPins
663 * Description : Configures pin routing and optionally pin electrical features.
664 *
665 * END ****************************************************************************************************************/
BOARD_InitDEBUG_UARTPins(void)666 void BOARD_InitDEBUG_UARTPins(void)
667 {
668 /* Port B Clock Gate Control: Clock enabled */
669 CLOCK_EnableClock(kCLOCK_PortB);
670
671 const port_pin_config_t DEBUG_UART_RX = {/* Internal pull-up/down resistor is disabled */
672 kPORT_PullDisable,
673 /* Fast slew rate is configured */
674 kPORT_FastSlewRate,
675 /* Passive filter is disabled */
676 kPORT_PassiveFilterDisable,
677 /* Open drain is disabled */
678 kPORT_OpenDrainDisable,
679 /* Low drive strength is configured */
680 kPORT_LowDriveStrength,
681 /* Pin is configured as UART0_RX */
682 kPORT_MuxAlt3,
683 /* Pin Control Register fields [15:0] are not locked */
684 kPORT_UnlockRegister};
685 /* PORTB16 (pin E10) is configured as UART0_RX */
686 PORT_SetPinConfig(BOARD_DEBUG_UART_RX_PORT, BOARD_DEBUG_UART_RX_PIN, &DEBUG_UART_RX);
687
688 const port_pin_config_t DEBUG_UART_TX = {/* Internal pull-up/down resistor is disabled */
689 kPORT_PullDisable,
690 /* Fast slew rate is configured */
691 kPORT_FastSlewRate,
692 /* Passive filter is disabled */
693 kPORT_PassiveFilterDisable,
694 /* Open drain is disabled */
695 kPORT_OpenDrainDisable,
696 /* Low drive strength is configured */
697 kPORT_LowDriveStrength,
698 /* Pin is configured as UART0_TX */
699 kPORT_MuxAlt3,
700 /* Pin Control Register fields [15:0] are not locked */
701 kPORT_UnlockRegister};
702 /* PORTB17 (pin E9) is configured as UART0_TX */
703 PORT_SetPinConfig(BOARD_DEBUG_UART_TX_PORT, BOARD_DEBUG_UART_TX_PIN, &DEBUG_UART_TX);
704
705 SIM->SOPT5 = ((SIM->SOPT5 &
706 /* Mask bits to zero which are setting */
707 (~(SIM_SOPT5_UART0TXSRC_MASK)))
708
709 /* UART 0 transmit data source select: UART0_TX pin. */
710 | SIM_SOPT5_UART0TXSRC(SOPT5_UART0TXSRC_UART_TX));
711 }
712
713 /* clang-format off */
714 /*
715 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
716 BOARD_InitSDHC0Pins:
717 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
718 - pin_list:
719 - {pin_num: E4, peripheral: SDHC, signal: CMD, pin_signal: ADC1_SE7a/PTE3/SPI1_SIN/UART1_RTS_b/SDHC0_CMD/TRACE_D1/SPI1_SOUT, slew_rate: fast, open_drain: disable,
720 pull_select: down, pull_enable: disable}
721 - {pin_num: D2, peripheral: SDHC, signal: 'DATA, 0', pin_signal: ADC1_SE5a/PTE1/LLWU_P0/SPI1_SOUT/UART1_RX/SDHC0_D0/TRACE_D3/I2C1_SCL/SPI1_SIN, slew_rate: fast,
722 open_drain: disable, pull_select: down, pull_enable: disable}
723 - {pin_num: D3, peripheral: SDHC, signal: 'DATA, 1', pin_signal: ADC1_SE4a/PTE0/SPI1_PCS1/UART1_TX/SDHC0_D1/TRACE_CLKOUT/I2C1_SDA/RTC_CLKOUT, slew_rate: fast, open_drain: disable,
724 pull_select: down, pull_enable: disable}
725 - {pin_num: E2, peripheral: SDHC, signal: 'DATA, 2', pin_signal: PTE5/SPI1_PCS2/UART3_RX/SDHC0_D2/FTM3_CH0, slew_rate: fast, open_drain: disable, pull_select: down,
726 pull_enable: disable}
727 - {pin_num: E3, peripheral: SDHC, signal: 'DATA, 3', pin_signal: PTE4/LLWU_P2/SPI1_PCS0/UART3_TX/SDHC0_D3/TRACE_D0, slew_rate: fast, open_drain: disable, pull_select: down,
728 pull_enable: disable}
729 - {pin_num: D1, peripheral: SDHC, signal: DCLK, pin_signal: ADC1_SE6a/PTE2/LLWU_P1/SPI1_SCK/UART1_CTS_b/SDHC0_DCLK/TRACE_D2, slew_rate: fast, open_drain: disable,
730 pull_select: down, pull_enable: disable}
731 - {pin_num: B3, peripheral: GPIOD, signal: 'GPIO, 10', pin_signal: PTD10/LPUART0_RTS_b/FB_A18, direction: INPUT, slew_rate: fast, open_drain: disable, pull_select: up,
732 pull_enable: enable, digital_filter: disable}
733 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
734 */
735 /* clang-format on */
736
737 /* FUNCTION ************************************************************************************************************
738 *
739 * Function Name : BOARD_InitSDHC0Pins
740 * Description : Configures pin routing and optionally pin electrical features.
741 *
742 * END ****************************************************************************************************************/
BOARD_InitSDHC0Pins(void)743 void BOARD_InitSDHC0Pins(void)
744 {
745 /* Port D Clock Gate Control: Clock enabled */
746 CLOCK_EnableClock(kCLOCK_PortD);
747 /* Port E Clock Gate Control: Clock enabled */
748 CLOCK_EnableClock(kCLOCK_PortE);
749
750 gpio_pin_config_t SDCARD_CARD_DETECTION_config = {
751 .pinDirection = kGPIO_DigitalInput,
752 .outputLogic = 0U
753 };
754 /* Initialize GPIO functionality on pin PTD10 (pin B3) */
755 GPIO_PinInit(BOARD_SDCARD_CARD_DETECTION_GPIO, BOARD_SDCARD_CARD_DETECTION_PIN, &SDCARD_CARD_DETECTION_config);
756 /* Configure digital filter */
757 PORT_EnablePinsDigitalFilter(
758 /* Digital filter is configured on port D */
759 PORTD,
760 /* Digital filter is configured for PORTD0 */
761 PORT_DFER_DFE_10_MASK,
762 /* Disable digital filter */
763 false);
764
765 const port_pin_config_t SDCARD_CARD_DETECTION = {/* Internal pull-up resistor is enabled */
766 kPORT_PullUp,
767 /* Fast slew rate is configured */
768 kPORT_FastSlewRate,
769 /* Passive filter is disabled */
770 kPORT_PassiveFilterDisable,
771 /* Open drain is disabled */
772 kPORT_OpenDrainDisable,
773 /* Low drive strength is configured */
774 kPORT_LowDriveStrength,
775 /* Pin is configured as PTD10 */
776 kPORT_MuxAsGpio,
777 /* Pin Control Register fields [15:0] are not locked */
778 kPORT_UnlockRegister};
779 /* PORTD10 (pin B3) is configured as PTD10 */
780 PORT_SetPinConfig(BOARD_SDCARD_CARD_DETECTION_PORT, BOARD_SDCARD_CARD_DETECTION_PIN, &SDCARD_CARD_DETECTION);
781
782 const port_pin_config_t SDHC0_D1 = {/* Internal pull-up/down resistor is disabled */
783 kPORT_PullDisable,
784 /* Fast slew rate is configured */
785 kPORT_FastSlewRate,
786 /* Passive filter is disabled */
787 kPORT_PassiveFilterDisable,
788 /* Open drain is disabled */
789 kPORT_OpenDrainDisable,
790 /* Low drive strength is configured */
791 kPORT_LowDriveStrength,
792 /* Pin is configured as SDHC0_D1 */
793 kPORT_MuxAlt4,
794 /* Pin Control Register fields [15:0] are not locked */
795 kPORT_UnlockRegister};
796 /* PORTE0 (pin D3) is configured as SDHC0_D1 */
797 PORT_SetPinConfig(BOARD_SDHC0_D1_PORT, BOARD_SDHC0_D1_PIN, &SDHC0_D1);
798
799 const port_pin_config_t SDHC0_D0 = {/* Internal pull-up/down resistor is disabled */
800 kPORT_PullDisable,
801 /* Fast slew rate is configured */
802 kPORT_FastSlewRate,
803 /* Passive filter is disabled */
804 kPORT_PassiveFilterDisable,
805 /* Open drain is disabled */
806 kPORT_OpenDrainDisable,
807 /* Low drive strength is configured */
808 kPORT_LowDriveStrength,
809 /* Pin is configured as SDHC0_D0 */
810 kPORT_MuxAlt4,
811 /* Pin Control Register fields [15:0] are not locked */
812 kPORT_UnlockRegister};
813 /* PORTE1 (pin D2) is configured as SDHC0_D0 */
814 PORT_SetPinConfig(BOARD_SDHC0_D0_PORT, BOARD_SDHC0_D0_PIN, &SDHC0_D0);
815
816 const port_pin_config_t SDHC0_DCLK = {/* Internal pull-up/down resistor is disabled */
817 kPORT_PullDisable,
818 /* Fast slew rate is configured */
819 kPORT_FastSlewRate,
820 /* Passive filter is disabled */
821 kPORT_PassiveFilterDisable,
822 /* Open drain is disabled */
823 kPORT_OpenDrainDisable,
824 /* Low drive strength is configured */
825 kPORT_LowDriveStrength,
826 /* Pin is configured as SDHC0_DCLK */
827 kPORT_MuxAlt4,
828 /* Pin Control Register fields [15:0] are not locked */
829 kPORT_UnlockRegister};
830 /* PORTE2 (pin D1) is configured as SDHC0_DCLK */
831 PORT_SetPinConfig(BOARD_SDHC0_DCLK_PORT, BOARD_SDHC0_DCLK_PIN, &SDHC0_DCLK);
832
833 const port_pin_config_t SDHC0_CMD = {/* Internal pull-up/down resistor is disabled */
834 kPORT_PullDisable,
835 /* Fast slew rate is configured */
836 kPORT_FastSlewRate,
837 /* Passive filter is disabled */
838 kPORT_PassiveFilterDisable,
839 /* Open drain is disabled */
840 kPORT_OpenDrainDisable,
841 /* Low drive strength is configured */
842 kPORT_LowDriveStrength,
843 /* Pin is configured as SDHC0_CMD */
844 kPORT_MuxAlt4,
845 /* Pin Control Register fields [15:0] are not locked */
846 kPORT_UnlockRegister};
847 /* PORTE3 (pin E4) is configured as SDHC0_CMD */
848 PORT_SetPinConfig(BOARD_SDHC0_CMD_PORT, BOARD_SDHC0_CMD_PIN, &SDHC0_CMD);
849
850 const port_pin_config_t SDHC0_D3 = {/* Internal pull-up/down resistor is disabled */
851 kPORT_PullDisable,
852 /* Fast slew rate is configured */
853 kPORT_FastSlewRate,
854 /* Passive filter is disabled */
855 kPORT_PassiveFilterDisable,
856 /* Open drain is disabled */
857 kPORT_OpenDrainDisable,
858 /* Low drive strength is configured */
859 kPORT_LowDriveStrength,
860 /* Pin is configured as SDHC0_D3 */
861 kPORT_MuxAlt4,
862 /* Pin Control Register fields [15:0] are not locked */
863 kPORT_UnlockRegister};
864 /* PORTE4 (pin E3) is configured as SDHC0_D3 */
865 PORT_SetPinConfig(BOARD_SDHC0_D3_PORT, BOARD_SDHC0_D3_PIN, &SDHC0_D3);
866
867 const port_pin_config_t SDHC0_D2 = {/* Internal pull-up/down resistor is disabled */
868 kPORT_PullDisable,
869 /* Fast slew rate is configured */
870 kPORT_FastSlewRate,
871 /* Passive filter is disabled */
872 kPORT_PassiveFilterDisable,
873 /* Open drain is disabled */
874 kPORT_OpenDrainDisable,
875 /* Low drive strength is configured */
876 kPORT_LowDriveStrength,
877 /* Pin is configured as SDHC0_D2 */
878 kPORT_MuxAlt4,
879 /* Pin Control Register fields [15:0] are not locked */
880 kPORT_UnlockRegister};
881 /* PORTE5 (pin E2) is configured as SDHC0_D2 */
882 PORT_SetPinConfig(BOARD_SDHC0_D2_PORT, BOARD_SDHC0_D2_PIN, &SDHC0_D2);
883 }
884
885 /* clang-format off */
886 /*
887 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
888 BOARD_InitENETPins:
889 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
890 - pin_list:
891 - {pin_num: K4, peripheral: ENET, signal: RMII_CLKIN, pin_signal: PTE26/ENET_1588_CLKIN/UART4_CTS_b/RTC_CLKOUT/USB0_CLKIN, identifier: ETHERNET_CLOCK, slew_rate: fast,
892 open_drain: disable, pull_select: down, pull_enable: disable}
893 - {pin_num: L10, peripheral: ENET, signal: RMII_CRS_DV, pin_signal: PTA14/SPI0_PCS0/UART0_TX/RMII0_CRS_DV/MII0_RXDV/I2C2_SCL/I2S0_RX_BCLK/I2S0_TXD1, slew_rate: fast,
894 open_drain: disable, pull_select: down, pull_enable: disable}
895 - {pin_num: H9, peripheral: ENET, signal: RMII_MDC, pin_signal: ADC0_SE9/ADC1_SE9/TSI0_CH6/PTB1/I2C0_SDA/FTM1_CH1/RMII0_MDC/MII0_MDC/SDRAM_RAS_b/FTM1_QD_PHB/TPM1_CH1,
896 slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable}
897 - {pin_num: H10, peripheral: ENET, signal: RMII_MDIO, pin_signal: ADC0_SE8/ADC1_SE8/TSI0_CH0/PTB0/LLWU_P5/I2C0_SCL/FTM1_CH0/RMII0_MDIO/MII0_MDIO/SDRAM_CAS_b/FTM1_QD_PHA/TPM1_CH0,
898 slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable}
899 - {pin_num: J9, peripheral: ENET, signal: RMII_RXD0, pin_signal: CMP2_IN1/PTA13/LLWU_P4/CAN0_RX/FTM1_CH1/RMII0_RXD0/MII0_RXD0/I2C2_SDA/I2S0_TX_FS/FTM1_QD_PHB/TPM1_CH1,
900 slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
901 - {pin_num: K9, peripheral: ENET, signal: RMII_RXD1, pin_signal: CMP2_IN0/PTA12/CAN0_TX/FTM1_CH0/RMII0_RXD1/MII0_RXD1/I2C2_SCL/I2S0_TXD0/FTM1_QD_PHA/TPM1_CH0, slew_rate: fast,
902 open_drain: disable, pull_select: down, pull_enable: disable}
903 - {pin_num: M8, peripheral: ENET, signal: RMII_RXER, pin_signal: PTA5/USB0_CLKIN/FTM0_CH2/RMII0_RXER/MII0_RXER/CMP2_OUT/I2S0_TX_BCLK/JTAG_TRST_b, slew_rate: fast,
904 open_drain: disable, pull_select: down, pull_enable: disable}
905 - {pin_num: K10, peripheral: ENET, signal: RMII_TXD0, pin_signal: CMP3_IN2/PTA16/SPI0_SOUT/UART0_CTS_b/UART0_COL_b/RMII0_TXD0/MII0_TXD0/I2S0_RX_FS/I2S0_RXD1, slew_rate: fast,
906 open_drain: disable, pull_select: down, pull_enable: disable}
907 - {pin_num: K11, peripheral: ENET, signal: RMII_TXD1, pin_signal: ADC1_SE17/PTA17/SPI0_SIN/UART0_RTS_b/RMII0_TXD1/MII0_TXD1/I2S0_MCLK, slew_rate: fast, open_drain: disable,
908 pull_select: down, pull_enable: disable}
909 - {pin_num: L11, peripheral: ENET, signal: RMII_TXEN, pin_signal: CMP3_IN1/PTA15/SPI0_SCK/UART0_RX/RMII0_TXEN/MII0_TXEN/I2S0_RXD0, slew_rate: fast, open_drain: disable,
910 pull_select: down, pull_enable: disable}
911 - {pin_num: K4, peripheral: ENET, signal: CLKIN_1588, pin_signal: PTE26/ENET_1588_CLKIN/UART4_CTS_b/RTC_CLKOUT/USB0_CLKIN, identifier: ENET_1588_CLKIN, slew_rate: fast,
912 open_drain: disable, pull_select: down, pull_enable: disable}
913 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
914 */
915 /* clang-format on */
916
917 /* FUNCTION ************************************************************************************************************
918 *
919 * Function Name : BOARD_InitENETPins
920 * Description : Configures pin routing and optionally pin electrical features.
921 *
922 * END ****************************************************************************************************************/
BOARD_InitENETPins(void)923 void BOARD_InitENETPins(void)
924 {
925 /* Port A Clock Gate Control: Clock enabled */
926 CLOCK_EnableClock(kCLOCK_PortA);
927 /* Port B Clock Gate Control: Clock enabled */
928 CLOCK_EnableClock(kCLOCK_PortB);
929 /* Port E Clock Gate Control: Clock enabled */
930 CLOCK_EnableClock(kCLOCK_PortE);
931
932 const port_pin_config_t RMII0_RXD1 = {/* Internal pull-up/down resistor is disabled */
933 kPORT_PullDisable,
934 /* Fast slew rate is configured */
935 kPORT_FastSlewRate,
936 /* Passive filter is disabled */
937 kPORT_PassiveFilterDisable,
938 /* Open drain is disabled */
939 kPORT_OpenDrainDisable,
940 /* Low drive strength is configured */
941 kPORT_LowDriveStrength,
942 /* Pin is configured as RMII0_RXD1 */
943 kPORT_MuxAlt4,
944 /* Pin Control Register fields [15:0] are not locked */
945 kPORT_UnlockRegister};
946 /* PORTA12 (pin K9) is configured as RMII0_RXD1 */
947 PORT_SetPinConfig(BOARD_RMII0_RXD1_PORT, BOARD_RMII0_RXD1_PIN, &RMII0_RXD1);
948
949 const port_pin_config_t RMII0_RXD0 = {/* Internal pull-up/down resistor is disabled */
950 kPORT_PullDisable,
951 /* Fast slew rate is configured */
952 kPORT_FastSlewRate,
953 /* Passive filter is disabled */
954 kPORT_PassiveFilterDisable,
955 /* Open drain is disabled */
956 kPORT_OpenDrainDisable,
957 /* Low drive strength is configured */
958 kPORT_LowDriveStrength,
959 /* Pin is configured as RMII0_RXD0 */
960 kPORT_MuxAlt4,
961 /* Pin Control Register fields [15:0] are not locked */
962 kPORT_UnlockRegister};
963 /* PORTA13 (pin J9) is configured as RMII0_RXD0 */
964 PORT_SetPinConfig(BOARD_RMII0_RXD0_PORT, BOARD_RMII0_RXD0_PIN, &RMII0_RXD0);
965
966 const port_pin_config_t RMII0_CRS_DV = {/* Internal pull-up/down resistor is disabled */
967 kPORT_PullDisable,
968 /* Fast slew rate is configured */
969 kPORT_FastSlewRate,
970 /* Passive filter is disabled */
971 kPORT_PassiveFilterDisable,
972 /* Open drain is disabled */
973 kPORT_OpenDrainDisable,
974 /* Low drive strength is configured */
975 kPORT_LowDriveStrength,
976 /* Pin is configured as RMII0_CRS_DV */
977 kPORT_MuxAlt4,
978 /* Pin Control Register fields [15:0] are not locked */
979 kPORT_UnlockRegister};
980 /* PORTA14 (pin L10) is configured as RMII0_CRS_DV */
981 PORT_SetPinConfig(BOARD_RMII0_CRS_DV_PORT, BOARD_RMII0_CRS_DV_PIN, &RMII0_CRS_DV);
982
983 const port_pin_config_t RMII0_TXEN = {/* Internal pull-up/down resistor is disabled */
984 kPORT_PullDisable,
985 /* Fast slew rate is configured */
986 kPORT_FastSlewRate,
987 /* Passive filter is disabled */
988 kPORT_PassiveFilterDisable,
989 /* Open drain is disabled */
990 kPORT_OpenDrainDisable,
991 /* Low drive strength is configured */
992 kPORT_LowDriveStrength,
993 /* Pin is configured as RMII0_TXEN */
994 kPORT_MuxAlt4,
995 /* Pin Control Register fields [15:0] are not locked */
996 kPORT_UnlockRegister};
997 /* PORTA15 (pin L11) is configured as RMII0_TXEN */
998 PORT_SetPinConfig(BOARD_RMII0_TXEN_PORT, BOARD_RMII0_TXEN_PIN, &RMII0_TXEN);
999
1000 const port_pin_config_t RMII0_TXD_0 = {/* Internal pull-up/down resistor is disabled */
1001 kPORT_PullDisable,
1002 /* Fast slew rate is configured */
1003 kPORT_FastSlewRate,
1004 /* Passive filter is disabled */
1005 kPORT_PassiveFilterDisable,
1006 /* Open drain is disabled */
1007 kPORT_OpenDrainDisable,
1008 /* Low drive strength is configured */
1009 kPORT_LowDriveStrength,
1010 /* Pin is configured as RMII0_TXD0 */
1011 kPORT_MuxAlt4,
1012 /* Pin Control Register fields [15:0] are not locked */
1013 kPORT_UnlockRegister};
1014 /* PORTA16 (pin K10) is configured as RMII0_TXD0 */
1015 PORT_SetPinConfig(BOARD_RMII0_TXD_0_PORT, BOARD_RMII0_TXD_0_PIN, &RMII0_TXD_0);
1016
1017 const port_pin_config_t RMII0_TXD_1 = {/* Internal pull-up/down resistor is disabled */
1018 kPORT_PullDisable,
1019 /* Fast slew rate is configured */
1020 kPORT_FastSlewRate,
1021 /* Passive filter is disabled */
1022 kPORT_PassiveFilterDisable,
1023 /* Open drain is disabled */
1024 kPORT_OpenDrainDisable,
1025 /* Low drive strength is configured */
1026 kPORT_LowDriveStrength,
1027 /* Pin is configured as RMII0_TXD1 */
1028 kPORT_MuxAlt4,
1029 /* Pin Control Register fields [15:0] are not locked */
1030 kPORT_UnlockRegister};
1031 /* PORTA17 (pin K11) is configured as RMII0_TXD1 */
1032 PORT_SetPinConfig(BOARD_RMII0_TXD_1_PORT, BOARD_RMII0_TXD_1_PIN, &RMII0_TXD_1);
1033
1034 const port_pin_config_t RMII0_RXER = {/* Internal pull-up/down resistor is disabled */
1035 kPORT_PullDisable,
1036 /* Fast slew rate is configured */
1037 kPORT_FastSlewRate,
1038 /* Passive filter is disabled */
1039 kPORT_PassiveFilterDisable,
1040 /* Open drain is disabled */
1041 kPORT_OpenDrainDisable,
1042 /* Low drive strength is configured */
1043 kPORT_LowDriveStrength,
1044 /* Pin is configured as RMII0_RXER */
1045 kPORT_MuxAlt4,
1046 /* Pin Control Register fields [15:0] are not locked */
1047 kPORT_UnlockRegister};
1048 /* PORTA5 (pin M8) is configured as RMII0_RXER */
1049 PORT_SetPinConfig(BOARD_RMII0_RXER_PORT, BOARD_RMII0_RXER_PIN, &RMII0_RXER);
1050
1051 const port_pin_config_t RMII0_MDIO = {/* Internal pull-up/down resistor is disabled */
1052 kPORT_PullDisable,
1053 /* Fast slew rate is configured */
1054 kPORT_FastSlewRate,
1055 /* Passive filter is disabled */
1056 kPORT_PassiveFilterDisable,
1057 /* Open drain is disabled */
1058 kPORT_OpenDrainDisable,
1059 /* Low drive strength is configured */
1060 kPORT_LowDriveStrength,
1061 /* Pin is configured as RMII0_MDIO */
1062 kPORT_MuxAlt4,
1063 /* Pin Control Register fields [15:0] are not locked */
1064 kPORT_UnlockRegister};
1065 /* PORTB0 (pin H10) is configured as RMII0_MDIO */
1066 PORT_SetPinConfig(BOARD_RMII0_MDIO_PORT, BOARD_RMII0_MDIO_PIN, &RMII0_MDIO);
1067
1068 const port_pin_config_t RMII0_MDC = {/* Internal pull-up/down resistor is disabled */
1069 kPORT_PullDisable,
1070 /* Fast slew rate is configured */
1071 kPORT_FastSlewRate,
1072 /* Passive filter is disabled */
1073 kPORT_PassiveFilterDisable,
1074 /* Open drain is disabled */
1075 kPORT_OpenDrainDisable,
1076 /* Low drive strength is configured */
1077 kPORT_LowDriveStrength,
1078 /* Pin is configured as RMII0_MDC */
1079 kPORT_MuxAlt4,
1080 /* Pin Control Register fields [15:0] are not locked */
1081 kPORT_UnlockRegister};
1082 /* PORTB1 (pin H9) is configured as RMII0_MDC */
1083 PORT_SetPinConfig(BOARD_RMII0_MDC_PORT, BOARD_RMII0_MDC_PIN, &RMII0_MDC);
1084
1085 const port_pin_config_t ETHERNET_CLOCK = {/* Internal pull-up/down resistor is disabled */
1086 kPORT_PullDisable,
1087 /* Fast slew rate is configured */
1088 kPORT_FastSlewRate,
1089 /* Passive filter is disabled */
1090 kPORT_PassiveFilterDisable,
1091 /* Open drain is disabled */
1092 kPORT_OpenDrainDisable,
1093 /* Low drive strength is configured */
1094 kPORT_LowDriveStrength,
1095 /* Pin is configured as ENET_1588_CLKIN */
1096 kPORT_MuxAlt2,
1097 /* Pin Control Register fields [15:0] are not locked */
1098 kPORT_UnlockRegister};
1099 /* PORTE26 (pin K4) is configured as ENET_1588_CLKIN */
1100 PORT_SetPinConfig(BOARD_ETHERNET_CLOCK_PORT, BOARD_ETHERNET_CLOCK_PIN, ÐERNET_CLOCK);
1101
1102 SIM->SOPT2 = ((SIM->SOPT2 &
1103 /* Mask bits to zero which are setting */
1104 (~(SIM_SOPT2_RMIISRC_MASK)))
1105
1106 /* RMII clock source select: External bypass clock (ENET_1588_CLKIN). */
1107 | SIM_SOPT2_RMIISRC(SOPT2_RMIISRC_ENET));
1108 }
1109
1110 /* clang-format off */
1111 /*
1112 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
1113 BOARD_InitUSBPins:
1114 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
1115 - pin_list:
1116 - {pin_num: K1, peripheral: USBPHY, signal: DM, pin_signal: USB1_DM/LLWU_P31, identifier: K66_MICRO_USB_DN_PHY}
1117 - {pin_num: J1, peripheral: USBPHY, signal: DP, pin_signal: USB1_DP/LLWU_P30, identifier: K66_MICRO_USB_DP_PHY}
1118 - {pin_num: F1, peripheral: USBPHY, signal: ID, pin_signal: PTE10/LLWU_P18/I2C3_SDA/I2S0_TXD0/LPUART0_CTS_b/FTM3_CH5/USB1_ID, slew_rate: fast, open_drain: disable,
1119 pull_select: down, pull_enable: disable}
1120 - {pin_num: L1, peripheral: USBPHY, signal: VBUS, pin_signal: USB1_VBUS/LLWU_P29}
1121 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
1122 */
1123 /* clang-format on */
1124
1125 /* FUNCTION ************************************************************************************************************
1126 *
1127 * Function Name : BOARD_InitUSBPins
1128 * Description : Configures pin routing and optionally pin electrical features.
1129 *
1130 * END ****************************************************************************************************************/
BOARD_InitUSBPins(void)1131 void BOARD_InitUSBPins(void)
1132 {
1133 /* Port E Clock Gate Control: Clock enabled */
1134 CLOCK_EnableClock(kCLOCK_PortE);
1135
1136 const port_pin_config_t USB_ID = {/* Internal pull-up/down resistor is disabled */
1137 kPORT_PullDisable,
1138 /* Fast slew rate is configured */
1139 kPORT_FastSlewRate,
1140 /* Passive filter is disabled */
1141 kPORT_PassiveFilterDisable,
1142 /* Open drain is disabled */
1143 kPORT_OpenDrainDisable,
1144 /* Low drive strength is configured */
1145 kPORT_LowDriveStrength,
1146 /* Pin is configured as USB1_ID */
1147 kPORT_MuxAlt7,
1148 /* Pin Control Register fields [15:0] are not locked */
1149 kPORT_UnlockRegister};
1150 /* PORTE10 (pin F1) is configured as USB1_ID */
1151 PORT_SetPinConfig(BOARD_USB_ID_PORT, BOARD_USB_ID_PIN, &USB_ID);
1152 }
1153
1154 /* clang-format off */
1155 /*
1156 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
1157 BOARD_InitOSCsPins:
1158 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
1159 - pin_list:
1160 - {pin_num: M12, peripheral: OSC, signal: EXTAL0, pin_signal: EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0/TPM_CLKIN0, slew_rate: no_init, open_drain: no_init, pull_select: no_init,
1161 pull_enable: no_init}
1162 - {pin_num: M11, peripheral: OSC, signal: XTAL0, pin_signal: XTAL0/PTA19/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1/TPM_CLKIN1, slew_rate: no_init, open_drain: no_init, pull_select: no_init,
1163 pull_enable: no_init}
1164 - {pin_num: M6, peripheral: RTC, signal: EXTAL32, pin_signal: EXTAL32}
1165 - {pin_num: M7, peripheral: RTC, signal: XTAL32, pin_signal: XTAL32}
1166 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
1167 */
1168 /* clang-format on */
1169
1170 /* FUNCTION ************************************************************************************************************
1171 *
1172 * Function Name : BOARD_InitOSCsPins
1173 * Description : Configures pin routing and optionally pin electrical features.
1174 *
1175 * END ****************************************************************************************************************/
BOARD_InitOSCsPins(void)1176 void BOARD_InitOSCsPins(void)
1177 {
1178 /* Port A Clock Gate Control: Clock enabled */
1179 CLOCK_EnableClock(kCLOCK_PortA);
1180
1181 /* PORTA18 (pin M12) is configured as EXTAL0 */
1182 PORT_SetPinMux(BOARD_EXTAL0_PORT, BOARD_EXTAL0_PIN, kPORT_PinDisabledOrAnalog);
1183
1184 /* PORTA19 (pin M11) is configured as XTAL0 */
1185 PORT_SetPinMux(BOARD_XTAL0_PORT, BOARD_XTAL0_PIN, kPORT_PinDisabledOrAnalog);
1186 }
1187 /***********************************************************************************************************************
1188 * EOF
1189 **********************************************************************************************************************/
1190
