1 /*
2 * Copyright 2018-2019 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /* clang-format off */
9 /*
10 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
11 !!GlobalInfo
12 product: Pins v5.0
13 processor: MK22FN512xxx12
14 package_id: MK22FN512VLH12
15 mcu_data: ksdk2_0
16 processor_version: 0.0.18
17 board: FRDM-K22F
18 pin_labels:
19 - {pin_num: '22', pin_signal: PTA0/UART0_CTS_b/FTM0_CH5/JTAG_TCLK/SWD_CLK/EZP_CLK, label: 'J11[4]/SWD_CLK_TGTMCU'}
20 - {pin_num: '23', pin_signal: PTA1/UART0_RX/FTM0_CH6/JTAG_TDI/EZP_DI, label: 'J2[4]/RED_LED', identifier: LEDRGB_RED}
21 - {pin_num: '24', pin_signal: PTA2/UART0_TX/FTM0_CH7/JTAG_TDO/TRACE_SWO/EZP_DO, label: 'J1[8]/GREEN_LED', identifier: LEDRGB_GREEN}
22 - {pin_num: '25', pin_signal: PTA3/UART0_RTS_b/FTM0_CH0/JTAG_TMS/SWD_DIO, label: 'J11[2]/SWD_DIO_TGTMCU'}
23 - {pin_num: '26', pin_signal: PTA4/LLWU_P3/FTM0_CH1/NMI_b/EZP_CS_b, label: 'J1[10]/LLWU_P3'}
24 - {pin_num: '27', pin_signal: PTA5/USB_CLKIN/FTM0_CH2/I2S0_TX_BCLK/JTAG_TRST_b, label: 'J1[1]/I2S0_TX_BCLK', identifier: AC_I2S_SCLK;USB_CLKIN}
25 - {pin_num: '28', pin_signal: PTA12/FTM1_CH0/I2S0_TXD0/FTM1_QD_PHA, label: 'J1[5]/I2S0_TXD0', identifier: AC_I2S_DIN}
26 - {pin_num: '29', pin_signal: PTA13/LLWU_P4/FTM1_CH1/I2S0_TX_FS/FTM1_QD_PHB, label: 'J1[3]', identifier: AC_I2S_LRCLK}
27 - {pin_num: '32', pin_signal: EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0, label: 'Y1[3]/EXTAL', identifier: EXTAL0}
28 - {pin_num: '33', pin_signal: XTAL0/PTA19/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1, label: 'Y1[1]/XTAL', identifier: XTAL0}
29 - {pin_num: '35', pin_signal: ADC0_SE8/ADC1_SE8/PTB0/LLWU_P5/I2C0_SCL/FTM1_CH0/FTM1_QD_PHA, label: 'J24[2]/LLWU_P5'}
30 - {pin_num: '36', pin_signal: ADC0_SE9/ADC1_SE9/PTB1/I2C0_SDA/FTM1_CH1/FTM1_QD_PHB, label: 'J24[4]'}
31 - {pin_num: '37', pin_signal: ADC0_SE12/PTB2/I2C0_SCL/UART0_RTS_b/FTM0_FLT3, label: 'J24[12]/U8[4]/ADC0_SE12/I2C0_SCL/AUD/ACCEL_I2C/POT_5K', identifier: ACCEL_SCL;AUDIO_SCL;POT_5K}
32 - {pin_num: '38', pin_signal: ADC0_SE13/PTB3/I2C0_SDA/UART0_CTS_b/FTM0_FLT0, label: 'J24[10]/U8[6]/ADC0_SE13/I2C0_SDA/AUD/ACCEL_I2C', identifier: ACCEL_SDA;AUDIO_SDA}
33 - {pin_num: '39', pin_signal: PTB16/SPI1_SOUT/UART0_RX/FTM_CLKIN0/FB_AD17/EWM_IN, label: 'J1[6]/J8[G1]/SD_CARD_DETECT', identifier: SD_CARD_DETECT}
34 - {pin_num: '40', pin_signal: PTB17/SPI1_SIN/UART0_TX/FTM_CLKIN1/FB_AD16/EWM_OUT_b, label: PUSH_BUTTON1, identifier: SW3}
35 - {pin_num: '41', pin_signal: PTB18/FTM2_CH0/I2S0_TX_BCLK/FB_AD15/FTM2_QD_PHA, label: 'J1[12]'}
36 - {pin_num: '42', pin_signal: PTB19/FTM2_CH1/I2S0_TX_FS/FB_OE_b/FTM2_QD_PHB, label: 'J2[2]'}
37 - {pin_num: '43', pin_signal: ADC0_SE14/PTC0/SPI0_PCS4/PDB0_EXTRG/USB_SOF_OUT/FB_AD14, label: 'J2[5]/U13[3]'}
38 - {pin_num: '44', pin_signal: ADC0_SE15/PTC1/LLWU_P6/SPI0_PCS3/UART1_RTS_b/FTM0_CH0/FB_AD13/I2S0_TXD0/LPUART0_RTS_b, label: 'J24[6]/LLWU_P6/ADC0_SE15/PUSH_BUTTON2',
39 identifier: SW2}
40 - {pin_num: '45', pin_signal: ADC0_SE4b/CMP1_IN0/PTC2/SPI0_PCS2/UART1_CTS_b/FTM0_CH1/FB_AD12/I2S0_TX_FS/LPUART0_CTS_b, label: 'J24[8]'}
41 - {pin_num: '51', pin_signal: CMP0_IN0/PTC6/LLWU_P10/SPI0_SOUT/PDB0_EXTRG/I2S0_RX_BCLK/FB_AD9/I2S0_MCLK, label: 'J1[16]/LLWU_P10'}
42 - {pin_num: '49', pin_signal: PTC4/LLWU_P8/SPI0_PCS0/UART1_TX/FTM0_CH3/FB_AD11/CMP1_OUT/LPUART0_TX, label: 'J8[P2]/J24[9]/uSD_card_CS', identifier: SD_CARD_DAT3}
43 - {pin_num: '50', pin_signal: PTC5/LLWU_P9/SPI0_SCK/LPTMR0_ALT2/I2S0_RXD0/FB_AD10/CMP0_OUT/FTM0_CH2, label: 'J1[15]/I2S0_RXD0', identifier: AC_I2S_DOUT}
44 - {pin_num: '52', pin_signal: CMP0_IN1/PTC7/SPI0_SIN/USB_SOF_OUT/I2S0_RX_FS/FB_AD8, label: 'J1[11]/I2S0_RX_FS'}
45 - {pin_num: '53', pin_signal: ADC1_SE4b/CMP0_IN2/PTC8/FTM3_CH4/I2S0_MCLK/FB_AD7, label: 'J1[7]/I2S0_MCLK', identifier: AC_SYS_MCLK}
46 - {pin_num: '54', pin_signal: ADC1_SE5b/CMP0_IN3/PTC9/FTM3_CH5/I2S0_RX_BCLK/FB_AD6/FTM2_FLT0, label: 'J1[9]/I2S0_RX_BCLK'}
47 - {pin_num: '55', pin_signal: ADC1_SE6b/PTC10/I2C1_SCL/FTM3_CH6/I2S0_RX_FS/FB_AD5, label: 'J1[13]/I2C1_SCL/I2S0_RX_FS'}
48 - {pin_num: '56', pin_signal: ADC1_SE7b/PTC11/LLWU_P11/I2C1_SDA/FTM3_CH7/FB_RW_b, label: 'J2[7]/I2C1_SDA', identifier: RF_CE}
49 - {pin_num: '57', pin_signal: PTD0/LLWU_P12/SPI0_PCS0/UART2_RTS_b/FTM3_CH0/FB_ALE/FB_CS1_b/FB_TS_b/LPUART0_RTS_b, label: 'U8[11]/LLWU_P12/ACCEL_INT1', identifier: ACCEL_INT1;RF_IRQ}
50 - {pin_num: '58', pin_signal: ADC0_SE5b/PTD1/SPI0_SCK/UART2_CTS_b/FTM3_CH1/FB_CS0_b/LPUART0_CTS_b, label: 'U8[9]/J8[P5]/SPI0_SCK/uSD_SPI_CL/ACCEL_INT2', identifier: SD_CARD_CLK;ACCEL_INT2}
51 - {pin_num: '59', pin_signal: PTD2/LLWU_P13/SPI0_SOUT/UART2_RX/FTM3_CH2/FB_AD4/LPUART0_RX/I2C0_SCL, label: 'J1[2]/J8[P3]/uSD_SPI_MOSI', identifier: SD_CARD_CMD}
52 - {pin_num: '60', pin_signal: PTD3/SPI0_SIN/UART2_TX/FTM3_CH3/FB_AD3/LPUART0_TX/I2C0_SDA, label: 'J1[4]/J8[P7]/SPI0_SIN/uSD_SPI_MISO', identifier: SD_CARD_DAT0}
53 - {pin_num: '61', pin_signal: PTD4/LLWU_P14/SPI0_PCS1/UART0_RTS_b/FTM0_CH4/FB_AD2/EWM_IN/SPI1_PCS0, label: 'J2[6]/SPI0_PCS1/LLWU_P14', identifier: RF_CS}
54 - {pin_num: '62', pin_signal: ADC0_SE6b/PTD5/SPI0_PCS2/UART0_CTS_b/FTM0_CH5/FB_AD1/EWM_OUT_b/SPI1_SCK, label: 'J2[12]/BLUE_LED', identifier: LEDRGB_BLUE}
55 - {pin_num: '63', pin_signal: ADC0_SE7b/PTD6/LLWU_P15/SPI0_PCS3/UART0_RX/FTM0_CH6/FB_AD0/FTM0_FLT0/SPI1_SOUT, label: 'J2[8]'}
56 - {pin_num: '64', pin_signal: PTD7/UART0_TX/FTM0_CH7/FTM0_FLT1/SPI1_SIN, label: 'J2[10]'}
57 - {pin_num: '1', pin_signal: ADC1_SE4a/PTE0/CLKOUT32K/SPI1_PCS1/UART1_TX/I2C1_SDA/RTC_CLKOUT, label: 'J2[18]/UART1_TX_TGTMCU', identifier: DEBUG_UART_TX;RTC_CLKOUT;CLKOUT32K}
58 - {pin_num: '2', pin_signal: ADC1_SE5a/PTE1/LLWU_P0/SPI1_SOUT/UART1_RX/I2C1_SCL/SPI1_SIN, label: 'J2[20]/UART1_RX_TGTMCU', identifier: DEBUG_UART_RX}
59 - {pin_num: '4', pin_signal: VSS4, label: GND}
60 - {pin_num: '31', pin_signal: VSS31, label: GND}
61 - {pin_num: '47', pin_signal: VSS47, label: GND}
62 - {pin_num: '16', pin_signal: VSSA, label: VSSA}
63 - {pin_num: '15', pin_signal: VREFL, label: VREFL}
64 - {pin_num: '14', pin_signal: VREFH, label: 'J2[16]/VREFH'}
65 - {pin_num: '19', pin_signal: XTAL32, label: XTAL32_RTC, identifier: XTAL32}
66 - {pin_num: '20', pin_signal: EXTAL32, label: EXTAL32_RTC, identifier: EXTAL32}
67 - {pin_num: '11', pin_signal: ADC1_DP0/ADC0_DP3, label: 'J24[5]/ADC0_DP3/ADC0_SE3/LIGHT_SNSR', identifier: LSENSE_EMITTER}
68 - {pin_num: '18', pin_signal: DAC0_OUT/CMP1_IN3/ADC0_SE23, label: 'J24[11]/DAC0_OUT/ADC0_SE23'}
69 - {pin_num: '12', pin_signal: ADC1_DM0/ADC0_DM3, label: 'J24[7]/ADC0_DM3/ADC0_SE7a'}
70 - {pin_num: '10', pin_signal: ADC0_DM0/ADC1_DM3, label: 'J24[3]/ADC0_DM0/ADC0_SE4a'}
71 - {pin_num: '9', pin_signal: ADC0_DP0/ADC1_DP3, label: 'J24[1]/ADC0_DP0/ADC0_SE0'}
72 - {pin_num: '17', pin_signal: VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18, label: 'J2[1]'}
73 - {pin_num: '21', pin_signal: VBAT, label: VBAT}
74 - {pin_num: '13', pin_signal: VDDA, label: P3V3_K22F}
75 - {pin_num: '30', pin_signal: VDD30, label: P3V3_K22F}
76 - {pin_num: '3', pin_signal: VDD3, label: P3V3_K22F}
77 - {pin_num: '48', pin_signal: VDD48, label: P3V3_K22F}
78 - {pin_num: '7', pin_signal: VOUT33, label: USB_VOUT33, identifier: USB_VOUT33}
79 - {pin_num: '5', pin_signal: USB0_DP, label: USB_DP, identifier: USB_DP}
80 - {pin_num: '6', pin_signal: USB0_DM, label: USB_DN, identifier: USB_DN}
81 - {pin_num: '34', pin_signal: RESET_b, label: 'J11[10]/RST_TGTMCU_b'}
82 - {pin_num: '8', pin_signal: VREGIN, label: P5V_K22F, identifier: USB_VREGIN}
83 - {pin_num: '46', pin_signal: CMP1_IN1/PTC3/LLWU_P7/SPI0_PCS1/UART1_RX/FTM0_CH2/CLKOUT/I2S0_TX_BCLK/LPUART0_RX, label: 'J1[14]', identifier: CLKOUT}
84 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
85 */
86 /* clang-format on */
87
88 #include "fsl_common.h"
89 #include "fsl_port.h"
90 #include "fsl_gpio.h"
91 #include "pin_mux.h"
92
93 /* FUNCTION ************************************************************************************************************
94 *
95 * Function Name : BOARD_InitBootPins
96 * Description : Calls initialization functions.
97 *
98 * END ****************************************************************************************************************/
BOARD_InitBootPins(void)99 void BOARD_InitBootPins(void)
100 {
101 BOARD_InitPins();
102 BOARD_InitDEBUG_UARTPins();
103 }
104
105 /* clang-format off */
106 /*
107 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
108 BOARD_InitPins:
109 - options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
110 - pin_list:
111 - {pin_num: '24', peripheral: TPIU, signal: SWO, pin_signal: PTA2/UART0_TX/FTM0_CH7/JTAG_TDO/TRACE_SWO/EZP_DO, identifier: '', pull_select: down, pull_enable: disable}
112 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
113 */
114 /* clang-format on */
115
116 /* FUNCTION ************************************************************************************************************
117 *
118 * Function Name : BOARD_InitPins
119 * Description : Configures pin routing and optionally pin electrical features.
120 *
121 * END ****************************************************************************************************************/
BOARD_InitPins(void)122 void BOARD_InitPins(void)
123 {
124 /* Port A Clock Gate Control: Clock enabled */
125 CLOCK_EnableClock(kCLOCK_PortA);
126
127 /* PORTA2 (pin 24) is configured as TRACE_SWO */
128 PORT_SetPinMux(PORTA, 2U, kPORT_MuxAlt7);
129
130 PORTA->PCR[2] = ((PORTA->PCR[2] &
131 /* Mask bits to zero which are setting */
132 (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK)))
133
134 /* Pull Select: Internal pulldown resistor is enabled on the corresponding pin, if the
135 * corresponding PE field is set. */
136 | PORT_PCR_PS(kPORT_PullDown)
137
138 /* Pull Enable: Internal pullup or pulldown resistor is not enabled on the corresponding pin. */
139 | PORT_PCR_PE(kPORT_PullDisable));
140 }
141
142 /* clang-format off */
143 /*
144 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
145 BOARD_InitLEDsPins:
146 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
147 - pin_list:
148 - {pin_num: '23', peripheral: GPIOA, signal: 'GPIO, 1', pin_signal: PTA1/UART0_RX/FTM0_CH6/JTAG_TDI/EZP_DI, direction: OUTPUT, gpio_init_state: 'true', slew_rate: slow,
149 open_drain: disable, pull_select: down, pull_enable: disable}
150 - {pin_num: '24', peripheral: GPIOA, signal: 'GPIO, 2', pin_signal: PTA2/UART0_TX/FTM0_CH7/JTAG_TDO/TRACE_SWO/EZP_DO, direction: OUTPUT, gpio_init_state: 'true',
151 slew_rate: slow, open_drain: disable, pull_select: down, pull_enable: disable}
152 - {pin_num: '62', peripheral: GPIOD, signal: 'GPIO, 5', pin_signal: ADC0_SE6b/PTD5/SPI0_PCS2/UART0_CTS_b/FTM0_CH5/FB_AD1/EWM_OUT_b/SPI1_SCK, direction: OUTPUT,
153 gpio_init_state: 'true', slew_rate: slow, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable}
154 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
155 */
156 /* clang-format on */
157
158 /* FUNCTION ************************************************************************************************************
159 *
160 * Function Name : BOARD_InitLEDsPins
161 * Description : Configures pin routing and optionally pin electrical features.
162 *
163 * END ****************************************************************************************************************/
BOARD_InitLEDsPins(void)164 void BOARD_InitLEDsPins(void)
165 {
166 /* Port A Clock Gate Control: Clock enabled */
167 CLOCK_EnableClock(kCLOCK_PortA);
168 /* Port D Clock Gate Control: Clock enabled */
169 CLOCK_EnableClock(kCLOCK_PortD);
170
171 gpio_pin_config_t LEDRGB_RED_config = {
172 .pinDirection = kGPIO_DigitalOutput,
173 .outputLogic = 1U
174 };
175 /* Initialize GPIO functionality on pin PTA1 (pin 23) */
176 GPIO_PinInit(BOARD_LEDRGB_RED_GPIO, BOARD_LEDRGB_RED_PIN, &LEDRGB_RED_config);
177
178 gpio_pin_config_t LEDRGB_GREEN_config = {
179 .pinDirection = kGPIO_DigitalOutput,
180 .outputLogic = 1U
181 };
182 /* Initialize GPIO functionality on pin PTA2 (pin 24) */
183 GPIO_PinInit(BOARD_LEDRGB_GREEN_GPIO, BOARD_LEDRGB_GREEN_PIN, &LEDRGB_GREEN_config);
184
185 gpio_pin_config_t LEDRGB_BLUE_config = {
186 .pinDirection = kGPIO_DigitalOutput,
187 .outputLogic = 1U
188 };
189 /* Initialize GPIO functionality on pin PTD5 (pin 62) */
190 GPIO_PinInit(BOARD_LEDRGB_BLUE_GPIO, BOARD_LEDRGB_BLUE_PIN, &LEDRGB_BLUE_config);
191
192 const port_pin_config_t LEDRGB_RED = {/* Internal pull-up/down resistor is disabled */
193 kPORT_PullDisable,
194 /* Slow slew rate is configured */
195 kPORT_SlowSlewRate,
196 /* Passive filter is disabled */
197 kPORT_PassiveFilterDisable,
198 /* Open drain is disabled */
199 kPORT_OpenDrainDisable,
200 /* Low drive strength is configured */
201 kPORT_LowDriveStrength,
202 /* Pin is configured as PTA1 */
203 kPORT_MuxAsGpio,
204 /* Pin Control Register fields [15:0] are not locked */
205 kPORT_UnlockRegister};
206 /* PORTA1 (pin 23) is configured as PTA1 */
207 PORT_SetPinConfig(BOARD_LEDRGB_RED_PORT, BOARD_LEDRGB_RED_PIN, &LEDRGB_RED);
208
209 const port_pin_config_t LEDRGB_GREEN = {/* Internal pull-up/down resistor is disabled */
210 kPORT_PullDisable,
211 /* Slow slew rate is configured */
212 kPORT_SlowSlewRate,
213 /* Passive filter is disabled */
214 kPORT_PassiveFilterDisable,
215 /* Open drain is disabled */
216 kPORT_OpenDrainDisable,
217 /* Low drive strength is configured */
218 kPORT_LowDriveStrength,
219 /* Pin is configured as PTA2 */
220 kPORT_MuxAsGpio,
221 /* Pin Control Register fields [15:0] are not locked */
222 kPORT_UnlockRegister};
223 /* PORTA2 (pin 24) is configured as PTA2 */
224 PORT_SetPinConfig(BOARD_LEDRGB_GREEN_PORT, BOARD_LEDRGB_GREEN_PIN, &LEDRGB_GREEN);
225
226 const port_pin_config_t LEDRGB_BLUE = {/* Internal pull-up/down resistor is disabled */
227 kPORT_PullDisable,
228 /* Slow slew rate is configured */
229 kPORT_SlowSlewRate,
230 /* Passive filter is disabled */
231 kPORT_PassiveFilterDisable,
232 /* Open drain is disabled */
233 kPORT_OpenDrainDisable,
234 /* Low drive strength is configured */
235 kPORT_LowDriveStrength,
236 /* Pin is configured as PTD5 */
237 kPORT_MuxAsGpio,
238 /* Pin Control Register fields [15:0] are not locked */
239 kPORT_UnlockRegister};
240 /* PORTD5 (pin 62) is configured as PTD5 */
241 PORT_SetPinConfig(BOARD_LEDRGB_BLUE_PORT, BOARD_LEDRGB_BLUE_PIN, &LEDRGB_BLUE);
242 }
243
244 /* clang-format off */
245 /*
246 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
247 BOARD_InitButtonsPins:
248 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
249 - pin_list:
250 - {pin_num: '40', peripheral: GPIOB, signal: 'GPIO, 17', pin_signal: PTB17/SPI1_SIN/UART0_TX/FTM_CLKIN1/FB_AD16/EWM_OUT_b, direction: INPUT, slew_rate: fast, open_drain: disable,
251 pull_select: up, pull_enable: enable}
252 - {pin_num: '44', peripheral: GPIOC, signal: 'GPIO, 1', pin_signal: ADC0_SE15/PTC1/LLWU_P6/SPI0_PCS3/UART1_RTS_b/FTM0_CH0/FB_AD13/I2S0_TXD0/LPUART0_RTS_b, direction: INPUT,
253 slew_rate: fast, open_drain: disable, pull_select: up, pull_enable: enable}
254 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
255 */
256 /* clang-format on */
257
258 /* FUNCTION ************************************************************************************************************
259 *
260 * Function Name : BOARD_InitButtonsPins
261 * Description : Configures pin routing and optionally pin electrical features.
262 *
263 * END ****************************************************************************************************************/
BOARD_InitButtonsPins(void)264 void BOARD_InitButtonsPins(void)
265 {
266 /* Port B Clock Gate Control: Clock enabled */
267 CLOCK_EnableClock(kCLOCK_PortB);
268 /* Port C Clock Gate Control: Clock enabled */
269 CLOCK_EnableClock(kCLOCK_PortC);
270
271 gpio_pin_config_t SW3_config = {
272 .pinDirection = kGPIO_DigitalInput,
273 .outputLogic = 0U
274 };
275 /* Initialize GPIO functionality on pin PTB17 (pin 40) */
276 GPIO_PinInit(BOARD_SW3_GPIO, BOARD_SW3_PIN, &SW3_config);
277
278 gpio_pin_config_t SW2_config = {
279 .pinDirection = kGPIO_DigitalInput,
280 .outputLogic = 0U
281 };
282 /* Initialize GPIO functionality on pin PTC1 (pin 44) */
283 GPIO_PinInit(BOARD_SW2_GPIO, BOARD_SW2_PIN, &SW2_config);
284
285 const port_pin_config_t SW3 = {/* Internal pull-up resistor is enabled */
286 kPORT_PullUp,
287 /* Fast slew rate is configured */
288 kPORT_FastSlewRate,
289 /* Passive filter is disabled */
290 kPORT_PassiveFilterDisable,
291 /* Open drain is disabled */
292 kPORT_OpenDrainDisable,
293 /* Low drive strength is configured */
294 kPORT_LowDriveStrength,
295 /* Pin is configured as PTB17 */
296 kPORT_MuxAsGpio,
297 /* Pin Control Register fields [15:0] are not locked */
298 kPORT_UnlockRegister};
299 /* PORTB17 (pin 40) is configured as PTB17 */
300 PORT_SetPinConfig(BOARD_SW3_PORT, BOARD_SW3_PIN, &SW3);
301
302 const port_pin_config_t SW2 = {/* Internal pull-up resistor is enabled */
303 kPORT_PullUp,
304 /* Fast slew rate is configured */
305 kPORT_FastSlewRate,
306 /* Passive filter is disabled */
307 kPORT_PassiveFilterDisable,
308 /* Open drain is disabled */
309 kPORT_OpenDrainDisable,
310 /* Low drive strength is configured */
311 kPORT_LowDriveStrength,
312 /* Pin is configured as PTC1 */
313 kPORT_MuxAsGpio,
314 /* Pin Control Register fields [15:0] are not locked */
315 kPORT_UnlockRegister};
316 /* PORTC1 (pin 44) is configured as PTC1 */
317 PORT_SetPinConfig(BOARD_SW2_PORT, BOARD_SW2_PIN, &SW2);
318 }
319
320 /* clang-format off */
321 /*
322 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
323 BOARD_InitDEBUG_UARTPins:
324 - options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'}
325 - pin_list:
326 - {pin_num: '2', peripheral: UART1, signal: RX, pin_signal: ADC1_SE5a/PTE1/LLWU_P0/SPI1_SOUT/UART1_RX/I2C1_SCL/SPI1_SIN, slew_rate: fast, open_drain: disable, pull_select: down,
327 pull_enable: disable}
328 - {pin_num: '1', peripheral: UART1, signal: TX, pin_signal: ADC1_SE4a/PTE0/CLKOUT32K/SPI1_PCS1/UART1_TX/I2C1_SDA/RTC_CLKOUT, identifier: DEBUG_UART_TX, direction: OUTPUT,
329 slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
330 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
331 */
332 /* clang-format on */
333
334 /* FUNCTION ************************************************************************************************************
335 *
336 * Function Name : BOARD_InitDEBUG_UARTPins
337 * Description : Configures pin routing and optionally pin electrical features.
338 *
339 * END ****************************************************************************************************************/
BOARD_InitDEBUG_UARTPins(void)340 void BOARD_InitDEBUG_UARTPins(void)
341 {
342 /* Port E Clock Gate Control: Clock enabled */
343 CLOCK_EnableClock(kCLOCK_PortE);
344
345 const port_pin_config_t DEBUG_UART_TX = {/* Internal pull-up/down resistor is disabled */
346 kPORT_PullDisable,
347 /* Fast slew rate is configured */
348 kPORT_FastSlewRate,
349 /* Passive filter is disabled */
350 kPORT_PassiveFilterDisable,
351 /* Open drain is disabled */
352 kPORT_OpenDrainDisable,
353 /* Low drive strength is configured */
354 kPORT_LowDriveStrength,
355 /* Pin is configured as UART1_TX */
356 kPORT_MuxAlt3,
357 /* Pin Control Register fields [15:0] are not locked */
358 kPORT_UnlockRegister};
359 /* PORTE0 (pin 1) is configured as UART1_TX */
360 PORT_SetPinConfig(BOARD_DEBUG_UART_TX_PORT, BOARD_DEBUG_UART_TX_PIN, &DEBUG_UART_TX);
361
362 const port_pin_config_t DEBUG_UART_RX = {/* Internal pull-up/down resistor is disabled */
363 kPORT_PullDisable,
364 /* Fast slew rate is configured */
365 kPORT_FastSlewRate,
366 /* Passive filter is disabled */
367 kPORT_PassiveFilterDisable,
368 /* Open drain is disabled */
369 kPORT_OpenDrainDisable,
370 /* Low drive strength is configured */
371 kPORT_LowDriveStrength,
372 /* Pin is configured as UART1_RX */
373 kPORT_MuxAlt3,
374 /* Pin Control Register fields [15:0] are not locked */
375 kPORT_UnlockRegister};
376 /* PORTE1 (pin 2) is configured as UART1_RX */
377 PORT_SetPinConfig(BOARD_DEBUG_UART_RX_PORT, BOARD_DEBUG_UART_RX_PIN, &DEBUG_UART_RX);
378
379 SIM->SOPT5 = ((SIM->SOPT5 &
380 /* Mask bits to zero which are setting */
381 (~(SIM_SOPT5_UART1TXSRC_MASK)))
382
383 /* UART 1 transmit data source select: UART1_TX pin. */
384 | SIM_SOPT5_UART1TXSRC(SOPT5_UART1TXSRC_UART_TX));
385 }
386
387 /* clang-format off */
388 /*
389 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
390 BOARD_InitAccelPins:
391 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
392 - pin_list:
393 - {pin_num: '37', peripheral: I2C0, signal: SCL, pin_signal: ADC0_SE12/PTB2/I2C0_SCL/UART0_RTS_b/FTM0_FLT3, identifier: ACCEL_SCL, slew_rate: fast, open_drain: enable,
394 pull_select: up, pull_enable: enable}
395 - {pin_num: '38', peripheral: I2C0, signal: SDA, pin_signal: ADC0_SE13/PTB3/I2C0_SDA/UART0_CTS_b/FTM0_FLT0, identifier: ACCEL_SDA, slew_rate: fast, open_drain: enable,
396 pull_select: up, pull_enable: enable}
397 - {pin_num: '57', peripheral: GPIOD, signal: 'GPIO, 0', pin_signal: PTD0/LLWU_P12/SPI0_PCS0/UART2_RTS_b/FTM3_CH0/FB_ALE/FB_CS1_b/FB_TS_b/LPUART0_RTS_b, identifier: ACCEL_INT1,
398 direction: INPUT, slew_rate: fast, open_drain: enable, pull_select: down, pull_enable: disable}
399 - {pin_num: '58', peripheral: GPIOD, signal: 'GPIO, 1', pin_signal: ADC0_SE5b/PTD1/SPI0_SCK/UART2_CTS_b/FTM3_CH1/FB_CS0_b/LPUART0_CTS_b, identifier: ACCEL_INT2,
400 direction: INPUT, slew_rate: fast, open_drain: enable, pull_select: down, pull_enable: disable}
401 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
402 */
403 /* clang-format on */
404
405 /* FUNCTION ************************************************************************************************************
406 *
407 * Function Name : BOARD_InitAccelPins
408 * Description : Configures pin routing and optionally pin electrical features.
409 *
410 * END ****************************************************************************************************************/
BOARD_InitAccelPins(void)411 void BOARD_InitAccelPins(void)
412 {
413 /* Port B Clock Gate Control: Clock enabled */
414 CLOCK_EnableClock(kCLOCK_PortB);
415 /* Port D Clock Gate Control: Clock enabled */
416 CLOCK_EnableClock(kCLOCK_PortD);
417
418 gpio_pin_config_t ACCEL_INT1_config = {
419 .pinDirection = kGPIO_DigitalInput,
420 .outputLogic = 0U
421 };
422 /* Initialize GPIO functionality on pin PTD0 (pin 57) */
423 GPIO_PinInit(BOARD_ACCEL_INT1_GPIO, BOARD_ACCEL_INT1_PIN, &ACCEL_INT1_config);
424
425 gpio_pin_config_t ACCEL_INT2_config = {
426 .pinDirection = kGPIO_DigitalInput,
427 .outputLogic = 0U
428 };
429 /* Initialize GPIO functionality on pin PTD1 (pin 58) */
430 GPIO_PinInit(BOARD_ACCEL_INT2_GPIO, BOARD_ACCEL_INT2_PIN, &ACCEL_INT2_config);
431
432 const port_pin_config_t ACCEL_SCL = {/* Internal pull-up resistor is enabled */
433 kPORT_PullUp,
434 /* Fast slew rate is configured */
435 kPORT_FastSlewRate,
436 /* Passive filter is disabled */
437 kPORT_PassiveFilterDisable,
438 /* Open drain is enabled */
439 kPORT_OpenDrainEnable,
440 /* Low drive strength is configured */
441 kPORT_LowDriveStrength,
442 /* Pin is configured as I2C0_SCL */
443 kPORT_MuxAlt2,
444 /* Pin Control Register fields [15:0] are not locked */
445 kPORT_UnlockRegister};
446 /* PORTB2 (pin 37) is configured as I2C0_SCL */
447 PORT_SetPinConfig(BOARD_ACCEL_SCL_PORT, BOARD_ACCEL_SCL_PIN, &ACCEL_SCL);
448
449 const port_pin_config_t ACCEL_SDA = {/* Internal pull-up resistor is enabled */
450 kPORT_PullUp,
451 /* Fast slew rate is configured */
452 kPORT_FastSlewRate,
453 /* Passive filter is disabled */
454 kPORT_PassiveFilterDisable,
455 /* Open drain is enabled */
456 kPORT_OpenDrainEnable,
457 /* Low drive strength is configured */
458 kPORT_LowDriveStrength,
459 /* Pin is configured as I2C0_SDA */
460 kPORT_MuxAlt2,
461 /* Pin Control Register fields [15:0] are not locked */
462 kPORT_UnlockRegister};
463 /* PORTB3 (pin 38) is configured as I2C0_SDA */
464 PORT_SetPinConfig(BOARD_ACCEL_SDA_PORT, BOARD_ACCEL_SDA_PIN, &ACCEL_SDA);
465
466 const port_pin_config_t ACCEL_INT1 = {/* Internal pull-up/down resistor is disabled */
467 kPORT_PullDisable,
468 /* Fast slew rate is configured */
469 kPORT_FastSlewRate,
470 /* Passive filter is disabled */
471 kPORT_PassiveFilterDisable,
472 /* Open drain is enabled */
473 kPORT_OpenDrainEnable,
474 /* Low drive strength is configured */
475 kPORT_LowDriveStrength,
476 /* Pin is configured as PTD0 */
477 kPORT_MuxAsGpio,
478 /* Pin Control Register fields [15:0] are not locked */
479 kPORT_UnlockRegister};
480 /* PORTD0 (pin 57) is configured as PTD0 */
481 PORT_SetPinConfig(BOARD_ACCEL_INT1_PORT, BOARD_ACCEL_INT1_PIN, &ACCEL_INT1);
482
483 const port_pin_config_t ACCEL_INT2 = {/* Internal pull-up/down resistor is disabled */
484 kPORT_PullDisable,
485 /* Fast slew rate is configured */
486 kPORT_FastSlewRate,
487 /* Passive filter is disabled */
488 kPORT_PassiveFilterDisable,
489 /* Open drain is enabled */
490 kPORT_OpenDrainEnable,
491 /* Low drive strength is configured */
492 kPORT_LowDriveStrength,
493 /* Pin is configured as PTD1 */
494 kPORT_MuxAsGpio,
495 /* Pin Control Register fields [15:0] are not locked */
496 kPORT_UnlockRegister};
497 /* PORTD1 (pin 58) is configured as PTD1 */
498 PORT_SetPinConfig(BOARD_ACCEL_INT2_PORT, BOARD_ACCEL_INT2_PIN, &ACCEL_INT2);
499 }
500
501 /* clang-format off */
502 /*
503 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
504 BOARD_InitSDHCPins:
505 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
506 - pin_list:
507 - {pin_num: '49', peripheral: SPI0, signal: PCS0_SS, pin_signal: PTC4/LLWU_P8/SPI0_PCS0/UART1_TX/FTM0_CH3/FB_AD11/CMP1_OUT/LPUART0_TX, direction: INPUT, slew_rate: fast,
508 open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable}
509 - {pin_num: '58', peripheral: SPI0, signal: SCK, pin_signal: ADC0_SE5b/PTD1/SPI0_SCK/UART2_CTS_b/FTM3_CH1/FB_CS0_b/LPUART0_CTS_b, identifier: SD_CARD_CLK, slew_rate: fast,
510 open_drain: disable, pull_select: down, pull_enable: disable}
511 - {pin_num: '59', peripheral: SPI0, signal: SOUT, pin_signal: PTD2/LLWU_P13/SPI0_SOUT/UART2_RX/FTM3_CH2/FB_AD4/LPUART0_RX/I2C0_SCL, slew_rate: fast, open_drain: disable,
512 pull_select: down, pull_enable: disable}
513 - {pin_num: '60', peripheral: SPI0, signal: SIN, pin_signal: PTD3/SPI0_SIN/UART2_TX/FTM3_CH3/FB_AD3/LPUART0_TX/I2C0_SDA, slew_rate: fast, open_drain: disable, pull_select: down,
514 pull_enable: disable}
515 - {pin_num: '39', peripheral: GPIOB, signal: 'GPIO, 16', pin_signal: PTB16/SPI1_SOUT/UART0_RX/FTM_CLKIN0/FB_AD17/EWM_IN, direction: INPUT, slew_rate: slow, open_drain: disable,
516 pull_select: up, pull_enable: enable}
517 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
518 */
519 /* clang-format on */
520
521 /* FUNCTION ************************************************************************************************************
522 *
523 * Function Name : BOARD_InitSDHCPins
524 * Description : Configures pin routing and optionally pin electrical features.
525 *
526 * END ****************************************************************************************************************/
BOARD_InitSDHCPins(void)527 void BOARD_InitSDHCPins(void)
528 {
529 /* Port B Clock Gate Control: Clock enabled */
530 CLOCK_EnableClock(kCLOCK_PortB);
531 /* Port C Clock Gate Control: Clock enabled */
532 CLOCK_EnableClock(kCLOCK_PortC);
533 /* Port D Clock Gate Control: Clock enabled */
534 CLOCK_EnableClock(kCLOCK_PortD);
535
536 gpio_pin_config_t SD_CARD_DETECT_config = {
537 .pinDirection = kGPIO_DigitalInput,
538 .outputLogic = 0U
539 };
540 /* Initialize GPIO functionality on pin PTB16 (pin 39) */
541 GPIO_PinInit(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PIN, &SD_CARD_DETECT_config);
542
543 const port_pin_config_t SD_CARD_DETECT = {/* Internal pull-up resistor is enabled */
544 kPORT_PullUp,
545 /* Slow slew rate is configured */
546 kPORT_SlowSlewRate,
547 /* Passive filter is disabled */
548 kPORT_PassiveFilterDisable,
549 /* Open drain is disabled */
550 kPORT_OpenDrainDisable,
551 /* Low drive strength is configured */
552 kPORT_LowDriveStrength,
553 /* Pin is configured as PTB16 */
554 kPORT_MuxAsGpio,
555 /* Pin Control Register fields [15:0] are not locked */
556 kPORT_UnlockRegister};
557 /* PORTB16 (pin 39) is configured as PTB16 */
558 PORT_SetPinConfig(BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN, &SD_CARD_DETECT);
559
560 const port_pin_config_t SD_CARD_DAT3 = {/* Internal pull-up/down resistor is disabled */
561 kPORT_PullDisable,
562 /* Fast slew rate is configured */
563 kPORT_FastSlewRate,
564 /* Passive filter is disabled */
565 kPORT_PassiveFilterDisable,
566 /* Open drain is disabled */
567 kPORT_OpenDrainDisable,
568 /* Low drive strength is configured */
569 kPORT_LowDriveStrength,
570 /* Pin is configured as SPI0_PCS0 */
571 kPORT_MuxAlt2,
572 /* Pin Control Register fields [15:0] are not locked */
573 kPORT_UnlockRegister};
574 /* PORTC4 (pin 49) is configured as SPI0_PCS0 */
575 PORT_SetPinConfig(BOARD_SD_CARD_DAT3_PORT, BOARD_SD_CARD_DAT3_PIN, &SD_CARD_DAT3);
576
577 const port_pin_config_t SD_CARD_CLK = {/* Internal pull-up/down resistor is disabled */
578 kPORT_PullDisable,
579 /* Fast slew rate is configured */
580 kPORT_FastSlewRate,
581 /* Passive filter is disabled */
582 kPORT_PassiveFilterDisable,
583 /* Open drain is disabled */
584 kPORT_OpenDrainDisable,
585 /* Low drive strength is configured */
586 kPORT_LowDriveStrength,
587 /* Pin is configured as SPI0_SCK */
588 kPORT_MuxAlt2,
589 /* Pin Control Register fields [15:0] are not locked */
590 kPORT_UnlockRegister};
591 /* PORTD1 (pin 58) is configured as SPI0_SCK */
592 PORT_SetPinConfig(BOARD_SD_CARD_CLK_PORT, BOARD_SD_CARD_CLK_PIN, &SD_CARD_CLK);
593
594 const port_pin_config_t SD_CARD_CMD = {/* Internal pull-up/down resistor is disabled */
595 kPORT_PullDisable,
596 /* Fast slew rate is configured */
597 kPORT_FastSlewRate,
598 /* Passive filter is disabled */
599 kPORT_PassiveFilterDisable,
600 /* Open drain is disabled */
601 kPORT_OpenDrainDisable,
602 /* Low drive strength is configured */
603 kPORT_LowDriveStrength,
604 /* Pin is configured as SPI0_SOUT */
605 kPORT_MuxAlt2,
606 /* Pin Control Register fields [15:0] are not locked */
607 kPORT_UnlockRegister};
608 /* PORTD2 (pin 59) is configured as SPI0_SOUT */
609 PORT_SetPinConfig(BOARD_SD_CARD_CMD_PORT, BOARD_SD_CARD_CMD_PIN, &SD_CARD_CMD);
610
611 const port_pin_config_t SD_CARD_DAT0 = {/* Internal pull-up/down resistor is disabled */
612 kPORT_PullDisable,
613 /* Fast slew rate is configured */
614 kPORT_FastSlewRate,
615 /* Passive filter is disabled */
616 kPORT_PassiveFilterDisable,
617 /* Open drain is disabled */
618 kPORT_OpenDrainDisable,
619 /* Low drive strength is configured */
620 kPORT_LowDriveStrength,
621 /* Pin is configured as SPI0_SIN */
622 kPORT_MuxAlt2,
623 /* Pin Control Register fields [15:0] are not locked */
624 kPORT_UnlockRegister};
625 /* PORTD3 (pin 60) is configured as SPI0_SIN */
626 PORT_SetPinConfig(BOARD_SD_CARD_DAT0_PORT, BOARD_SD_CARD_DAT0_PIN, &SD_CARD_DAT0);
627 }
628
629 /* clang-format off */
630 /*
631 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
632 BOARD_InitOSCPins:
633 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
634 - pin_list:
635 - {pin_num: '32', peripheral: OSC, signal: EXTAL0, pin_signal: EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0, slew_rate: no_init, open_drain: no_init, pull_select: no_init,
636 pull_enable: no_init}
637 - {pin_num: '33', peripheral: OSC, signal: XTAL0, pin_signal: XTAL0/PTA19/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1, slew_rate: no_init, open_drain: no_init, pull_select: no_init,
638 pull_enable: no_init}
639 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
640 */
641 /* clang-format on */
642
643 /* FUNCTION ************************************************************************************************************
644 *
645 * Function Name : BOARD_InitOSCPins
646 * Description : Configures pin routing and optionally pin electrical features.
647 *
648 * END ****************************************************************************************************************/
BOARD_InitOSCPins(void)649 void BOARD_InitOSCPins(void)
650 {
651 /* Port A Clock Gate Control: Clock enabled */
652 CLOCK_EnableClock(kCLOCK_PortA);
653
654 /* PORTA18 (pin 32) is configured as EXTAL0 */
655 PORT_SetPinMux(BOARD_EXTAL0_PORT, BOARD_EXTAL0_PIN, kPORT_PinDisabledOrAnalog);
656
657 /* PORTA19 (pin 33) is configured as XTAL0 */
658 PORT_SetPinMux(BOARD_XTAL0_PORT, BOARD_XTAL0_PIN, kPORT_PinDisabledOrAnalog);
659 }
660
661 /* clang-format off */
662 /*
663 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
664 BOARD_InitPOTPins:
665 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
666 - pin_list:
667 - {pin_num: '37', peripheral: ADC0, signal: 'SE, 12', pin_signal: ADC0_SE12/PTB2/I2C0_SCL/UART0_RTS_b/FTM0_FLT3, identifier: POT_5K, slew_rate: fast, open_drain: disable,
668 pull_select: down, pull_enable: disable}
669 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
670 */
671 /* clang-format on */
672
673 /* FUNCTION ************************************************************************************************************
674 *
675 * Function Name : BOARD_InitPOTPins
676 * Description : Configures pin routing and optionally pin electrical features.
677 *
678 * END ****************************************************************************************************************/
BOARD_InitPOTPins(void)679 void BOARD_InitPOTPins(void)
680 {
681 /* Port B Clock Gate Control: Clock enabled */
682 CLOCK_EnableClock(kCLOCK_PortB);
683
684 const port_pin_config_t POT_5K = {/* Internal pull-up/down resistor is disabled */
685 kPORT_PullDisable,
686 /* Fast slew rate is configured */
687 kPORT_FastSlewRate,
688 /* Passive filter is disabled */
689 kPORT_PassiveFilterDisable,
690 /* Open drain is disabled */
691 kPORT_OpenDrainDisable,
692 /* Low drive strength is configured */
693 kPORT_LowDriveStrength,
694 /* Pin is configured as ADC0_SE12 */
695 kPORT_PinDisabledOrAnalog,
696 /* Pin Control Register fields [15:0] are not locked */
697 kPORT_UnlockRegister};
698 /* PORTB2 (pin 37) is configured as ADC0_SE12 */
699 PORT_SetPinConfig(BOARD_POT_5K_PORT, BOARD_POT_5K_PIN, &POT_5K);
700 }
701
702 /* clang-format off */
703 /*
704 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
705 BOARD_InitLSENSEPins:
706 - options: {prefix: BOARD_, coreID: core0, enableClock: 'true'}
707 - pin_list:
708 - {pin_num: '11', peripheral: ADC0, signal: 'SE, 3', pin_signal: ADC1_DP0/ADC0_DP3}
709 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
710 */
711 /* clang-format on */
712
713 /* FUNCTION ************************************************************************************************************
714 *
715 * Function Name : BOARD_InitLSENSEPins
716 * Description : Configures pin routing and optionally pin electrical features.
717 *
718 * END ****************************************************************************************************************/
BOARD_InitLSENSEPins(void)719 void BOARD_InitLSENSEPins(void)
720 {
721 }
722 /***********************************************************************************************************************
723 * EOF
724 **********************************************************************************************************************/
725
