1 /* 2 * Copyright 2020 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef __FLASH_CONFIG__ 9 #define __FLASH_CONFIG__ 10 11 #include <stdint.h> 12 #include <stdbool.h> 13 #include "fsl_common.h" 14 15 /*! @name Driver version */ 16 /*@{*/ 17 /*! @brief FLASH_CONFIG driver version 2.0.0. */ 18 #define FSL_FLASH_CONFIG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) 19 /*@}*/ 20 21 /******************************************************************************* 22 * Definition 23 ******************************************************************************/ 24 25 /* FLEXSPI memory config block related defintions */ 26 #define FLASH_CONFIG_BLOCK_TAG (0x42464346) 27 #define FLASH_CONFIG_BLOCK_VERSION (0x56010400) 28 29 #define CMD_SDR 0x01 30 #define CMD_DDR 0x21 31 #define RADDR_SDR 0x02 32 #define RADDR_DDR 0x22 33 #define CADDR_SDR 0x03 34 #define CADDR_DDR 0x23 35 #define MODE1_SDR 0x04 36 #define MODE1_DDR 0x24 37 #define MODE2_SDR 0x05 38 #define MODE2_DDR 0x25 39 #define MODE4_SDR 0x06 40 #define MODE4_DDR 0x26 41 #define MODE8_SDR 0x07 42 #define MODE8_DDR 0x27 43 #define WRITE_SDR 0x08 44 #define WRITE_DDR 0x28 45 #define READ_SDR 0x09 46 #define READ_DDR 0x29 47 #define LEARN_SDR 0x0A 48 #define LEARN_DDR 0x2A 49 #define DATSZ_SDR 0x0B 50 #define DATSZ_DDR 0x2B 51 #define DUMMY_SDR 0x0C 52 #define DUMMY_DDR 0x2C 53 #define DUMMY_RWDS_SDR 0x0D 54 #define DUMMY_RWDS_DDR 0x2D 55 #define JMP_ON_CS 0x1F 56 #define STOP_EXE 0 57 58 #define FLEXSPI_1PAD 0 59 #define FLEXSPI_2PAD 1 60 #define FLEXSPI_4PAD 2 61 #define FLEXSPI_8PAD 3 62 63 #define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ 64 (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ 65 FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) 66 67 /* !@brief Data pad used in Read command */ 68 enum 69 { 70 kSerialFlash_1Pads = 1, 71 kSerialFlash_2Pads = 2, 72 kSerialFlash_4Pads = 4, 73 kSerialFlash_8Pads = 8, 74 }; 75 76 /* !@brief FLEXSPI clock configuration - In High speed boot mode */ 77 enum 78 { 79 kFlexSpiSerialClk_30MHz = 1, 80 kFlexSpiSerialClk_50MHz = 2, 81 kFlexSpiSerialClk_60MHz = 3, 82 kFlexSpiSerialClk_80MHz = 4, 83 kFlexSpiSerialClk_100MHz = 5, 84 kFlexSpiSerialClk_120MHz = 6, 85 kFlexSpiSerialClk_133MHz = 7, 86 kFlexSpiSerialClk_166MHz = 8, 87 kFlexSpiSerialClk_200MHz = 9, 88 }; 89 90 /* !@brief FLEXSPI clock configuration - In Normal boot SDR mode */ 91 enum 92 { 93 kFlexSpiSerialClk_SDR_24MHz = 1, 94 kFlexSpiSerialClk_SDR_48MHz = 2, 95 }; 96 97 /* !@brief FLEXSPI clock configuration - In Normal boot DDR mode */ 98 enum 99 { 100 kFlexSpiSerialClk_DDR_48MHz = 1, 101 }; 102 103 /* !@brief Misc feature bit definitions */ 104 enum 105 { 106 kFlexSpiMiscOffset_DiffClkEnable = 0, /* !< Bit for Differential clock enable */ 107 kFlexSpiMiscOffset_WordAddressableEnable = 3, /* !< Bit for Word Addressable enable */ 108 kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, /* !< Bit for Safe Configuration Frequency enable */ 109 kFlexSpiMiscOffset_DdrModeEnable = 6, /* !< Bit for DDR clock confiuration indication. */ 110 }; 111 112 /* !@brief Flash Configuration Command Type */ 113 enum 114 { 115 kDeviceConfigCmdType_Generic, /* !< Generic command, for example: configure dummy cycles, drive strength, etc */ 116 kDeviceConfigCmdType_QuadEnable, /* !< Quad Enable command */ 117 kDeviceConfigCmdType_Spi2Xpi, /* !< Switch from SPI to DPI/QPI/OPI mode */ 118 kDeviceConfigCmdType_Xpi2Spi, /* !< Switch from DPI/QPI/OPI to SPI mode */ 119 kDeviceConfigCmdType_Spi2NoCmd, /* !< Switch to 0-4-4/0-8-8 mode */ 120 kDeviceConfigCmdType_Reset, /* !< Reset device command */ 121 }; 122 123 typedef struct 124 { 125 uint8_t time_100ps; /* !< Data valid time, in terms of 100ps */ 126 uint8_t delay_cells; /* !< Data valid time, in terms of delay cells */ 127 } flexspi_dll_time_t; 128 129 /* !@brief FlexSPI LUT Sequence structure */ 130 typedef struct _lut_sequence 131 { 132 uint8_t seqNum; /* !< Sequence Number, valid number: 1-16 */ 133 uint8_t seqId; /* !< Sequence Index, valid number: 0-15 */ 134 uint16_t reserved; 135 } flexspi_lut_seq_t; 136 137 /* !@brief FlexSPI Memory Configuration Block */ 138 typedef struct _FlexSPIConfig 139 { 140 uint32_t tag; /* !< [0x000-0x003] Tag, fixed value 0x42464346UL */ 141 uint32_t version; /* !< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix */ 142 uint32_t reserved0; /* !< [0x008-0x00b] Reserved for future use */ 143 uint8_t readSampleClkSrc; /* !< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */ 144 uint8_t csHoldTime; /* !< [0x00d-0x00d] CS hold time, default value: 3 */ 145 uint8_t csSetupTime; /* !< [0x00e-0x00e] CS setup time, default value: 3 */ 146 uint8_t columnAddressWidth; /* !< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For 147 Serial NAND, need to refer to datasheet */ 148 uint8_t deviceModeCfgEnable; /* !< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable */ 149 uint8_t deviceModeType; /* !< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, 150 Generic configuration, etc. */ 151 uint16_t waitTimeCfgCommands; /* !< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for 152 DPI/QPI/OPI switch or reset command */ 153 flexspi_lut_seq_t deviceModeSeq; /* !< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - 154 LUt sequence number, [31:16] Reserved */ 155 uint32_t deviceModeArg; /* !< [0x018-0x01b] Argument/Parameter for device configuration */ 156 uint8_t configCmdEnable; /* !< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable */ 157 uint8_t configModeType[3]; /* !< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe */ 158 flexspi_lut_seq_t configCmdSeqs[3]; /* !< [0x020-0x02b] Sequence info for Device Configuration command, similar as 159 deviceModeSeq */ 160 uint32_t reserved1; /* !< [0x02c-0x02f] Reserved for future use */ 161 uint32_t configCmdArgs[3]; /* !< [0x030-0x03b] Arguments/Parameters for device Configuration commands */ 162 uint32_t reserved2; /* !< [0x03c-0x03f] Reserved for future use */ 163 uint32_t controllerMiscOption; /* !< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for 164 more details */ 165 uint8_t deviceType; /* !< [0x044-0x044] Device Type: See Flash Type Definition for more details */ 166 uint8_t sflashPadType; /* !< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal */ 167 uint8_t serialClkFreq; /* !< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot 168 Chapter for more details */ 169 uint8_t lutCustomSeqEnable; /* !< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot 170 be done using 1 LUT sequence, currently, only applicable to HyperFLASH */ 171 uint32_t reserved3[2]; /* !< [0x048-0x04f] Reserved for future use */ 172 uint32_t sflashA1Size; /* !< [0x050-0x053] Size of Flash connected to A1 */ 173 uint32_t sflashA2Size; /* !< [0x054-0x057] Size of Flash connected to A2 */ 174 uint32_t sflashB1Size; /* !< [0x058-0x05b] Size of Flash connected to B1 */ 175 uint32_t sflashB2Size; /* !< [0x05c-0x05f] Size of Flash connected to B2 */ 176 uint32_t csPadSettingOverride; /* !< [0x060-0x063] CS pad setting override value */ 177 uint32_t sclkPadSettingOverride; /* !< [0x064-0x067] SCK pad setting override value */ 178 uint32_t dataPadSettingOverride; /* !< [0x068-0x06b] data pad setting override value */ 179 uint32_t dqsPadSettingOverride; /* !< [0x06c-0x06f] DQS pad setting override value */ 180 uint32_t timeoutInMs; /* !< [0x070-0x073] Timeout threshold for read status command */ 181 uint32_t commandInterval; /* !< [0x074-0x077] CS deselect interval between two commands */ 182 flexspi_dll_time_t dataValidTime[2]; /* !< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B */ 183 uint16_t busyOffset; /* !< [0x07c-0x07d] Busy offset, valid value: 0-31 */ 184 uint16_t busyBitPolarity; /* !< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - 185 busy flag is 0 when flash device is busy */ 186 uint32_t lookupTable[64]; /* !< [0x080-0x17f] Lookup table holds Flash command sequences */ 187 flexspi_lut_seq_t lutCustomSeq[12]; /* !< [0x180-0x1af] Customizable LUT Sequences */ 188 uint32_t reserved4[4]; /* !< [0x1b0-0x1bf] Reserved for future use */ 189 } flexspi_mem_config_t; 190 /* 191 * Serial NOR configuration block 192 */ 193 typedef struct _flexspi_nor_config 194 { 195 flexspi_mem_config_t memConfig; /* !< Common memory configuration info via FlexSPI */ 196 uint32_t pageSize; /* !< Page size of Serial NOR */ 197 uint32_t sectorSize; /* !< Sector size of Serial NOR */ 198 uint8_t ipcmdSerialClkFreq; /* !< Clock frequency for IP command */ 199 uint8_t isUniformBlockSize; /* !< Sector/Block size is the same */ 200 uint8_t isDataOrderSwapped; /* !< Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2) */ 201 uint8_t reserved0[1]; /* !< Reserved for future use */ 202 uint8_t serialNorType; /* !< Serial NOR Flash type: 0/1/2/3 */ 203 uint8_t needExitNoCmdMode; /* !< Need to exit NoCmd mode before other IP command */ 204 uint8_t halfClkForNonReadCmd; /* !< Half the Serial Clock for non-read command: true/false */ 205 uint8_t needRestoreNoCmdMode; /* !< Need to Restore NoCmd mode after IP commmand execution */ 206 uint32_t blockSize; /* !< Block size */ 207 uint32_t flashStateCtx; /* !< Flash State Context */ 208 uint32_t reserve2[10]; /* !< Reserved for future use */ 209 } flexspi_nor_config_t; 210 #ifdef __cplusplus 211 extern "C" { 212 #endif 213 214 #ifdef __cplusplus 215 } 216 #endif 217 #endif /* __FLASH_CONFIG__ */ 218
