1 /* 2 * Copyright 2018-2019 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 */ 8 #ifndef __FLASH_CONFIG_H__ 9 #define __FLASH_CONFIG_H__ 10 #include <stdint.h> 11 #include "fsl_iap.h" 12 13 /*! @name Driver version */ 14 /*@{*/ 15 /*! @brief FLASH_CONFIG driver version 2.0.0. */ 16 #define FSL_FLASH_CONFIG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) 17 /*@}*/ 18 19 /******************************************************************************* 20 * Definition 21 ******************************************************************************/ 22 23 /* FLEXSPI memory config block related defintions */ 24 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL) /* ascii "FCFB" Big Endian */ 25 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) /* V1.4.0 */ 26 27 /* !@brief FLEXSPI clock configuration - When clock source is PLL */ 28 enum 29 { 30 kFlexSpiSerialClk_30MHz = 1, 31 kFlexSpiSerialClk_50MHz = 2, 32 kFlexSpiSerialClk_60MHz = 3, 33 kFlexSpiSerialClk_80MHz = 4, 34 kFlexSpiSerialClk_100MHz = 5, 35 kFlexSpiSerialClk_120MHz = 6, 36 kFlexSpiSerialClk_133MHz = 7, 37 kFlexSpiSerialClk_166MHz = 8, 38 kFlexSpiSerialClk_200MHz = 9, 39 }; 40 41 /* !@brief LUT instructions supported by FLEXSPI */ 42 #define CMD_SDR 0x01 43 #define CMD_DDR 0x21 44 #define RADDR_SDR 0x02 45 #define RADDR_DDR 0x22 46 #define CADDR_SDR 0x03 47 #define CADDR_DDR 0x23 48 #define MODE1_SDR 0x04 49 #define MODE1_DDR 0x24 50 #define MODE2_SDR 0x05 51 #define MODE2_DDR 0x25 52 #define MODE4_SDR 0x06 53 #define MODE4_DDR 0x26 54 #define MODE8_SDR 0x07 55 #define MODE8_DDR 0x27 56 #define WRITE_SDR 0x08 57 #define WRITE_DDR 0x28 58 #define READ_SDR 0x09 59 #define READ_DDR 0x29 60 #define LEARN_SDR 0x0A 61 #define LEARN_DDR 0x2A 62 #define DATSZ_SDR 0x0B 63 #define DATSZ_DDR 0x2B 64 #define DUMMY_SDR 0x0C 65 #define DUMMY_DDR 0x2C 66 #define DUMMY_RWDS_SDR 0x0D 67 #define DUMMY_RWDS_DDR 0x2D 68 #define JMP_ON_CS 0x1F 69 #define STOP_EXE 0 70 71 #define FLEXSPI_1PAD 0 72 #define FLEXSPI_2PAD 1 73 #define FLEXSPI_4PAD 2 74 #define FLEXSPI_8PAD 3 75 76 #define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ 77 (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ 78 FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) 79 80 /* !@brief FlexSPI Read Sample Clock Source definition */ 81 typedef enum _FlashReadSampleClkSource 82 { 83 kFlexSPIReadSampleClk_LoopbackInternally = 0, 84 kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, 85 kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, 86 kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, 87 } flexspi_read_sample_clk_t; 88 89 /* !@brief Misc feature bit definitions */ 90 enum 91 { 92 kFlexSpiMiscOffset_DiffClkEnable = 0, /* !< Bit for Differential clock enable */ 93 kFlexSpiMiscOffset_ParallelEnable = 2, /* !< Bit for Parallel mode enable */ 94 kFlexSpiMiscOffset_WordAddressableEnable = 3, /* !< Bit for Word Addressable enable */ 95 kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, /* !< Bit for Safe Configuration Frequency enable */ 96 kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, /* !< Bit for Pad setting override enable */ 97 kFlexSpiMiscOffset_DdrModeEnable = 6, /* !< Bit for DDR clock confiuration indication. */ 98 kFlexSpiMiscOffset_UseValidTimeForAllFreq = 7, /* !< Bit for DLLCR settings under all modes */ 99 }; 100 101 #endif 102
