1 /* 2 * Copyright 2018-2021 NXP 3 * All rights reserved. 4 * 5 * SPDXLicense-Identifier: BSD-3-Clause 6 */ 7 #include "flash_config.h" 8 9 /* Component ID definition, used by tools. */ 10 #ifndef FSL_COMPONENT_ID 11 #define FSL_COMPONENT_ID "platform.drivers.flash_config" 12 #endif 13 14 /******************************************************************************* 15 * Code 16 ******************************************************************************/ 17 #if defined(BOOT_HEADER_ENABLE) && (BOOT_HEADER_ENABLE == 1) 18 #if defined(__ARMCC_VERSION) || defined(__GNUC__) 19 __attribute__((section(".flash_conf"), used)) 20 #elif defined(__ICCARM__) 21 #pragma location = ".flash_conf" 22 #endif 23 24 const flexspi_nor_config_t flash_config = { 25 .memConfig = 26 { 27 .tag = FLEXSPI_CFG_BLK_TAG, 28 .version = FLEXSPI_CFG_BLK_VERSION, 29 .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad, 30 .csHoldTime = 3, 31 .csSetupTime = 3, 32 .deviceModeCfgEnable = 1, 33 .deviceModeType = kDeviceConfigCmdType_Spi2Xpi, 34 .waitTimeCfgCommands = 1, 35 .deviceModeSeq = 36 { 37 .seqNum = 1, 38 .seqId = 6, /* See Lookup table for more details */ 39 .reserved = 0, 40 }, 41 .deviceModeArg = 2, /* Enable OPI DDR mode */ 42 .controllerMiscOption = 43 (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DdrModeEnable), 44 .deviceType = kFlexSpiDeviceType_SerialNOR, 45 .sflashPadType = kSerialFlash_8Pads, 46 .serialClkFreq = kFlexSpiSerialClk_60MHz, 47 .sflashA1Size = 64ul * 1024u * 1024u, 48 .busyOffset = 0u, 49 .busyBitPolarity = 0u, 50 .lookupTable = 51 { 52 /* Read */ 53 [0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xEE, CMD_DDR, FLEXSPI_8PAD, 0x11), 54 [1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, DUMMY_DDR, FLEXSPI_8PAD, 0x04), 55 [2] = FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP_EXE, FLEXSPI_1PAD, 0x00), 56 57 /* Read status SPI */ 58 [4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04), 59 60 /* Read Status OPI */ 61 [4 * 2 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x05, CMD_DDR, FLEXSPI_8PAD, 0xFA), 62 [4 * 2 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, DUMMY_DDR, FLEXSPI_8PAD, 0x04), 63 [4 * 2 + 2] = FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP_EXE, FLEXSPI_1PAD, 0x00), 64 65 /* Write Enable */ 66 [4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP_EXE, FLEXSPI_1PAD, 0x00), 67 68 /* Write Enable - OPI */ 69 [4 * 4 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x06, CMD_DDR, FLEXSPI_8PAD, 0xF9), 70 71 /* Erase Sector */ 72 [4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x21, CMD_DDR, FLEXSPI_8PAD, 0xDE), 73 [4 * 5 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, STOP_EXE, FLEXSPI_1PAD, 0x00), 74 75 /* Enable OPI DDR mode */ 76 [4 * 6 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x72, CMD_SDR, FLEXSPI_1PAD, 0x00), 77 [4 * 6 + 1] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x00, CMD_SDR, FLEXSPI_1PAD, 0x00), 78 [4 * 6 + 2] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x00, WRITE_SDR, FLEXSPI_1PAD, 0x01), 79 80 /* Erase Block */ 81 [4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xDC, CMD_DDR, FLEXSPI_8PAD, 0x23), 82 [4 * 8 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, STOP_EXE, FLEXSPI_1PAD, 0x00), 83 84 /* Page program */ 85 [4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x12, CMD_DDR, FLEXSPI_8PAD, 0xED), 86 [4 * 9 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, WRITE_DDR, FLEXSPI_8PAD, 0x04), 87 88 /* Erase Chip */ 89 [4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x60, CMD_DDR, FLEXSPI_8PAD, 0x9F), 90 }, 91 }, 92 .pageSize = 256u, 93 .sectorSize = 4u * 1024u, 94 .ipcmdSerialClkFreq = 1u, 95 .serialNorType = 2u, 96 .blockSize = 64u * 1024u, 97 .flashStateCtx = 0x07008200u, 98 }; 99 #endif /* BOOT_HEADER_ENABLE */ 100
