1 /*
2  * Copyright 2022 NXP
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 /***********************************************************************************************************************
8  * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
9  * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
10  **********************************************************************************************************************/
11 
12 /*
13  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
14 !!GlobalInfo
15 product: Pins v12.0
16 processor: MIMXRT1176xxxxx
17 package_id: MIMXRT1176DVMAA
18 mcu_data: ksdk2_0
19 processor_version: 12.0.0
20  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
21  */
22 
23 #include "fsl_common.h"
24 #include "fsl_iomuxc.h"
25 #include "pin_mux.h"
26 
27 /* FUNCTION ************************************************************************************************************
28  *
29  * Function Name : BOARD_InitBootPins
30  * Description   : Calls initialization functions.
31  *
32  * END ****************************************************************************************************************/
BOARD_InitBootPins(void)33 void BOARD_InitBootPins(void) {
34     BOARD_InitPins();
35 }
36 
37 /*
38  * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
39 BOARD_InitPins:
40 - options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'}
41 - pin_list:
42   - {pin_num: M15, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AD_25, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
43     open_drain: Disable, drive_strength: High, slew_rate: Slow}
44   - {pin_num: L13, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AD_24, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
45     open_drain: Disable, drive_strength: High, slew_rate: Slow}
46  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
47  */
48 
49 /* FUNCTION ************************************************************************************************************
50  *
51  * Function Name : BOARD_InitPins, assigned for the Cortex-M7F core.
52  * Description   : Configures pin routing and optionally pin electrical features.
53  *
54  * END ****************************************************************************************************************/
BOARD_InitPins(void)55 void BOARD_InitPins(void) {
56   CLOCK_EnableClock(kCLOCK_Iomuxc);           /* LPCG on: LPCG is ON. */
57 
58   IOMUXC_SetPinMux(
59       IOMUXC_GPIO_AD_24_LPUART1_TXD,          /* GPIO_AD_24 is configured as LPUART1_TXD */
60       0U);                                    /* Software Input On Field: Input Path is determined by functionality */
61   IOMUXC_SetPinMux(
62       IOMUXC_GPIO_AD_25_LPUART1_RXD,          /* GPIO_AD_25 is configured as LPUART1_RXD */
63       0U);                                    /* Software Input On Field: Input Path is determined by functionality */
64   IOMUXC_SetPinConfig(
65       IOMUXC_GPIO_AD_24_LPUART1_TXD,          /* GPIO_AD_24 PAD functional properties : */
66       0x02U);                                 /* Slew Rate Field: Slow Slew Rate
67                                                  Drive Strength Field: high drive strength
68                                                  Pull / Keep Select Field: Pull Disable, Highz
69                                                  Pull Up / Down Config. Field: Weak pull down
70                                                  Open Drain Field: Disabled
71                                                  Domain write protection: Both cores are allowed
72                                                  Domain write protection lock: Neither of DWP bits is locked */
73   IOMUXC_SetPinConfig(
74       IOMUXC_GPIO_AD_25_LPUART1_RXD,          /* GPIO_AD_25 PAD functional properties : */
75       0x02U);                                 /* Slew Rate Field: Slow Slew Rate
76                                                  Drive Strength Field: high drive strength
77                                                  Pull / Keep Select Field: Pull Disable, Highz
78                                                  Pull Up / Down Config. Field: Weak pull down
79                                                  Open Drain Field: Disabled
80                                                  Domain write protection: Both cores are allowed
81                                                  Domain write protection lock: Neither of DWP bits is locked */
82 }
83 
84 /***********************************************************************************************************************
85  * EOF
86  **********************************************************************************************************************/
87