1 /* 2 * Copyright 2022 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _CLOCK_CONFIG_H_ 9 #define _CLOCK_CONFIG_H_ 10 11 #include "fsl_common.h" 12 13 /******************************************************************************* 14 * Definitions 15 ******************************************************************************/ 16 #define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ 17 18 #define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ 19 /******************************************************************************* 20 ************************ BOARD_InitBootClocks function ************************ 21 ******************************************************************************/ 22 23 #if defined(__cplusplus) 24 extern "C" { 25 #endif /* __cplusplus*/ 26 27 /*! 28 * @brief This function executes default configuration of clocks. 29 * 30 */ 31 void BOARD_InitBootClocks(void); 32 33 #if defined(__cplusplus) 34 } 35 #endif /* __cplusplus*/ 36 37 /******************************************************************************* 38 ********************** Configuration BOARD_BootClockRUN *********************** 39 ******************************************************************************/ 40 /******************************************************************************* 41 * Definitions for BOARD_BootClockRUN configuration 42 ******************************************************************************/ 43 #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ 44 45 /* Clock outputs (values are in Hz): */ 46 #define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL 47 #define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL 48 #define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL 49 #define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL 50 #define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL 51 #define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL 52 #define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL 53 #define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 0UL 54 #define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 0UL 55 #define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL 56 #define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL 57 #define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL 58 #define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL 59 #define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL 60 #define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL 61 #define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL 62 #define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL 63 #define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL 64 #define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL 65 #define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL 66 #define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL 67 #define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL 68 #define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL 69 #define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL 70 #define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL 71 #define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL 72 #define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL 73 #define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL 74 #define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL 75 #define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL 76 #define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL 77 #define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL 78 #define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL 79 #define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 62500000UL 80 #define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL 81 #define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL 82 #define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL 83 #define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL 84 #define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL 85 #define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 176000000UL 86 #define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 176000000UL 87 88 /*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. 89 */ 90 extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; 91 /*! @brief Sys PLL for BOARD_BootClockRUN configuration. 92 */ 93 extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; 94 /*! @brief Enet PLL set for BOARD_BootClockRUN configuration. 95 */ 96 extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; 97 98 /******************************************************************************* 99 * API for BOARD_BootClockRUN configuration 100 ******************************************************************************/ 101 #if defined(__cplusplus) 102 extern "C" { 103 #endif /* __cplusplus*/ 104 105 /*! 106 * @brief This function executes configuration of clocks. 107 * 108 */ 109 void BOARD_BootClockRUN(void); 110 111 #if defined(__cplusplus) 112 } 113 #endif /* __cplusplus*/ 114 115 /******************************************************************************* 116 ******************* Configuration BOARD_BootClockRUN_400M ********************* 117 ******************************************************************************/ 118 /******************************************************************************* 119 * Definitions for BOARD_BootClockRUN_400M configuration 120 ******************************************************************************/ 121 #define BOARD_BOOTCLOCKRUN_400M_CORE_CLOCK 396000000U /*!< Core clock frequency: 396000000Hz */ 122 123 /* Clock outputs (values are in Hz): */ 124 #define BOARD_BOOTCLOCKRUN_400M_AHB_CLK_ROOT 396000000UL 125 #define BOARD_BOOTCLOCKRUN_400M_CAN_CLK_ROOT 40000000UL 126 #define BOARD_BOOTCLOCKRUN_400M_CKIL_SYNC_CLK_ROOT 32768UL 127 #define BOARD_BOOTCLOCKRUN_400M_CLKO1_CLK 0UL 128 #define BOARD_BOOTCLOCKRUN_400M_CLKO2_CLK 0UL 129 #define BOARD_BOOTCLOCKRUN_400M_CLK_1M 1000000UL 130 #define BOARD_BOOTCLOCKRUN_400M_CLK_24M 24000000UL 131 #define BOARD_BOOTCLOCKRUN_400M_ENET_125M_CLK 0UL 132 #define BOARD_BOOTCLOCKRUN_400M_ENET_25M_REF_CLK 0UL 133 #define BOARD_BOOTCLOCKRUN_400M_ENET_500M_REF_CLK 500000000UL 134 #define BOARD_BOOTCLOCKRUN_400M_ENET_REF_CLK 0UL 135 #define BOARD_BOOTCLOCKRUN_400M_ENET_TX_CLK 0UL 136 #define BOARD_BOOTCLOCKRUN_400M_FLEXIO1_CLK_ROOT 30000000UL 137 #define BOARD_BOOTCLOCKRUN_400M_FLEXSPI_CLK_ROOT 132000000UL 138 #define BOARD_BOOTCLOCKRUN_400M_GPT1_IPG_CLK_HIGHFREQ 49500000UL 139 #define BOARD_BOOTCLOCKRUN_400M_GPT2_IPG_CLK_HIGHFREQ 49500000UL 140 #define BOARD_BOOTCLOCKRUN_400M_IPG_CLK_ROOT 99000000UL 141 #define BOARD_BOOTCLOCKRUN_400M_LPI2C_CLK_ROOT 60000000UL 142 #define BOARD_BOOTCLOCKRUN_400M_LPSPI_CLK_ROOT 105600000UL 143 #define BOARD_BOOTCLOCKRUN_400M_MQS_MCLK 63529411UL 144 #define BOARD_BOOTCLOCKRUN_400M_PERCLK_CLK_ROOT 49500000UL 145 #define BOARD_BOOTCLOCKRUN_400M_SAI1_CLK_ROOT 63529411UL 146 #define BOARD_BOOTCLOCKRUN_400M_SAI1_MCLK1 63529411UL 147 #define BOARD_BOOTCLOCKRUN_400M_SAI1_MCLK2 63529411UL 148 #define BOARD_BOOTCLOCKRUN_400M_SAI1_MCLK3 30000000UL 149 #define BOARD_BOOTCLOCKRUN_400M_SAI2_CLK_ROOT 63529411UL 150 #define BOARD_BOOTCLOCKRUN_400M_SAI2_MCLK1 63529411UL 151 #define BOARD_BOOTCLOCKRUN_400M_SAI2_MCLK2 0UL 152 #define BOARD_BOOTCLOCKRUN_400M_SAI2_MCLK3 30000000UL 153 #define BOARD_BOOTCLOCKRUN_400M_SAI3_CLK_ROOT 63529411UL 154 #define BOARD_BOOTCLOCKRUN_400M_SAI3_MCLK1 63529411UL 155 #define BOARD_BOOTCLOCKRUN_400M_SAI3_MCLK2 0UL 156 #define BOARD_BOOTCLOCKRUN_400M_SAI3_MCLK3 30000000UL 157 #define BOARD_BOOTCLOCKRUN_400M_SEMC_CLK_ROOT 49500000UL 158 #define BOARD_BOOTCLOCKRUN_400M_SPDIF0_CLK_ROOT 30000000UL 159 #define BOARD_BOOTCLOCKRUN_400M_SPDIF0_EXTCLK_OUT 0UL 160 #define BOARD_BOOTCLOCKRUN_400M_TRACE_CLK_ROOT 132000000UL 161 #define BOARD_BOOTCLOCKRUN_400M_UART_CLK_ROOT 80000000UL 162 #define BOARD_BOOTCLOCKRUN_400M_USBPHY1_CLK 0UL 163 #define BOARD_BOOTCLOCKRUN_400M_USDHC1_CLK_ROOT 176000000UL 164 #define BOARD_BOOTCLOCKRUN_400M_USDHC2_CLK_ROOT 176000000UL 165 166 /*! @brief Usb1 PLL set for BOARD_BootClockRUN_400M configuration. 167 */ 168 extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN_400M; 169 /*! @brief Sys PLL for BOARD_BootClockRUN_400M configuration. 170 */ 171 extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN_400M; 172 /*! @brief Enet PLL set for BOARD_BootClockRUN_400M configuration. 173 */ 174 extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN_400M; 175 176 /******************************************************************************* 177 * API for BOARD_BootClockRUN_400M configuration 178 ******************************************************************************/ 179 #if defined(__cplusplus) 180 extern "C" { 181 #endif /* __cplusplus*/ 182 183 /*! 184 * @brief This function executes configuration of clocks. 185 * 186 */ 187 void BOARD_BootClockRUN_400M(void); 188 189 #if defined(__cplusplus) 190 } 191 #endif /* __cplusplus*/ 192 193 #endif /* _CLOCK_CONFIG_H_ */ 194 195
