1 /* 2 * Copyright 2018-2020 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__ 9 #define __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__ 10 11 #include <stdint.h> 12 #include <stdbool.h> 13 #include "fsl_common.h" 14 15 /*! @name Driver version */ 16 /*@{*/ 17 /*! @brief XIP_BOARD driver version 2.0.1. */ 18 #define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) 19 /*@}*/ 20 21 /* FLEXSPI memory config block related defintions */ 22 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian 23 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 24 #define FLEXSPI_CFG_BLK_SIZE (512) 25 26 /* FLEXSPI Feature related definitions */ 27 #define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 28 29 /* Lookup table related defintions */ 30 #define CMD_INDEX_READ 0 31 #define CMD_INDEX_READSTATUS 1 32 #define CMD_INDEX_WRITEENABLE 2 33 #define CMD_INDEX_WRITE 4 34 35 #define CMD_LUT_SEQ_IDX_READ 0 36 #define CMD_LUT_SEQ_IDX_READSTATUS 1 37 #define CMD_LUT_SEQ_IDX_WRITEENABLE 3 38 #define CMD_LUT_SEQ_IDX_WRITE 9 39 40 #define CMD_SDR 0x01 41 #define CMD_DDR 0x21 42 #define RADDR_SDR 0x02 43 #define RADDR_DDR 0x22 44 #define CADDR_SDR 0x03 45 #define CADDR_DDR 0x23 46 #define MODE1_SDR 0x04 47 #define MODE1_DDR 0x24 48 #define MODE2_SDR 0x05 49 #define MODE2_DDR 0x25 50 #define MODE4_SDR 0x06 51 #define MODE4_DDR 0x26 52 #define MODE8_SDR 0x07 53 #define MODE8_DDR 0x27 54 #define WRITE_SDR 0x08 55 #define WRITE_DDR 0x28 56 #define READ_SDR 0x09 57 #define READ_DDR 0x29 58 #define LEARN_SDR 0x0A 59 #define LEARN_DDR 0x2A 60 #define DATSZ_SDR 0x0B 61 #define DATSZ_DDR 0x2B 62 #define DUMMY_SDR 0x0C 63 #define DUMMY_DDR 0x2C 64 #define DUMMY_RWDS_SDR 0x0D 65 #define DUMMY_RWDS_DDR 0x2D 66 #define JMP_ON_CS 0x1F 67 #define STOP 0 68 69 #define FLEXSPI_1PAD 0 70 #define FLEXSPI_2PAD 1 71 #define FLEXSPI_4PAD 2 72 #define FLEXSPI_8PAD 3 73 74 #define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ 75 (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ 76 FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) 77 78 //!@brief Definitions for FlexSPI Serial Clock Frequency 79 typedef enum _FlexSpiSerialClockFreq 80 { 81 kFlexSpiSerialClk_30MHz = 1, 82 kFlexSpiSerialClk_50MHz = 2, 83 kFlexSpiSerialClk_60MHz = 3, 84 kFlexSpiSerialClk_75MHz = 4, 85 kFlexSpiSerialClk_80MHz = 5, 86 kFlexSpiSerialClk_100MHz = 6, 87 kFlexSpiSerialClk_133MHz = 7, 88 } flexspi_serial_clk_freq_t; 89 90 //!@brief FlexSPI clock configuration type 91 enum 92 { 93 kFlexSpiClk_SDR, //!< Clock configure for SDR mode 94 kFlexSpiClk_DDR, //!< Clock configurat for DDR mode 95 }; 96 97 //!@brief FlexSPI Read Sample Clock Source definition 98 typedef enum _FlashReadSampleClkSource 99 { 100 kFlexSPIReadSampleClk_LoopbackInternally = 0, 101 kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, 102 kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, 103 kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, 104 } flexspi_read_sample_clk_t; 105 106 //!@brief Misc feature bit definitions 107 enum 108 { 109 kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable 110 kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable 111 kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable 112 kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable 113 kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable 114 kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable 115 kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. 116 }; 117 118 //!@brief Flash Type Definition 119 enum 120 { 121 kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR 122 kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND 123 kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH 124 kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND 125 kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs 126 }; 127 128 //!@brief Flash Pad Definitions 129 enum 130 { 131 kSerialFlash_1Pad = 1, 132 kSerialFlash_2Pads = 2, 133 kSerialFlash_4Pads = 4, 134 kSerialFlash_8Pads = 8, 135 }; 136 137 //!@brief FlexSPI LUT Sequence structure 138 typedef struct _lut_sequence 139 { 140 uint8_t seqNum; //!< Sequence Number, valid number: 1-16 141 uint8_t seqId; //!< Sequence Index, valid number: 0-15 142 uint16_t reserved; 143 } flexspi_lut_seq_t; 144 145 //!@brief Flash Configuration Command Type 146 enum 147 { 148 kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc 149 kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command 150 kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode 151 kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode 152 kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode 153 kDeviceConfigCmdType_Reset, //!< Reset device command 154 }; 155 156 //!@brief FlexSPI Memory Configuration Block 157 typedef struct _FlexSPIConfig 158 { 159 uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL 160 uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix 161 uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use 162 uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 163 uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 164 uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 165 uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For 166 //! Serial NAND, need to refer to datasheet 167 uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable 168 uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, 169 //! Generic configuration, etc. 170 uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for 171 //! DPI/QPI/OPI switch or reset command 172 flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt 173 //! sequence number, [31:16] Reserved 174 uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration 175 uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable 176 uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe 177 flexspi_lut_seq_t 178 configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq 179 uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use 180 uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands 181 uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use 182 uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more 183 //! details 184 uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details 185 uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal 186 uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot 187 //! Chapter for more details 188 uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot 189 //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH 190 uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use 191 uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 192 uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 193 uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 194 uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 195 uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value 196 uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value 197 uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value 198 uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value 199 uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command 200 uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands 201 uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns 202 uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 203 uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - 204 //! busy flag is 0 when flash device is busy 205 uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences 206 flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences 207 uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use 208 } flexspi_mem_config_t; 209 210 /* */ 211 #define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 212 #define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 213 #define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 214 #define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 215 #define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 216 #define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 217 #define NOR_CMD_INDEX_DUMMY 6 //!< 6 218 #define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 219 220 #define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block 221 #define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ 222 CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block 223 #define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ 224 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block 225 #define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ 226 CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block 227 #define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ 228 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block 229 #define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block 230 #define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block 231 #define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ 232 CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block 233 #define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block 234 #define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block 235 #define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ 236 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block 237 #define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ 238 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk 239 240 /* 241 * Serial NOR configuration block 242 */ 243 typedef struct _flexspi_nor_config 244 { 245 flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI 246 uint32_t pageSize; //!< Page size of Serial NOR 247 uint32_t sectorSize; //!< Sector size of Serial NOR 248 uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command 249 uint8_t isUniformBlockSize; //!< Sector/Block size is the same 250 uint8_t reserved0[2]; //!< Reserved for future use 251 uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 252 uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command 253 uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false 254 uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution 255 uint32_t blockSize; //!< Block size 256 uint32_t reserve2[11]; //!< Reserved for future use 257 } flexspi_nor_config_t; 258 259 #ifdef __cplusplus 260 extern "C" { 261 #endif 262 263 #ifdef __cplusplus 264 } 265 #endif 266 #endif /* __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__ */ 267
