1 /* 2 * Copyright 2022 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _CLOCK_CONFIG_H_ 9 #define _CLOCK_CONFIG_H_ 10 11 #include "fsl_common.h" 12 13 /******************************************************************************* 14 * Definitions 15 ******************************************************************************/ 16 #define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ 17 18 #define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ 19 /******************************************************************************* 20 ************************ BOARD_InitBootClocks function ************************ 21 ******************************************************************************/ 22 23 #if defined(__cplusplus) 24 extern "C" { 25 #endif /* __cplusplus*/ 26 27 /*! 28 * @brief This function executes default configuration of clocks. 29 * 30 */ 31 void BOARD_InitBootClocks(void); 32 33 #if defined(__cplusplus) 34 } 35 #endif /* __cplusplus*/ 36 37 /******************************************************************************* 38 ********************** Configuration BOARD_BootClockRUN *********************** 39 ******************************************************************************/ 40 /******************************************************************************* 41 * Definitions for BOARD_BootClockRUN configuration 42 ******************************************************************************/ 43 #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ 44 45 /* Clock outputs (values are in Hz): */ 46 #define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL 47 #define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL 48 #define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL 49 #define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL 50 #define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL 51 #define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL 52 #define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL 53 #define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL 54 #define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL 55 #define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL 56 #define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL 57 #define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL 58 #define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL 59 #define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL 60 #define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL 61 #define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL 62 #define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL 63 #define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL 64 #define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL 65 #define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL 66 #define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL 67 #define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL 68 #define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL 69 #define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL 70 #define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL 71 #define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL 72 #define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL 73 #define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL 74 #define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL 75 #define BOARD_BOOTCLOCKRUN_USBPHY_CLK 0UL 76 77 /*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. 78 */ 79 extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; 80 /*! @brief Sys PLL for BOARD_BootClockRUN configuration. 81 */ 82 extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; 83 /*! @brief Enet PLL set for BOARD_BootClockRUN configuration. 84 */ 85 extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN; 86 87 /******************************************************************************* 88 * API for BOARD_BootClockRUN configuration 89 ******************************************************************************/ 90 #if defined(__cplusplus) 91 extern "C" { 92 #endif /* __cplusplus*/ 93 94 /*! 95 * @brief This function executes configuration of clocks. 96 * 97 */ 98 void BOARD_BootClockRUN(void); 99 100 #if defined(__cplusplus) 101 } 102 #endif /* __cplusplus*/ 103 104 /******************************************************************************* 105 ******************* Configuration BOARD_BootClockRUN_400M ********************* 106 ******************************************************************************/ 107 /******************************************************************************* 108 * Definitions for BOARD_BootClockRUN_400M configuration 109 ******************************************************************************/ 110 #define BOARD_BOOTCLOCKRUN_400M_CORE_CLOCK 396000000U /*!< Core clock frequency: 396000000Hz */ 111 112 /* Clock outputs (values are in Hz): */ 113 #define BOARD_BOOTCLOCKRUN_400M_ADC_ALT_CLK 40000000UL 114 #define BOARD_BOOTCLOCKRUN_400M_CKIL_SYNC_CLK_ROOT 32768UL 115 #define BOARD_BOOTCLOCKRUN_400M_CLKO1_CLK 0UL 116 #define BOARD_BOOTCLOCKRUN_400M_CLKO2_CLK 0UL 117 #define BOARD_BOOTCLOCKRUN_400M_CLK_1M 1000000UL 118 #define BOARD_BOOTCLOCKRUN_400M_CLK_24M 24000000UL 119 #define BOARD_BOOTCLOCKRUN_400M_CORE_CLK_ROOT 396000000UL 120 #define BOARD_BOOTCLOCKRUN_400M_ENET_500M_REF_CLK 500000000UL 121 #define BOARD_BOOTCLOCKRUN_400M_FLEXIO1_CLK_ROOT 30000000UL 122 #define BOARD_BOOTCLOCKRUN_400M_FLEXSPI_CLK_ROOT 132000000UL 123 #define BOARD_BOOTCLOCKRUN_400M_GPT1_IPG_CLK_HIGHFREQ 49500000UL 124 #define BOARD_BOOTCLOCKRUN_400M_GPT2_IPG_CLK_HIGHFREQ 49500000UL 125 #define BOARD_BOOTCLOCKRUN_400M_IPG_CLK_ROOT 99000000UL 126 #define BOARD_BOOTCLOCKRUN_400M_LPI2C_CLK_ROOT 60000000UL 127 #define BOARD_BOOTCLOCKRUN_400M_LPSPI_CLK_ROOT 105600000UL 128 #define BOARD_BOOTCLOCKRUN_400M_MQS_MCLK 63529411UL 129 #define BOARD_BOOTCLOCKRUN_400M_PERCLK_CLK_ROOT 49500000UL 130 #define BOARD_BOOTCLOCKRUN_400M_SAI1_CLK_ROOT 63529411UL 131 #define BOARD_BOOTCLOCKRUN_400M_SAI1_MCLK1 63529411UL 132 #define BOARD_BOOTCLOCKRUN_400M_SAI1_MCLK2 63529411UL 133 #define BOARD_BOOTCLOCKRUN_400M_SAI1_MCLK3 30000000UL 134 #define BOARD_BOOTCLOCKRUN_400M_SAI3_CLK_ROOT 63529411UL 135 #define BOARD_BOOTCLOCKRUN_400M_SAI3_MCLK1 63529411UL 136 #define BOARD_BOOTCLOCKRUN_400M_SAI3_MCLK2 0UL 137 #define BOARD_BOOTCLOCKRUN_400M_SAI3_MCLK3 30000000UL 138 #define BOARD_BOOTCLOCKRUN_400M_SPDIF0_CLK_ROOT 30000000UL 139 #define BOARD_BOOTCLOCKRUN_400M_SPDIF0_EXTCLK_OUT 0UL 140 #define BOARD_BOOTCLOCKRUN_400M_TRACE_CLK_ROOT 132000000UL 141 #define BOARD_BOOTCLOCKRUN_400M_UART_CLK_ROOT 80000000UL 142 #define BOARD_BOOTCLOCKRUN_400M_USBPHY_CLK 0UL 143 144 /*! @brief Usb1 PLL set for BOARD_BootClockRUN_400M configuration. 145 */ 146 extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN_400M; 147 /*! @brief Sys PLL for BOARD_BootClockRUN_400M configuration. 148 */ 149 extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN_400M; 150 /*! @brief Enet PLL set for BOARD_BootClockRUN_400M configuration. 151 */ 152 extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN_400M; 153 154 /******************************************************************************* 155 * API for BOARD_BootClockRUN_400M configuration 156 ******************************************************************************/ 157 #if defined(__cplusplus) 158 extern "C" { 159 #endif /* __cplusplus*/ 160 161 /*! 162 * @brief This function executes configuration of clocks. 163 * 164 */ 165 void BOARD_BootClockRUN_400M(void); 166 167 #if defined(__cplusplus) 168 } 169 #endif /* __cplusplus*/ 170 171 #endif /* _CLOCK_CONFIG_H_ */ 172 173