1 /*
2 * Copyright 2020-2022 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /*
9 * How to setup clock using clock driver functions:
10 *
11 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
12 *
13 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
14 *
15 * 3. Call CLOCK_SetRootClock() to configure corresponding module clock source and divider.
16 *
17 */
18
19 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
20 !!GlobalInfo
21 product: Clocks v8.0
22 processor: MIMXRT1176xxxxx
23 package_id: MIMXRT1176DVMAA
24 mcu_data: ksdk2_0
25 processor_version: 0.0.0
26 board: MIMXRT1170-EVKB
27 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
28
29 #include "clock_config.h"
30 #include "fsl_iomuxc.h"
31 #include "fsl_dcdc.h"
32 #include "fsl_pmu.h"
33 #include "fsl_clock.h"
34
35 /*******************************************************************************
36 * Definitions
37 ******************************************************************************/
38
39 /*******************************************************************************
40 * Variables
41 ******************************************************************************/
42
43 /*******************************************************************************
44 ************************ BOARD_InitBootClocks function ************************
45 ******************************************************************************/
BOARD_InitBootClocks(void)46 void BOARD_InitBootClocks(void)
47 {
48 BOARD_BootClockRUN();
49 }
50
51 #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
52 #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
53 /* This function should not run from SDRAM since it will change SEMC configuration. */
54 AT_QUICKACCESS_SECTION_CODE(void UpdateSemcClock(void));
UpdateSemcClock(void)55 void UpdateSemcClock(void)
56 {
57 /* Enable self-refresh mode and update semc clock root to 200MHz. */
58 SEMC->IPCMD = 0xA55A000D;
59 while ((SEMC->INTR & 0x3) == 0)
60 ;
61 SEMC->INTR = 0x3;
62 SEMC->DCCR = 0x0B;
63 /*
64 * Currently we are using SEMC parameter which fit both 166MHz and 200MHz, only
65 * need to change the SEMC clock root here. If customer is using their own DCD and
66 * want to switch from 166MHz to 200MHz, extra SEMC configuration might need to be
67 * adjusted here to fine tune the SDRAM performance
68 */
69 CCM->CLOCK_ROOT[kCLOCK_Root_Semc].CONTROL = 0x602;
70 }
71 #endif
72 #endif
73
74 /*******************************************************************************
75 ********************** Configuration BOARD_BootClockRUN ***********************
76 ******************************************************************************/
77 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
78 !!Configuration
79 name: BOARD_BootClockRUN
80 called_from_default_init: true
81 outputs:
82 - {id: ACMP_CLK_ROOT.outFreq, value: 24 MHz}
83 - {id: ADC1_CLK_ROOT.outFreq, value: 24 MHz}
84 - {id: ADC2_CLK_ROOT.outFreq, value: 24 MHz}
85 - {id: ARM_PLL_CLK.outFreq, value: 996 MHz}
86 - {id: ASRC_CLK_ROOT.outFreq, value: 24 MHz}
87 - {id: AXI_CLK_ROOT.outFreq, value: 996 MHz}
88 - {id: BUS_CLK_ROOT.outFreq, value: 240 MHz}
89 - {id: BUS_LPSR_CLK_ROOT.outFreq, value: 160 MHz}
90 - {id: CAN1_CLK_ROOT.outFreq, value: 24 MHz}
91 - {id: CAN2_CLK_ROOT.outFreq, value: 24 MHz}
92 - {id: CAN3_CLK_ROOT.outFreq, value: 24 MHz}
93 - {id: CCM_CLKO1_CLK_ROOT.outFreq, value: 24 MHz}
94 - {id: CCM_CLKO2_CLK_ROOT.outFreq, value: 24 MHz}
95 - {id: CLK_1M.outFreq, value: 1 MHz}
96 - {id: CSI2_CLK_ROOT.outFreq, value: 24 MHz}
97 - {id: CSI2_ESC_CLK_ROOT.outFreq, value: 24 MHz}
98 - {id: CSI2_UI_CLK_ROOT.outFreq, value: 24 MHz}
99 - {id: CSI_CLK_ROOT.outFreq, value: 24 MHz}
100 - {id: CSSYS_CLK_ROOT.outFreq, value: 24 MHz}
101 - {id: CSTRACE_CLK_ROOT.outFreq, value: 132 MHz}
102 - {id: ELCDIF_CLK_ROOT.outFreq, value: 24 MHz}
103 - {id: EMV1_CLK_ROOT.outFreq, value: 24 MHz}
104 - {id: EMV2_CLK_ROOT.outFreq, value: 24 MHz}
105 - {id: ENET1_CLK_ROOT.outFreq, value: 24 MHz}
106 - {id: ENET2_CLK_ROOT.outFreq, value: 24 MHz}
107 - {id: ENET_1G_TX_CLK.outFreq, value: 24 MHz}
108 - {id: ENET_25M_CLK_ROOT.outFreq, value: 24 MHz}
109 - {id: ENET_QOS_CLK_ROOT.outFreq, value: 24 MHz}
110 - {id: ENET_TIMER1_CLK_ROOT.outFreq, value: 24 MHz}
111 - {id: ENET_TIMER2_CLK_ROOT.outFreq, value: 24 MHz}
112 - {id: ENET_TIMER3_CLK_ROOT.outFreq, value: 24 MHz}
113 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 24 MHz}
114 - {id: FLEXIO2_CLK_ROOT.outFreq, value: 24 MHz}
115 - {id: FLEXSPI1_CLK_ROOT.outFreq, value: 24 MHz}
116 - {id: FLEXSPI2_CLK_ROOT.outFreq, value: 24 MHz}
117 - {id: GC355_CLK_ROOT.outFreq, value: 492.0000125 MHz}
118 - {id: GPT1_CLK_ROOT.outFreq, value: 24 MHz}
119 - {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz}
120 - {id: GPT2_CLK_ROOT.outFreq, value: 24 MHz}
121 - {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz}
122 - {id: GPT3_CLK_ROOT.outFreq, value: 24 MHz}
123 - {id: GPT3_ipg_clk_highfreq.outFreq, value: 24 MHz}
124 - {id: GPT4_CLK_ROOT.outFreq, value: 24 MHz}
125 - {id: GPT4_ipg_clk_highfreq.outFreq, value: 24 MHz}
126 - {id: GPT5_CLK_ROOT.outFreq, value: 24 MHz}
127 - {id: GPT5_ipg_clk_highfreq.outFreq, value: 24 MHz}
128 - {id: GPT6_CLK_ROOT.outFreq, value: 24 MHz}
129 - {id: GPT6_ipg_clk_highfreq.outFreq, value: 24 MHz}
130 - {id: LCDIFV2_CLK_ROOT.outFreq, value: 24 MHz}
131 - {id: LPI2C1_CLK_ROOT.outFreq, value: 24 MHz}
132 - {id: LPI2C2_CLK_ROOT.outFreq, value: 24 MHz}
133 - {id: LPI2C3_CLK_ROOT.outFreq, value: 24 MHz}
134 - {id: LPI2C4_CLK_ROOT.outFreq, value: 24 MHz}
135 - {id: LPI2C5_CLK_ROOT.outFreq, value: 24 MHz}
136 - {id: LPI2C6_CLK_ROOT.outFreq, value: 24 MHz}
137 - {id: LPSPI1_CLK_ROOT.outFreq, value: 24 MHz}
138 - {id: LPSPI2_CLK_ROOT.outFreq, value: 24 MHz}
139 - {id: LPSPI3_CLK_ROOT.outFreq, value: 24 MHz}
140 - {id: LPSPI4_CLK_ROOT.outFreq, value: 24 MHz}
141 - {id: LPSPI5_CLK_ROOT.outFreq, value: 24 MHz}
142 - {id: LPSPI6_CLK_ROOT.outFreq, value: 24 MHz}
143 - {id: LPUART10_CLK_ROOT.outFreq, value: 24 MHz}
144 - {id: LPUART11_CLK_ROOT.outFreq, value: 24 MHz}
145 - {id: LPUART12_CLK_ROOT.outFreq, value: 24 MHz}
146 - {id: LPUART1_CLK_ROOT.outFreq, value: 24 MHz}
147 - {id: LPUART2_CLK_ROOT.outFreq, value: 24 MHz}
148 - {id: LPUART3_CLK_ROOT.outFreq, value: 24 MHz}
149 - {id: LPUART4_CLK_ROOT.outFreq, value: 24 MHz}
150 - {id: LPUART5_CLK_ROOT.outFreq, value: 24 MHz}
151 - {id: LPUART6_CLK_ROOT.outFreq, value: 24 MHz}
152 - {id: LPUART7_CLK_ROOT.outFreq, value: 24 MHz}
153 - {id: LPUART8_CLK_ROOT.outFreq, value: 24 MHz}
154 - {id: LPUART9_CLK_ROOT.outFreq, value: 24 MHz}
155 - {id: M4_CLK_ROOT.outFreq, value: 4320/11 MHz}
156 - {id: M4_SYSTICK_CLK_ROOT.outFreq, value: 24 MHz}
157 - {id: M7_CLK_ROOT.outFreq, value: 996 MHz}
158 - {id: M7_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz}
159 - {id: MIC_CLK_ROOT.outFreq, value: 24 MHz}
160 - {id: MIPI_DSI_TX_CLK_ESC_ROOT.outFreq, value: 24 MHz}
161 - {id: MIPI_ESC_CLK_ROOT.outFreq, value: 24 MHz}
162 - {id: MIPI_REF_CLK_ROOT.outFreq, value: 24 MHz}
163 - {id: MQS_CLK_ROOT.outFreq, value: 24 MHz}
164 - {id: MQS_MCLK.outFreq, value: 24 MHz}
165 - {id: OSC_24M.outFreq, value: 24 MHz}
166 - {id: OSC_32K.outFreq, value: 32.768 kHz}
167 - {id: OSC_RC_16M.outFreq, value: 16 MHz}
168 - {id: OSC_RC_400M.outFreq, value: 400 MHz}
169 - {id: OSC_RC_48M.outFreq, value: 48 MHz}
170 - {id: OSC_RC_48M_DIV2.outFreq, value: 24 MHz}
171 - {id: PLL_VIDEO_CLK.outFreq, value: 984.000025 MHz}
172 - {id: SAI1_CLK_ROOT.outFreq, value: 24 MHz}
173 - {id: SAI1_MCLK1.outFreq, value: 24 MHz}
174 - {id: SAI1_MCLK3.outFreq, value: 24 MHz}
175 - {id: SAI2_CLK_ROOT.outFreq, value: 24 MHz}
176 - {id: SAI2_MCLK1.outFreq, value: 24 MHz}
177 - {id: SAI2_MCLK3.outFreq, value: 24 MHz}
178 - {id: SAI3_CLK_ROOT.outFreq, value: 24 MHz}
179 - {id: SAI3_MCLK1.outFreq, value: 24 MHz}
180 - {id: SAI3_MCLK3.outFreq, value: 24 MHz}
181 - {id: SAI4_CLK_ROOT.outFreq, value: 24 MHz}
182 - {id: SAI4_MCLK1.outFreq, value: 24 MHz}
183 - {id: SEMC_CLK_ROOT.outFreq, value: 198 MHz}
184 - {id: SPDIF_CLK_ROOT.outFreq, value: 24 MHz}
185 - {id: SYS_PLL2_CLK.outFreq, value: 528 MHz}
186 - {id: SYS_PLL2_PFD0_CLK.outFreq, value: 352 MHz}
187 - {id: SYS_PLL2_PFD1_CLK.outFreq, value: 594 MHz}
188 - {id: SYS_PLL2_PFD2_CLK.outFreq, value: 396 MHz}
189 - {id: SYS_PLL2_PFD3_CLK.outFreq, value: 297 MHz}
190 - {id: SYS_PLL3_CLK.outFreq, value: 480 MHz}
191 - {id: SYS_PLL3_DIV2_CLK.outFreq, value: 240 MHz}
192 - {id: SYS_PLL3_PFD0_CLK.outFreq, value: 8640/13 MHz}
193 - {id: SYS_PLL3_PFD1_CLK.outFreq, value: 8640/17 MHz}
194 - {id: SYS_PLL3_PFD2_CLK.outFreq, value: 270 MHz}
195 - {id: SYS_PLL3_PFD3_CLK.outFreq, value: 4320/11 MHz}
196 - {id: USDHC1_CLK_ROOT.outFreq, value: 24 MHz}
197 - {id: USDHC2_CLK_ROOT.outFreq, value: 24 MHz}
198 settings:
199 - {id: CoreBusClockRootsInitializationConfig, value: selectedCore}
200 - {id: SOCDomainVoltage, value: OD}
201 - {id: ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG, value: Low}
202 - {id: ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG, value: Enabled}
203 - {id: ANADIG_PLL.PLL_AUDIO_BYPASS.sel, value: ANADIG_OSC.OSC_24M}
204 - {id: ANADIG_PLL.PLL_VIDEO.denom, value: '960000'}
205 - {id: ANADIG_PLL.PLL_VIDEO.div, value: '41'}
206 - {id: ANADIG_PLL.PLL_VIDEO.num, value: '1'}
207 - {id: ANADIG_PLL.SYS_PLL1_BYPASS.sel, value: ANADIG_OSC.OSC_24M}
208 - {id: ANADIG_PLL.SYS_PLL2.denom, value: '268435455'}
209 - {id: ANADIG_PLL.SYS_PLL2.div, value: '22'}
210 - {id: ANADIG_PLL.SYS_PLL2.num, value: '0'}
211 - {id: ANADIG_PLL.SYS_PLL2_SS_DIV.scale, value: '268435455'}
212 - {id: ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale, value: '22', locked: true}
213 - {id: ANADIG_PLL.SYS_PLL3_PFD3_MUL.scale, value: '18', locked: true}
214 - {id: ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG, value: Enabled}
215 - {id: ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG, value: Disabled}
216 - {id: ANADIG_PLL_PLL_VIDEO_CTRL0_POWERUP_CFG, value: Enabled}
217 - {id: ANADIG_PLL_SYS_PLL1_CTRL0_POWERUP_CFG, value: Disabled}
218 - {id: ANADIG_PLL_SYS_PLL1_CTRL_GATE_CFG, value: Disabled}
219 - {id: ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG, value: Enabled}
220 - {id: ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG, value: Enabled}
221 - {id: ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG, value: Enabled}
222 - {id: CCM.CLOCK_ROOT0.MUX.sel, value: ANADIG_PLL.ARM_PLL_CLK}
223 - {id: CCM.CLOCK_ROOT1.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD3_CLK}
224 - {id: CCM.CLOCK_ROOT2.DIV.scale, value: '2'}
225 - {id: CCM.CLOCK_ROOT2.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
226 - {id: CCM.CLOCK_ROOT25.DIV.scale, value: '22'}
227 - {id: CCM.CLOCK_ROOT25.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
228 - {id: CCM.CLOCK_ROOT26.DIV.scale, value: '22'}
229 - {id: CCM.CLOCK_ROOT26.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
230 - {id: CCM.CLOCK_ROOT3.DIV.scale, value: '3'}
231 - {id: CCM.CLOCK_ROOT3.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
232 - {id: CCM.CLOCK_ROOT4.DIV.scale, value: '3'}
233 - {id: CCM.CLOCK_ROOT4.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD1_CLK}
234 - {id: CCM.CLOCK_ROOT6.DIV.scale, value: '4'}
235 - {id: CCM.CLOCK_ROOT6.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
236 - {id: CCM.CLOCK_ROOT68.DIV.scale, value: '2'}
237 - {id: CCM.CLOCK_ROOT68.MUX.sel, value: ANADIG_PLL.PLL_VIDEO_CLK}
238 - {id: CCM.CLOCK_ROOT8.DIV.scale, value: '240'}
239 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
240
241 /*******************************************************************************
242 * Variables for BOARD_BootClockRUN configuration
243 ******************************************************************************/
244
245 #ifndef SKIP_POWER_ADJUSTMENT
246 #if __CORTEX_M == 7
247 #define BYPASS_LDO_LPSR 1
248 #define SKIP_LDO_ADJUSTMENT 1
249 #elif __CORTEX_M == 4
250 #define SKIP_DCDC_ADJUSTMENT 1
251 #define SKIP_FBB_ENABLE 1
252 #endif
253 #endif
254
255 const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
256 {
257 .postDivider = kCLOCK_PllPostDiv2, /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */
258 .loopDivider = 166, /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */
259 };
260
261 const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN =
262 {
263 .mfd = 268435455, /* Denominator of spread spectrum */
264 .ss = NULL, /* Spread spectrum parameter */
265 .ssEnable = false, /* Enable spread spectrum or not */
266 };
267
268 const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
269 {
270 .loopDivider = 41, /* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */
271 .postDivider = 0, /* Divider after PLL, should only be 1, 2, 4, 8, 16, 32 */
272 .numerator = 1, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
273 .denominator = 960000, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
274 .ss = NULL, /* Spread spectrum parameter */
275 .ssEnable = false, /* Enable spread spectrum or not */
276 };
277
278 /*******************************************************************************
279 * Code for BOARD_BootClockRUN configuration
280 ******************************************************************************/
BOARD_BootClockRUN(void)281 void BOARD_BootClockRUN(void)
282 {
283 clock_root_config_t rootCfg = {0};
284
285 #if !defined(SKIP_DCDC_CONFIGURATION) || (!SKIP_DCDC_CONFIGURATION)
286 /* Set DCDC to DCM mode to improve the efficiency for light loading in run mode and transient performance with a big loading step. */
287 DCDC_BootIntoDCM(DCDC);
288
289 #if !defined(SKIP_DCDC_ADJUSTMENT) || (!SKIP_DCDC_ADJUSTMENT)
290 if((OCOTP->FUSEN[16].FUSE == 0x57AC5969U) && ((OCOTP->FUSEN[17].FUSE & 0xFFU) == 0x0BU))
291 {
292 DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P15V);
293 }
294 else
295 {
296 /* Set 1.125V for production samples to align with data sheet requirement */
297 DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P125V);
298 }
299 #endif /* SKIP_DCDC_ADJUSTMENT */
300 #endif /* SKIP_DCDC_CONFIGURATION */
301
302 #if !defined(SKIP_FBB_ENABLE) || (!SKIP_FBB_ENABLE)
303 /* Check if FBB need to be enabled in OverDrive(OD) mode */
304 if(((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1)
305 {
306 PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, true);
307 }
308 else
309 {
310 PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, false);
311 }
312 #endif
313
314 #if defined(BYPASS_LDO_LPSR) && BYPASS_LDO_LPSR
315 PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, true);
316 PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS, true);
317 #endif
318
319 #if !defined(SKIP_LDO_ADJUSTMENT) || (!SKIP_LDO_ADJUSTMENT)
320 pmu_static_lpsr_ana_ldo_config_t lpsrAnaConfig;
321 pmu_static_lpsr_dig_config_t lpsrDigConfig;
322
323 if((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) == 0UL)
324 {
325 PMU_StaticGetLpsrAnaLdoDefaultConfig(&lpsrAnaConfig);
326 PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS, &lpsrAnaConfig);
327 }
328
329 if((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) == 0UL)
330 {
331 PMU_StaticGetLpsrDigLdoDefaultConfig(&lpsrDigConfig);
332 lpsrDigConfig.targetVoltage = kPMU_LpsrDigTargetStableVoltage1P117V;
333 PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS, &lpsrDigConfig);
334 }
335 #endif
336
337 /* Config CLK_1M */
338 CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz);
339
340 /* Init OSC RC 16M */
341 ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK;
342
343 /* Init OSC RC 400M */
344 CLOCK_OSC_EnableOscRc400M();
345 CLOCK_OSC_GateOscRc400M(true);
346
347 /* Init OSC RC 48M */
348 CLOCK_OSC_EnableOsc48M(true);
349 CLOCK_OSC_EnableOsc48MDiv2(true);
350
351 /* Config OSC 24M */
352 ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0);
353 /* Wait for 24M OSC to be stable. */
354 while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK !=
355 (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK))
356 {
357 }
358
359 /* Swicth both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */
360 #if __CORTEX_M == 7
361 rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2;
362 rootCfg.div = 1;
363 CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
364
365 rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
366 rootCfg.div = 1;
367 CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
368 #endif
369
370 #if __CORTEX_M == 4
371 rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2;
372 rootCfg.div = 1;
373 CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
374
375 rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2;
376 rootCfg.div = 1;
377 CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
378 #endif
379
380 /*
381 * if DCD is used, please make sure the clock source of SEMC is not changed in the following PLL/PFD configuration code.
382 */
383 /* Init Arm Pll. */
384 CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
385
386 /* Bypass Sys Pll1. */
387 CLOCK_SetPllBypass(kCLOCK_PllSys1, true);
388
389 /* DeInit Sys Pll1. */
390 CLOCK_DeinitSysPll1();
391
392 /* Init Sys Pll2. */
393 CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN);
394
395 /* Init System Pll2 pfd0. */
396 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27);
397
398 /* Init System Pll2 pfd1. */
399 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16);
400
401 /* Init System Pll2 pfd2. */
402 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
403
404 /* Init System Pll2 pfd3. */
405 CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32);
406
407 /* Init Sys Pll3. */
408 CLOCK_InitSysPll3();
409
410 /* Init System Pll3 pfd0. */
411 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 13);
412
413 /* Init System Pll3 pfd1. */
414 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 17);
415
416 /* Init System Pll3 pfd2. */
417 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 32);
418
419 /* Init System Pll3 pfd3. */
420 CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22);
421
422 /* Bypass Audio Pll. */
423 CLOCK_SetPllBypass(kCLOCK_PllAudio, true);
424
425 /* DeInit Audio Pll. */
426 CLOCK_DeinitAudioPll();
427
428 /* Init Video Pll. */
429 CLOCK_InitVideoPll(&videoPllConfig_BOARD_BootClockRUN);
430
431 /* Module clock root configurations. */
432 /* Configure M7 using ARM_PLL_CLK */
433 #if __CORTEX_M == 7
434 rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut;
435 rootCfg.div = 1;
436 CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
437 #endif
438
439 /* Configure M4 using SYS_PLL3_PFD3_CLK */
440 #if __CORTEX_M == 4
441 rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3;
442 rootCfg.div = 1;
443 CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
444 #endif
445
446 /* Configure BUS using SYS_PLL3_CLK */
447 rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out;
448 rootCfg.div = 2;
449 CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg);
450
451 /* Configure BUS_LPSR using SYS_PLL3_CLK */
452 rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out;
453 rootCfg.div = 3;
454 CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
455
456 /* Configure SEMC using SYS_PLL2_PFD1_CLK */
457 #ifndef SKIP_SEMC_INIT
458 rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1;
459 rootCfg.div = 3;
460 CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg);
461 #endif
462
463 #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
464 #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
465 UpdateSemcClock();
466 #endif
467 #endif
468
469 /* Configure CSSYS using OSC_RC_48M_DIV2 */
470 rootCfg.mux = kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2;
471 rootCfg.div = 1;
472 CLOCK_SetRootClock(kCLOCK_Root_Cssys, &rootCfg);
473
474 /* Configure CSTRACE using SYS_PLL2_CLK */
475 rootCfg.mux = kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out;
476 rootCfg.div = 4;
477 CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg);
478
479 /* Configure M4_SYSTICK using OSC_RC_48M_DIV2 */
480 #if __CORTEX_M == 4
481 rootCfg.mux = kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
482 rootCfg.div = 1;
483 CLOCK_SetRootClock(kCLOCK_Root_M4_Systick, &rootCfg);
484 #endif
485
486 /* Configure M7_SYSTICK using OSC_RC_48M_DIV2 */
487 #if __CORTEX_M == 7
488 rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
489 rootCfg.div = 240;
490 CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
491 #endif
492
493 /* Configure ADC1 using OSC_RC_48M_DIV2 */
494 rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2;
495 rootCfg.div = 1;
496 CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg);
497
498 /* Configure ADC2 using OSC_RC_48M_DIV2 */
499 rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2;
500 rootCfg.div = 1;
501 CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg);
502
503 /* Configure ACMP using OSC_RC_48M_DIV2 */
504 rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2;
505 rootCfg.div = 1;
506 CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg);
507
508 /* Configure FLEXIO1 using OSC_RC_48M_DIV2 */
509 rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2;
510 rootCfg.div = 1;
511 CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg);
512
513 /* Configure FLEXIO2 using OSC_RC_48M_DIV2 */
514 rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2;
515 rootCfg.div = 1;
516 CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg);
517
518 /* Configure GPT1 using OSC_RC_48M_DIV2 */
519 rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2;
520 rootCfg.div = 1;
521 CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg);
522
523 /* Configure GPT2 using OSC_RC_48M_DIV2 */
524 rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2;
525 rootCfg.div = 1;
526 CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg);
527
528 /* Configure GPT3 using OSC_RC_48M_DIV2 */
529 rootCfg.mux = kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2;
530 rootCfg.div = 1;
531 CLOCK_SetRootClock(kCLOCK_Root_Gpt3, &rootCfg);
532
533 /* Configure GPT4 using OSC_RC_48M_DIV2 */
534 rootCfg.mux = kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2;
535 rootCfg.div = 1;
536 CLOCK_SetRootClock(kCLOCK_Root_Gpt4, &rootCfg);
537
538 /* Configure GPT5 using OSC_RC_48M_DIV2 */
539 rootCfg.mux = kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2;
540 rootCfg.div = 1;
541 CLOCK_SetRootClock(kCLOCK_Root_Gpt5, &rootCfg);
542
543 /* Configure GPT6 using OSC_RC_48M_DIV2 */
544 rootCfg.mux = kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2;
545 rootCfg.div = 1;
546 CLOCK_SetRootClock(kCLOCK_Root_Gpt6, &rootCfg);
547
548 /* Configure FLEXSPI1 using OSC_RC_48M_DIV2 */
549 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) || defined(FLEXSPI_IN_USE))
550 rootCfg.mux = kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2;
551 rootCfg.div = 1;
552 CLOCK_SetRootClock(kCLOCK_Root_Flexspi1, &rootCfg);
553 #endif
554
555 /* Configure FLEXSPI2 using OSC_RC_48M_DIV2 */
556 rootCfg.mux = kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2;
557 rootCfg.div = 1;
558 CLOCK_SetRootClock(kCLOCK_Root_Flexspi2, &rootCfg);
559
560 /* Configure CAN1 using OSC_RC_48M_DIV2 */
561 rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2;
562 rootCfg.div = 1;
563 CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg);
564
565 /* Configure CAN2 using OSC_RC_48M_DIV2 */
566 rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2;
567 rootCfg.div = 1;
568 CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg);
569
570 /* Configure CAN3 using OSC_RC_48M_DIV2 */
571 rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2;
572 rootCfg.div = 1;
573 CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg);
574
575 /* Configure LPUART1 using SYS_PLL2_CLK */
576 rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out;
577 rootCfg.div = 22;
578 CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg);
579
580 /* Configure LPUART2 using SYS_PLL2_CLK */
581 rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out;
582 rootCfg.div = 22;
583 CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg);
584
585 /* Configure LPUART3 using OSC_RC_48M_DIV2 */
586 rootCfg.mux = kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2;
587 rootCfg.div = 1;
588 CLOCK_SetRootClock(kCLOCK_Root_Lpuart3, &rootCfg);
589
590 /* Configure LPUART4 using OSC_RC_48M_DIV2 */
591 rootCfg.mux = kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2;
592 rootCfg.div = 1;
593 CLOCK_SetRootClock(kCLOCK_Root_Lpuart4, &rootCfg);
594
595 /* Configure LPUART5 using OSC_RC_48M_DIV2 */
596 rootCfg.mux = kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2;
597 rootCfg.div = 1;
598 CLOCK_SetRootClock(kCLOCK_Root_Lpuart5, &rootCfg);
599
600 /* Configure LPUART6 using OSC_RC_48M_DIV2 */
601 rootCfg.mux = kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2;
602 rootCfg.div = 1;
603 CLOCK_SetRootClock(kCLOCK_Root_Lpuart6, &rootCfg);
604
605 /* Configure LPUART7 using OSC_RC_48M_DIV2 */
606 rootCfg.mux = kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2;
607 rootCfg.div = 1;
608 CLOCK_SetRootClock(kCLOCK_Root_Lpuart7, &rootCfg);
609
610 /* Configure LPUART8 using OSC_RC_48M_DIV2 */
611 rootCfg.mux = kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2;
612 rootCfg.div = 1;
613 CLOCK_SetRootClock(kCLOCK_Root_Lpuart8, &rootCfg);
614
615 /* Configure LPUART9 using OSC_RC_48M_DIV2 */
616 rootCfg.mux = kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2;
617 rootCfg.div = 1;
618 CLOCK_SetRootClock(kCLOCK_Root_Lpuart9, &rootCfg);
619
620 /* Configure LPUART10 using OSC_RC_48M_DIV2 */
621 rootCfg.mux = kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2;
622 rootCfg.div = 1;
623 CLOCK_SetRootClock(kCLOCK_Root_Lpuart10, &rootCfg);
624
625 /* Configure LPUART11 using OSC_RC_48M_DIV2 */
626 rootCfg.mux = kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2;
627 rootCfg.div = 1;
628 CLOCK_SetRootClock(kCLOCK_Root_Lpuart11, &rootCfg);
629
630 /* Configure LPUART12 using OSC_RC_48M_DIV2 */
631 rootCfg.mux = kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2;
632 rootCfg.div = 1;
633 CLOCK_SetRootClock(kCLOCK_Root_Lpuart12, &rootCfg);
634
635 /* Configure LPI2C1 using OSC_RC_48M_DIV2 */
636 rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2;
637 rootCfg.div = 1;
638 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg);
639
640 /* Configure LPI2C2 using OSC_RC_48M_DIV2 */
641 rootCfg.mux = kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2;
642 rootCfg.div = 1;
643 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c2, &rootCfg);
644
645 /* Configure LPI2C3 using OSC_RC_48M_DIV2 */
646 rootCfg.mux = kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2;
647 rootCfg.div = 1;
648 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c3, &rootCfg);
649
650 /* Configure LPI2C4 using OSC_RC_48M_DIV2 */
651 rootCfg.mux = kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2;
652 rootCfg.div = 1;
653 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c4, &rootCfg);
654
655 /* Configure LPI2C5 using OSC_RC_48M_DIV2 */
656 rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2;
657 rootCfg.div = 1;
658 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg);
659
660 /* Configure LPI2C6 using OSC_RC_48M_DIV2 */
661 rootCfg.mux = kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2;
662 rootCfg.div = 1;
663 CLOCK_SetRootClock(kCLOCK_Root_Lpi2c6, &rootCfg);
664
665 /* Configure LPSPI1 using OSC_RC_48M_DIV2 */
666 rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2;
667 rootCfg.div = 1;
668 CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg);
669
670 /* Configure LPSPI2 using OSC_RC_48M_DIV2 */
671 rootCfg.mux = kCLOCK_LPSPI2_ClockRoot_MuxOscRc48MDiv2;
672 rootCfg.div = 1;
673 CLOCK_SetRootClock(kCLOCK_Root_Lpspi2, &rootCfg);
674
675 /* Configure LPSPI3 using OSC_RC_48M_DIV2 */
676 rootCfg.mux = kCLOCK_LPSPI3_ClockRoot_MuxOscRc48MDiv2;
677 rootCfg.div = 1;
678 CLOCK_SetRootClock(kCLOCK_Root_Lpspi3, &rootCfg);
679
680 /* Configure LPSPI4 using OSC_RC_48M_DIV2 */
681 rootCfg.mux = kCLOCK_LPSPI4_ClockRoot_MuxOscRc48MDiv2;
682 rootCfg.div = 1;
683 CLOCK_SetRootClock(kCLOCK_Root_Lpspi4, &rootCfg);
684
685 /* Configure LPSPI5 using OSC_RC_48M_DIV2 */
686 rootCfg.mux = kCLOCK_LPSPI5_ClockRoot_MuxOscRc48MDiv2;
687 rootCfg.div = 1;
688 CLOCK_SetRootClock(kCLOCK_Root_Lpspi5, &rootCfg);
689
690 /* Configure LPSPI6 using OSC_RC_48M_DIV2 */
691 rootCfg.mux = kCLOCK_LPSPI6_ClockRoot_MuxOscRc48MDiv2;
692 rootCfg.div = 1;
693 CLOCK_SetRootClock(kCLOCK_Root_Lpspi6, &rootCfg);
694
695 /* Configure EMV1 using OSC_RC_48M_DIV2 */
696 rootCfg.mux = kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2;
697 rootCfg.div = 1;
698 CLOCK_SetRootClock(kCLOCK_Root_Emv1, &rootCfg);
699
700 /* Configure EMV2 using OSC_RC_48M_DIV2 */
701 rootCfg.mux = kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2;
702 rootCfg.div = 1;
703 CLOCK_SetRootClock(kCLOCK_Root_Emv2, &rootCfg);
704
705 /* Configure ENET1 using OSC_RC_48M_DIV2 */
706 rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2;
707 rootCfg.div = 1;
708 CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg);
709
710 /* Configure ENET2 using OSC_RC_48M_DIV2 */
711 rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2;
712 rootCfg.div = 1;
713 CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg);
714
715 /* Configure ENET_QOS using OSC_RC_48M_DIV2 */
716 rootCfg.mux = kCLOCK_ENET_QOS_ClockRoot_MuxOscRc48MDiv2;
717 rootCfg.div = 1;
718 CLOCK_SetRootClock(kCLOCK_Root_Enet_Qos, &rootCfg);
719
720 /* Configure ENET_25M using OSC_RC_48M_DIV2 */
721 rootCfg.mux = kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2;
722 rootCfg.div = 1;
723 CLOCK_SetRootClock(kCLOCK_Root_Enet_25m, &rootCfg);
724
725 /* Configure ENET_TIMER1 using OSC_RC_48M_DIV2 */
726 rootCfg.mux = kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2;
727 rootCfg.div = 1;
728 CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer1, &rootCfg);
729
730 /* Configure ENET_TIMER2 using OSC_RC_48M_DIV2 */
731 rootCfg.mux = kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2;
732 rootCfg.div = 1;
733 CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer2, &rootCfg);
734
735 /* Configure ENET_TIMER3 using OSC_RC_48M_DIV2 */
736 rootCfg.mux = kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc48MDiv2;
737 rootCfg.div = 1;
738 CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer3, &rootCfg);
739
740 /* Configure USDHC1 using OSC_RC_48M_DIV2 */
741 rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2;
742 rootCfg.div = 1;
743 CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg);
744
745 /* Configure USDHC2 using OSC_RC_48M_DIV2 */
746 rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2;
747 rootCfg.div = 1;
748 CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg);
749
750 /* Configure ASRC using OSC_RC_48M_DIV2 */
751 rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2;
752 rootCfg.div = 1;
753 CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg);
754
755 /* Configure MQS using OSC_RC_48M_DIV2 */
756 rootCfg.mux = kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2;
757 rootCfg.div = 1;
758 CLOCK_SetRootClock(kCLOCK_Root_Mqs, &rootCfg);
759
760 /* Configure MIC using OSC_RC_48M_DIV2 */
761 rootCfg.mux = kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2;
762 rootCfg.div = 1;
763 CLOCK_SetRootClock(kCLOCK_Root_Mic, &rootCfg);
764
765 /* Configure SPDIF using OSC_RC_48M_DIV2 */
766 rootCfg.mux = kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2;
767 rootCfg.div = 1;
768 CLOCK_SetRootClock(kCLOCK_Root_Spdif, &rootCfg);
769
770 /* Configure SAI1 using OSC_RC_48M_DIV2 */
771 rootCfg.mux = kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2;
772 rootCfg.div = 1;
773 CLOCK_SetRootClock(kCLOCK_Root_Sai1, &rootCfg);
774
775 /* Configure SAI2 using OSC_RC_48M_DIV2 */
776 rootCfg.mux = kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2;
777 rootCfg.div = 1;
778 CLOCK_SetRootClock(kCLOCK_Root_Sai2, &rootCfg);
779
780 /* Configure SAI3 using OSC_RC_48M_DIV2 */
781 rootCfg.mux = kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2;
782 rootCfg.div = 1;
783 CLOCK_SetRootClock(kCLOCK_Root_Sai3, &rootCfg);
784
785 /* Configure SAI4 using OSC_RC_48M_DIV2 */
786 rootCfg.mux = kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2;
787 rootCfg.div = 1;
788 CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg);
789
790 /* Configure GC355 using PLL_VIDEO_CLK */
791 rootCfg.mux = kCLOCK_GC355_ClockRoot_MuxVideoPllOut;
792 rootCfg.div = 2;
793 CLOCK_SetRootClock(kCLOCK_Root_Gc355, &rootCfg);
794
795 /* Configure LCDIF using OSC_RC_48M_DIV2 */
796 rootCfg.mux = kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2;
797 rootCfg.div = 1;
798 CLOCK_SetRootClock(kCLOCK_Root_Lcdif, &rootCfg);
799
800 /* Configure LCDIFV2 using OSC_RC_48M_DIV2 */
801 rootCfg.mux = kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2;
802 rootCfg.div = 1;
803 CLOCK_SetRootClock(kCLOCK_Root_Lcdifv2, &rootCfg);
804
805 /* Configure MIPI_REF using OSC_RC_48M_DIV2 */
806 rootCfg.mux = kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2;
807 rootCfg.div = 1;
808 CLOCK_SetRootClock(kCLOCK_Root_Mipi_Ref, &rootCfg);
809
810 /* Configure MIPI_ESC using OSC_RC_48M_DIV2 */
811 rootCfg.mux = kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2;
812 rootCfg.div = 1;
813 CLOCK_SetRootClock(kCLOCK_Root_Mipi_Esc, &rootCfg);
814
815 /* Configure CSI2 using OSC_RC_48M_DIV2 */
816 rootCfg.mux = kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2;
817 rootCfg.div = 1;
818 CLOCK_SetRootClock(kCLOCK_Root_Csi2, &rootCfg);
819
820 /* Configure CSI2_ESC using OSC_RC_48M_DIV2 */
821 rootCfg.mux = kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2;
822 rootCfg.div = 1;
823 CLOCK_SetRootClock(kCLOCK_Root_Csi2_Esc, &rootCfg);
824
825 /* Configure CSI2_UI using OSC_RC_48M_DIV2 */
826 rootCfg.mux = kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2;
827 rootCfg.div = 1;
828 CLOCK_SetRootClock(kCLOCK_Root_Csi2_Ui, &rootCfg);
829
830 /* Configure CSI using OSC_RC_48M_DIV2 */
831 rootCfg.mux = kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2;
832 rootCfg.div = 1;
833 CLOCK_SetRootClock(kCLOCK_Root_Csi, &rootCfg);
834
835 /* Configure CKO1 using OSC_RC_48M_DIV2 */
836 rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2;
837 rootCfg.div = 1;
838 CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg);
839
840 /* Configure CKO2 using OSC_RC_48M_DIV2 */
841 rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2;
842 rootCfg.div = 1;
843 CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg);
844
845 /* Set SAI1 MCLK1 clock source. */
846 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
847 /* Set SAI1 MCLK2 clock source. */
848 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 3);
849 /* Set SAI1 MCLK3 clock source. */
850 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
851 /* Set SAI2 MCLK3 clock source. */
852 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
853 /* Set SAI3 MCLK3 clock source. */
854 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
855
856 /* Set MQS configuration. */
857 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
858 /* Set ENET Ref clock source. */
859 IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK;
860 /* Set ENET_1G Tx clock source. */
861 IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK);
862 /* Set ENET_1G Ref clock source. */
863 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK;
864 /* Set ENET_QOS Tx clock source. */
865 IOMUXC_GPR->GPR6 &= ~IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_MASK;
866 /* Set ENET_QOS Ref clock source. */
867 IOMUXC_GPR->GPR6 &= ~IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_MASK;
868 /* Set GPT1 High frequency reference clock source. */
869 IOMUXC_GPR->GPR22 &= ~IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK;
870 /* Set GPT2 High frequency reference clock source. */
871 IOMUXC_GPR->GPR23 &= ~IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK;
872 /* Set GPT3 High frequency reference clock source. */
873 IOMUXC_GPR->GPR24 &= ~IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK;
874 /* Set GPT4 High frequency reference clock source. */
875 IOMUXC_GPR->GPR25 &= ~IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK;
876 /* Set GPT5 High frequency reference clock source. */
877 IOMUXC_GPR->GPR26 &= ~IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK;
878 /* Set GPT6 High frequency reference clock source. */
879 IOMUXC_GPR->GPR27 &= ~IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK;
880
881 #if __CORTEX_M == 7
882 SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7);
883 #else
884 SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M4);
885 #endif
886 }
