1 /*
2 * Copyright 2020-2022 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "sdmmc_config.h"
9 #include "fsl_iomuxc.h"
10 /*******************************************************************************
11 * Definitions
12 ******************************************************************************/
13
14 /*******************************************************************************
15 * Prototypes
16 ******************************************************************************/
17 void BOARD_SDCardPowerControl(bool enable);
18
19 /*******************************************************************************
20 * Variables
21 ******************************************************************************/
22 /*!brief sdmmc dma buffer */
23 AT_NONCACHEABLE_SECTION_ALIGN(static uint32_t s_sdmmcHostDmaBuffer[BOARD_SDMMC_HOST_DMA_DESCRIPTOR_BUFFER_SIZE],
24 SDMMCHOST_DMA_DESCRIPTOR_BUFFER_ALIGN_SIZE);
25 #if defined SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER && SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER
26 /* two cache line length for sdmmc host driver maintain unalign transfer */
27 SDK_ALIGN(static uint8_t s_sdmmcCacheLineAlignBuffer[BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE * 2U],
28 BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE);
29 #endif
30 #if defined(SDIO_ENABLED) || defined(SD_ENABLED)
31 static sd_detect_card_t s_cd;
32 static sd_io_voltage_t s_ioVoltage = {
33 .type = BOARD_SDMMC_SD_IO_VOLTAGE_CONTROL_TYPE,
34 .func = NULL,
35 };
36 #endif
37 static sdmmchost_t s_host;
38 #ifdef SDIO_ENABLED
39 static sdio_card_int_t s_sdioInt;
40 #endif
41
42 GPIO_HANDLE_DEFINE(s_CardDetectGpioHandle);
43 GPIO_HANDLE_DEFINE(s_PowerResetGpioHandle);
44 /*******************************************************************************
45 * Code
46 ******************************************************************************/
BOARD_USDHC1ClockConfiguration(void)47 uint32_t BOARD_USDHC1ClockConfiguration(void)
48 {
49 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
50 /*configure system pll PFD0 fractional divider to 24, output clock is 528MHZ * 18 / 24 = 396 MHZ*/
51 CLOCK_InitSysPfd(kCLOCK_Pfd0, 24U);
52 /* Configure USDHC clock source and divider */
53 CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1U); /* USDHC clock root frequency maximum: 198MHZ */
54 CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1U);
55
56 return 396000000U / 2U;
57 }
58
59 #if defined(SDIO_ENABLED) || defined(SD_ENABLED)
BOARD_SDCardGetDetectStatus(void)60 bool BOARD_SDCardGetDetectStatus(void)
61 {
62 uint8_t pinState;
63
64 if (HAL_GpioGetInput(s_CardDetectGpioHandle, &pinState) == kStatus_HAL_GpioSuccess)
65 {
66 if (pinState == BOARD_SDMMC_SD_CD_INSERT_LEVEL)
67 {
68 return true;
69 }
70 }
71 return false;
72 }
SDMMC_SD_CD_Callback(void * param)73 void SDMMC_SD_CD_Callback(void *param)
74 {
75 if (s_cd.callback != NULL)
76 {
77 s_cd.callback(BOARD_SDCardGetDetectStatus(), s_cd.userData);
78 }
79 }
80
BOARD_SDCardDAT3PullFunction(uint32_t status)81 void BOARD_SDCardDAT3PullFunction(uint32_t status)
82 {
83 if (status == kSD_DAT3PullDown)
84 {
85 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3,
86 IOMUXC_SW_PAD_CTL_PAD_SPEED(1) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
87 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
88 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
89 IOMUXC_SW_PAD_CTL_PAD_DSE(1));
90 }
91 else
92 {
93 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3,
94 IOMUXC_SW_PAD_CTL_PAD_SPEED(1) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
95 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
96 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
97 IOMUXC_SW_PAD_CTL_PAD_DSE(1));
98 }
99 }
100
BOARD_SDCardDetectInit(sd_cd_t cd,void * userData)101 void BOARD_SDCardDetectInit(sd_cd_t cd, void *userData)
102 {
103 uint8_t pinState;
104
105 /* install card detect callback */
106 s_cd.cdDebounce_ms = BOARD_SDMMC_SD_CARD_DETECT_DEBOUNCE_DELAY_MS;
107 s_cd.type = BOARD_SDMMC_SD_CD_TYPE;
108 s_cd.cardDetected = BOARD_SDCardGetDetectStatus;
109 s_cd.callback = cd;
110 s_cd.userData = userData;
111
112 if (BOARD_SDMMC_SD_CD_TYPE == kSD_DetectCardByGpioCD)
113 {
114 hal_gpio_pin_config_t sw_config = {
115 kHAL_GpioDirectionIn,
116 0,
117 BOARD_SDMMC_SD_CD_GPIO_PORT,
118 BOARD_SDMMC_SD_CD_GPIO_PIN,
119 };
120 HAL_GpioInit(s_CardDetectGpioHandle, &sw_config);
121 HAL_GpioSetTriggerMode(s_CardDetectGpioHandle, BOARD_SDMMC_SD_CD_INTTERUPT_TYPE);
122 HAL_GpioInstallCallback(s_CardDetectGpioHandle, SDMMC_SD_CD_Callback, NULL);
123
124 if (HAL_GpioGetInput(s_CardDetectGpioHandle, &pinState) == kStatus_HAL_GpioSuccess)
125 {
126 if (pinState == BOARD_SDMMC_SD_CD_INSERT_LEVEL)
127 {
128 if (cd != NULL)
129 {
130 cd(true, userData);
131 }
132 }
133 }
134 }
135
136 /* register DAT3 pull function switch function pointer */
137 if (BOARD_SDMMC_SD_CD_TYPE == kSD_DetectCardByHostDATA3)
138 {
139 s_cd.dat3PullFunc = BOARD_SDCardDAT3PullFunction;
140 /* make sure the card is power on for DAT3 pull up */
141 BOARD_SDCardPowerControl(true);
142 }
143 }
144
BOARD_SDCardPowerResetInit(void)145 void BOARD_SDCardPowerResetInit(void)
146 {
147 hal_gpio_pin_config_t sw_config = {
148 kHAL_GpioDirectionOut,
149 1,
150 BOARD_SDMMC_SD_POWER_RESET_GPIO_PORT,
151 BOARD_SDMMC_SD_POWER_RESET_GPIO_PIN,
152 };
153 HAL_GpioInit(s_PowerResetGpioHandle, &sw_config);
154 }
155
BOARD_SDCardPowerControl(bool enable)156 void BOARD_SDCardPowerControl(bool enable)
157 {
158 if (enable)
159 {
160 HAL_GpioSetOutput(s_PowerResetGpioHandle, 1);
161 }
162 else
163 {
164 /* Power off the card only when the card is inserted, since the card detect circuit is depend on the power on
165 * the EVK, card detect will not work if the power is off */
166 if (BOARD_SDCardGetDetectStatus() == true)
167 {
168 HAL_GpioSetOutput(s_PowerResetGpioHandle, 0);
169 }
170 }
171 }
172
BOARD_SD_Pin_Config(uint32_t freq)173 void BOARD_SD_Pin_Config(uint32_t freq)
174 {
175 uint32_t speed = 0U, strength = 0U;
176
177 if (freq <= 50000000)
178 {
179 speed = 0U;
180 strength = 7U;
181 }
182 else if (freq <= 100000000)
183 {
184 speed = 2U;
185 strength = 7U;
186 }
187 else
188 {
189 speed = 3U;
190 strength = 7U;
191 }
192
193 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD,
194 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
195 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
196 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
197 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
198 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK,
199 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
200 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
201 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
202 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0,
203 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
204 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
205 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
206 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
207 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1,
208 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
209 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
210 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
211 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
212 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2,
213 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
214 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
215 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
216 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
217 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3,
218 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
219 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
220 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
221 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
222 }
223 #endif
224
225 #ifdef SD_ENABLED
BOARD_SD_Config(void * card,sd_cd_t cd,uint32_t hostIRQPriority,void * userData)226 void BOARD_SD_Config(void *card, sd_cd_t cd, uint32_t hostIRQPriority, void *userData)
227 {
228 assert(card);
229
230 s_host.dmaDesBuffer = s_sdmmcHostDmaBuffer;
231 s_host.dmaDesBufferWordsNum = BOARD_SDMMC_HOST_DMA_DESCRIPTOR_BUFFER_SIZE;
232 s_host.enableCacheControl = BOARD_SDMMC_HOST_CACHE_CONTROL;
233 #if defined SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER && SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER
234 s_host.cacheAlignBuffer = s_sdmmcCacheLineAlignBuffer;
235 s_host.cacheAlignBufferSize = BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE * 2U;
236 #endif
237
238 ((sd_card_t *)card)->host = &s_host;
239 ((sd_card_t *)card)->host->hostController.base = BOARD_SDMMC_SD_HOST_BASEADDR;
240 ((sd_card_t *)card)->host->hostController.sourceClock_Hz = BOARD_USDHC1ClockConfiguration();
241
242 ((sd_card_t *)card)->usrParam.cd = &s_cd;
243 ((sd_card_t *)card)->usrParam.pwr = BOARD_SDCardPowerControl;
244 ((sd_card_t *)card)->usrParam.ioStrength = BOARD_SD_Pin_Config;
245 ((sd_card_t *)card)->usrParam.ioVoltage = &s_ioVoltage;
246 ((sd_card_t *)card)->usrParam.maxFreq = BOARD_SDMMC_SD_HOST_SUPPORT_SDR104_FREQ;
247
248 BOARD_SDCardPowerResetInit();
249 BOARD_SDCardDetectInit(cd, userData);
250
251 NVIC_SetPriority(BOARD_SDMMC_SD_HOST_IRQ, hostIRQPriority);
252 }
253 #endif
254
255 #ifdef SDIO_ENABLED
BOARD_SDIO_Config(void * card,sd_cd_t cd,uint32_t hostIRQPriority,sdio_int_t cardInt)256 void BOARD_SDIO_Config(void *card, sd_cd_t cd, uint32_t hostIRQPriority, sdio_int_t cardInt)
257 {
258 assert(card);
259
260 s_host.dmaDesBuffer = s_sdmmcHostDmaBuffer;
261 s_host.dmaDesBufferWordsNum = BOARD_SDMMC_HOST_DMA_DESCRIPTOR_BUFFER_SIZE;
262 s_host.enableCacheControl = BOARD_SDMMC_HOST_CACHE_CONTROL;
263 #if defined SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER && SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER
264 s_host.cacheAlignBuffer = s_sdmmcCacheLineAlignBuffer;
265 s_host.cacheAlignBufferSize = BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE * 2U;
266 #endif
267
268 ((sdio_card_t *)card)->host = &s_host;
269 ((sdio_card_t *)card)->host->hostController.base = BOARD_SDMMC_SDIO_HOST_BASEADDR;
270 ((sdio_card_t *)card)->host->hostController.sourceClock_Hz = BOARD_USDHC1ClockConfiguration();
271
272 ((sdio_card_t *)card)->usrParam.cd = &s_cd;
273 ((sdio_card_t *)card)->usrParam.pwr = BOARD_SDCardPowerControl;
274 ((sdio_card_t *)card)->usrParam.ioStrength = BOARD_SD_Pin_Config;
275 ((sdio_card_t *)card)->usrParam.ioVoltage = &s_ioVoltage;
276 ((sdio_card_t *)card)->usrParam.maxFreq = BOARD_SDMMC_SD_HOST_SUPPORT_SDR104_FREQ;
277 if (cardInt != NULL)
278 {
279 s_sdioInt.cardInterrupt = cardInt;
280 ((sdio_card_t *)card)->usrParam.sdioInt = &s_sdioInt;
281 }
282
283 BOARD_SDCardPowerResetInit();
284 BOARD_SDCardDetectInit(cd, NULL);
285
286 NVIC_SetPriority(BOARD_SDMMC_SDIO_HOST_IRQ, hostIRQPriority);
287 }
288 #endif
289
290 #ifdef MMC_ENABLED
BOARD_MMC_Pin_Config(uint32_t freq)291 static void BOARD_MMC_Pin_Config(uint32_t freq)
292 {
293 uint32_t speed = 0U, strength = 0U;
294
295 if (freq <= 50000000)
296 {
297 speed = 0U;
298 strength = 7U;
299 }
300 else if (freq <= 100000000)
301 {
302 speed = 2U;
303 strength = 7U;
304 }
305 else
306 {
307 speed = 3U;
308 strength = 7U;
309 }
310
311 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_05_USDHC2_CMD,
312 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
313 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
314 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
315 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
316 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_04_USDHC2_CLK,
317 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
318 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
319 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
320 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0,
321 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
322 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
323 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
324 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
325 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1,
326 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
327 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
328 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
329 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
330 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2,
331 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
332 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
333 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
334 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
335 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3,
336 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
337 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
338 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
339 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
340 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4,
341 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
342 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
343 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
344 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
345 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5,
346 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
347 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
348 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
349 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
350 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6,
351 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
352 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
353 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
354 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
355 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7,
356 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
357 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
358 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
359 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
360 }
361
BOARD_MMC_Config(void * card,uint32_t hostIRQPriority)362 void BOARD_MMC_Config(void *card, uint32_t hostIRQPriority)
363 {
364 assert(card);
365
366 s_host.dmaDesBuffer = s_sdmmcHostDmaBuffer;
367 s_host.dmaDesBufferWordsNum = BOARD_SDMMC_HOST_DMA_DESCRIPTOR_BUFFER_SIZE;
368 s_host.enableCacheControl = BOARD_SDMMC_HOST_CACHE_CONTROL;
369 #if defined SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER && SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER
370 s_host.cacheAlignBuffer = s_sdmmcCacheLineAlignBuffer;
371 s_host.cacheAlignBufferSize = BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE * 2U;
372 #endif
373
374 ((mmc_card_t *)card)->host = &s_host;
375 ((mmc_card_t *)card)->host->hostController.base = BOARD_SDMMC_MMC_HOST_BASEADDR;
376 ((mmc_card_t *)card)->host->hostController.sourceClock_Hz = BOARD_USDHC1ClockConfiguration();
377 ((mmc_card_t *)card)->usrParam.ioStrength = BOARD_MMC_Pin_Config;
378 ((mmc_card_t *)card)->usrParam.maxFreq = BOARD_SDMMC_MMC_HOST_SUPPORT_HS200_FREQ;
379
380 ((mmc_card_t *)card)->hostVoltageWindowVCC = BOARD_SDMMC_MMC_VCC_SUPPLY;
381 ((mmc_card_t *)card)->hostVoltageWindowVCCQ = BOARD_SDMMC_MMC_VCCQ_SUPPLY;
382
383 NVIC_SetPriority(BOARD_SDMMC_MMC_HOST_IRQ, hostIRQPriority);
384 }
385 #endif
386
