1 /*
2 * Copyright (c) 2013-2020 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 #include "Driver_NAND.h"
20
21 #define ARM_NAND_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */
22
23 /* Driver Version */
24 static const ARM_DRIVER_VERSION DriverVersion = {
25 ARM_NAND_API_VERSION,
26 ARM_NAND_DRV_VERSION
27 };
28
29 /* Driver Capabilities */
30 static const ARM_NAND_CAPABILITIES DriverCapabilities = {
31 0, /* Signal Device Ready event (R/Bn rising edge) */
32 0, /* Supports re-entrant operation (SendCommand/Address, Read/WriteData) */
33 0, /* Supports Sequence operation (ExecuteSequence, AbortSequence) */
34 0, /* Supports VCC Power Supply Control */
35 0, /* Supports 1.8 VCC Power Supply */
36 0, /* Supports VCCQ I/O Power Supply Control */
37 0, /* Supports 1.8 VCCQ I/O Power Supply */
38 0, /* Supports VPP High Voltage Power Supply Control */
39 0, /* Supports WPn (Write Protect) Control */
40 0, /* Number of CEn (Chip Enable) lines: ce_lines + 1 */
41 0, /* Supports manual CEn (Chip Enable) Control */
42 0, /* Supports R/Bn (Ready/Busy) Monitoring */
43 0, /* Supports 16-bit data */
44 0, /* Supports NV-DDR Data Interface (ONFI) */
45 0, /* Supports NV-DDR2 Data Interface (ONFI) */
46 0, /* Fastest (highest) SDR Timing Mode supported (ONFI) */
47 0, /* Fastest (highest) NV_DDR Timing Mode supported (ONFI) */
48 0, /* Fastest (highest) NV_DDR2 Timing Mode supported (ONFI) */
49 0, /* Supports Driver Strength 2.0x = 18 Ohms */
50 0, /* Supports Driver Strength 1.4x = 25 Ohms */
51 0, /* Supports Driver Strength 0.7x = 50 Ohms */
52 #if (ARM_NAND_API_VERSION > 0x201U)
53 0 /* Reserved (must be zero) */
54 #endif
55 };
56
57 /* Exported functions */
58
ARM_NAND_GetVersion(void)59 static ARM_DRIVER_VERSION ARM_NAND_GetVersion (void) {
60 return DriverVersion;
61 }
62
ARM_NAND_GetCapabilities(void)63 static ARM_NAND_CAPABILITIES ARM_NAND_GetCapabilities (void) {
64 return DriverCapabilities;
65 }
66
ARM_NAND_Initialize(ARM_NAND_SignalEvent_t cb_event)67 static int32_t ARM_NAND_Initialize (ARM_NAND_SignalEvent_t cb_event) {
68 return ARM_DRIVER_ERROR_UNSUPPORTED;
69 }
70
ARM_NAND_Uninitialize(void)71 static int32_t ARM_NAND_Uninitialize (void) {
72 return ARM_DRIVER_ERROR_UNSUPPORTED;
73 }
74
ARM_NAND_PowerControl(ARM_POWER_STATE state)75 static int32_t ARM_NAND_PowerControl (ARM_POWER_STATE state) {
76
77 switch ((int32_t)state) {
78 case ARM_POWER_OFF:
79 return ARM_DRIVER_ERROR_UNSUPPORTED;
80
81 case ARM_POWER_LOW:
82 return ARM_DRIVER_ERROR_UNSUPPORTED;
83
84 case ARM_POWER_FULL:
85 return ARM_DRIVER_ERROR_UNSUPPORTED;
86
87 default:
88 return ARM_DRIVER_ERROR_UNSUPPORTED;
89 }
90 return ARM_DRIVER_OK;
91 }
92
ARM_NAND_DevicePower(uint32_t voltage)93 static int32_t ARM_NAND_DevicePower (uint32_t voltage) {
94 return ARM_DRIVER_ERROR_UNSUPPORTED;
95 }
96
ARM_NAND_WriteProtect(uint32_t dev_num,bool enable)97 static int32_t ARM_NAND_WriteProtect (uint32_t dev_num, bool enable) {
98 return ARM_DRIVER_ERROR_UNSUPPORTED;
99 }
100
ARM_NAND_ChipEnable(uint32_t dev_num,bool enable)101 static int32_t ARM_NAND_ChipEnable (uint32_t dev_num, bool enable) {
102 return ARM_DRIVER_ERROR_UNSUPPORTED;
103 }
104
ARM_NAND_GetDeviceBusy(uint32_t dev_num)105 static int32_t ARM_NAND_GetDeviceBusy (uint32_t dev_num) {
106 return ARM_DRIVER_ERROR_UNSUPPORTED;
107 }
108
ARM_NAND_SendCommand(uint32_t dev_num,uint8_t cmd)109 static int32_t ARM_NAND_SendCommand (uint32_t dev_num, uint8_t cmd) {
110 return ARM_DRIVER_ERROR_UNSUPPORTED;
111 }
112
ARM_NAND_SendAddress(uint32_t dev_num,uint8_t addr)113 static int32_t ARM_NAND_SendAddress (uint32_t dev_num, uint8_t addr) {
114 return ARM_DRIVER_ERROR_UNSUPPORTED;
115 }
116
ARM_NAND_ReadData(uint32_t dev_num,void * data,uint32_t cnt,uint32_t mode)117 static int32_t ARM_NAND_ReadData (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode) {
118 return ARM_DRIVER_ERROR_UNSUPPORTED;
119 }
120
ARM_NAND_WriteData(uint32_t dev_num,const void * data,uint32_t cnt,uint32_t mode)121 static int32_t ARM_NAND_WriteData (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode) {
122 return ARM_DRIVER_ERROR_UNSUPPORTED;
123 }
124
ARM_NAND_ExecuteSequence(uint32_t dev_num,uint32_t code,uint32_t cmd,uint32_t addr_col,uint32_t addr_row,void * data,uint32_t data_cnt,uint8_t * status,uint32_t * count)125 static int32_t ARM_NAND_ExecuteSequence (uint32_t dev_num, uint32_t code, uint32_t cmd,
126 uint32_t addr_col, uint32_t addr_row,
127 void *data, uint32_t data_cnt,
128 uint8_t *status, uint32_t *count) {
129 return ARM_DRIVER_ERROR_UNSUPPORTED;
130 }
131
ARM_NAND_AbortSequence(uint32_t dev_num)132 static int32_t ARM_NAND_AbortSequence (uint32_t dev_num) {
133 return ARM_DRIVER_ERROR_UNSUPPORTED;
134 }
135
ARM_NAND_Control(uint32_t dev_num,uint32_t control,uint32_t arg)136 static int32_t ARM_NAND_Control (uint32_t dev_num, uint32_t control, uint32_t arg) {
137
138 switch (control) {
139 case ARM_NAND_BUS_MODE:
140 return ARM_DRIVER_ERROR_UNSUPPORTED;
141
142 case ARM_NAND_BUS_DATA_WIDTH:
143 return ARM_DRIVER_ERROR_UNSUPPORTED;
144
145 case ARM_NAND_DEVICE_READY_EVENT:
146 return ARM_DRIVER_ERROR_UNSUPPORTED;
147
148 default:
149 return ARM_DRIVER_ERROR_UNSUPPORTED;
150 }
151
152 return ARM_DRIVER_ERROR;
153 }
154
ARM_NAND_GetStatus(uint32_t dev_num)155 static ARM_NAND_STATUS ARM_NAND_GetStatus (uint32_t dev_num) {
156 ARM_NAND_STATUS stat;
157
158 stat.busy = 0U;
159 stat.ecc_error = 0U;
160
161 return stat;
162 }
163
ARM_NAND_InquireECC(int32_t index,ARM_NAND_ECC_INFO * info)164 static int32_t ARM_NAND_InquireECC (int32_t index, ARM_NAND_ECC_INFO *info) {
165 return ARM_DRIVER_ERROR_UNSUPPORTED;
166 }
167
168 /* NAND Driver Control Block */
169 extern \
170 ARM_DRIVER_NAND Driver_NAND0;
171 ARM_DRIVER_NAND Driver_NAND0 = {
172 ARM_NAND_GetVersion,
173 ARM_NAND_GetCapabilities,
174 ARM_NAND_Initialize,
175 ARM_NAND_Uninitialize,
176 ARM_NAND_PowerControl,
177 ARM_NAND_DevicePower,
178 ARM_NAND_WriteProtect,
179 ARM_NAND_ChipEnable,
180 ARM_NAND_GetDeviceBusy,
181 ARM_NAND_SendCommand,
182 ARM_NAND_SendAddress,
183 ARM_NAND_ReadData,
184 ARM_NAND_WriteData,
185 ARM_NAND_ExecuteSequence,
186 ARM_NAND_AbortSequence,
187 ARM_NAND_Control,
188 ARM_NAND_GetStatus,
189 ARM_NAND_InquireECC
190 };
191
