1 /* 2 * NOTE: File generated by lpc_cfg_utils.py 3 * from LPC51U68JBD48/signal_configuration.xml 4 * 5 * 6 */ 7 8 #ifndef _ZEPHYR_DTS_BINDING_LPC51U68JBD48_ 9 #define _ZEPHYR_DTS_BINDING_LPC51U68JBD48_ 10 11 #define IOCON_MUX(offset, type, mux) \ 12 (((offset & 0xFFF) << 20) | \ 13 (((type) & 0x3) << 18) | \ 14 (((mux) & 0xF) << 0)) 15 16 #define IOCON_TYPE_D 0x0 17 #define IOCON_TYPE_I 0x1 18 #define IOCON_TYPE_A 0x2 19 20 #define ADC0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 21 #define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 22 #define CTIMER0_CAPTURE0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 3) /* PIO0_0 */ 23 #define DMA0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 24 #define DMA0_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 25 #define DMA0_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 26 #define DMA0_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 27 #define DMA0_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 28 #define DMA0_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 29 #define DMA0_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 30 #define DMA0_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 31 #define DMA0_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 32 #define DMA0_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 33 #define DMA0_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 34 #define DMA0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 35 #define DMA0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 36 #define DMA0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 37 #define DMA0_TRIG4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 38 #define DMA0_TRIG5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 39 #define DMA0_TRIG6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 40 #define DMA0_TRIG7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 41 #define DMA0_TRIG8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 42 #define DMA0_TRIG9_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 43 #define FC0_RXD_SDA_MOSI_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 1) /* PIO0_0 */ 44 #define FC3_CTS_SDA_SSEL0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 2) /* PIO0_0 */ 45 #define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 46 #define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 47 #define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 48 #define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 49 #define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 0) /* PIO0_0 */ 50 #define SCT0_OUT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_D, 5) /* PIO0_0 */ 51 #define ADC0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 52 #define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 53 #define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 54 #define DMA0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 55 #define DMA0_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 56 #define DMA0_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 57 #define DMA0_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 58 #define DMA0_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 59 #define DMA0_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 60 #define DMA0_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 61 #define DMA0_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 62 #define DMA0_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 63 #define DMA0_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 64 #define DMA0_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 65 #define DMA0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 66 #define DMA0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 67 #define DMA0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 68 #define DMA0_TRIG4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 69 #define DMA0_TRIG5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 70 #define DMA0_TRIG6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 71 #define DMA0_TRIG7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 72 #define DMA0_TRIG8_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 73 #define DMA0_TRIG9_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 74 #define FC0_TXD_SCL_MISO_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 1) /* PIO0_1 */ 75 #define FC3_RTS_SCL_SSEL1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ 76 #define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 77 #define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 78 #define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 79 #define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 80 #define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 81 #define SCT0_OUT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ 82 #define ADC0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 83 #define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 84 #define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 85 #define DMA0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 86 #define DMA0_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 87 #define DMA0_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 88 #define DMA0_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 89 #define DMA0_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 90 #define DMA0_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 91 #define DMA0_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 92 #define DMA0_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 93 #define DMA0_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 94 #define DMA0_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 95 #define DMA0_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 96 #define DMA0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 97 #define DMA0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 98 #define DMA0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 99 #define DMA0_TRIG4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 100 #define DMA0_TRIG5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 101 #define DMA0_TRIG6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 102 #define DMA0_TRIG7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 103 #define DMA0_TRIG8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 104 #define DMA0_TRIG9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 105 #define FC0_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ 106 #define FC3_SSEL2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ 107 #define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 108 #define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 109 #define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 110 #define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 111 #define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 112 #define ADC0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 113 #define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 114 #define CTIMER0_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ 115 #define DMA0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 116 #define DMA0_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 117 #define DMA0_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 118 #define DMA0_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 119 #define DMA0_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 120 #define DMA0_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 121 #define DMA0_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 122 #define DMA0_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 123 #define DMA0_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 124 #define DMA0_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 125 #define DMA0_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 126 #define DMA0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 127 #define DMA0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 128 #define DMA0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 129 #define DMA0_TRIG4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 130 #define DMA0_TRIG5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 131 #define DMA0_TRIG6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 132 #define DMA0_TRIG7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 133 #define DMA0_TRIG8_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 134 #define DMA0_TRIG9_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 135 #define FC6_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ 136 #define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 137 #define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 138 #define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 139 #define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 140 #define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 141 #define SCT0_OUT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ 142 #define ADC0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 143 #define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 144 #define CTIMER0_MATCH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ 145 #define DMA0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 146 #define DMA0_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 147 #define DMA0_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 148 #define DMA0_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 149 #define DMA0_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 150 #define DMA0_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 151 #define DMA0_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 152 #define DMA0_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 153 #define DMA0_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 154 #define DMA0_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 155 #define DMA0_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 156 #define DMA0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 157 #define DMA0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 158 #define DMA0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 159 #define DMA0_TRIG4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 160 #define DMA0_TRIG5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 161 #define DMA0_TRIG6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 162 #define DMA0_TRIG7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 163 #define DMA0_TRIG8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 164 #define DMA0_TRIG9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 165 #define FC6_TXD_SCL_MISO_WS_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ 166 #define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 167 #define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 168 #define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 169 #define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 170 #define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 171 #define UTICK0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 5) /* PIO0_6 */ 172 #define ADC0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 173 #define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 174 #define CTIMER0_CAPTURE2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 5) /* PIO0_7 */ 175 #define CTIMER0_MATCH2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ 176 #define DMA0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 177 #define DMA0_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 178 #define DMA0_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 179 #define DMA0_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 180 #define DMA0_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 181 #define DMA0_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 182 #define DMA0_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 183 #define DMA0_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 184 #define DMA0_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 185 #define DMA0_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 186 #define DMA0_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 187 #define DMA0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 188 #define DMA0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 189 #define DMA0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 190 #define DMA0_TRIG4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 191 #define DMA0_TRIG5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 192 #define DMA0_TRIG6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 193 #define DMA0_TRIG7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 194 #define DMA0_TRIG8_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 195 #define DMA0_TRIG9_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 196 #define FC6_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ 197 #define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 198 #define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 199 #define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 200 #define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 201 #define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 202 #define SCT0_OUT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ 203 #define ADC0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 204 #define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 205 #define CTIMER0_MATCH3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ 206 #define DMA0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 207 #define DMA0_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 208 #define DMA0_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 209 #define DMA0_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 210 #define DMA0_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 211 #define DMA0_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 212 #define DMA0_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 213 #define DMA0_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 214 #define DMA0_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 215 #define DMA0_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 216 #define DMA0_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 217 #define DMA0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 218 #define DMA0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 219 #define DMA0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 220 #define DMA0_TRIG4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 221 #define DMA0_TRIG5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 222 #define DMA0_TRIG6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 223 #define DMA0_TRIG7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 224 #define DMA0_TRIG8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 225 #define DMA0_TRIG9_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 226 #define FC2_RXD_SDA_MOSI_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ 227 #define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 228 #define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 229 #define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 230 #define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 231 #define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 232 #define SCT0_OUT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ 233 #define ADC0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 234 #define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 235 #define CTIMER3_CAPTURE0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 3) /* PIO0_9 */ 236 #define DMA0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 237 #define DMA0_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 238 #define DMA0_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 239 #define DMA0_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 240 #define DMA0_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 241 #define DMA0_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 242 #define DMA0_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 243 #define DMA0_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 244 #define DMA0_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 245 #define DMA0_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 246 #define DMA0_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 247 #define DMA0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 248 #define DMA0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 249 #define DMA0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 250 #define DMA0_TRIG4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 251 #define DMA0_TRIG5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 252 #define DMA0_TRIG6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 253 #define DMA0_TRIG7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 254 #define DMA0_TRIG8_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 255 #define DMA0_TRIG9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 256 #define FC2_TXD_SCL_MISO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 1) /* PIO0_9 */ 257 #define FC3_CTS_SDA_SSEL0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 5) /* PIO0_9 */ 258 #define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 259 #define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 260 #define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 261 #define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 262 #define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 0) /* PIO0_9 */ 263 #define SCT0_OUT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_D, 2) /* PIO0_9 */ 264 #define ADC0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 265 #define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 266 #define CTIMER3_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ 267 #define DMA0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 268 #define DMA0_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 269 #define DMA0_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 270 #define DMA0_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 271 #define DMA0_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 272 #define DMA0_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 273 #define DMA0_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 274 #define DMA0_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 275 #define DMA0_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 276 #define DMA0_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 277 #define DMA0_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 278 #define DMA0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 279 #define DMA0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 280 #define DMA0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 281 #define DMA0_TRIG4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 282 #define DMA0_TRIG5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 283 #define DMA0_TRIG6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 284 #define DMA0_TRIG7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 285 #define DMA0_TRIG8_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 286 #define DMA0_TRIG9_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 287 #define FC2_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ 288 #define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 289 #define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 290 #define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 291 #define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 292 #define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 293 #define SCT0_OUT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ 294 #define ADC0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 295 #define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 296 #define DMA0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 297 #define DMA0_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 298 #define DMA0_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 299 #define DMA0_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 300 #define DMA0_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 301 #define DMA0_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 302 #define DMA0_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 303 #define DMA0_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 304 #define DMA0_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 305 #define DMA0_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 306 #define DMA0_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 307 #define DMA0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 308 #define DMA0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 309 #define DMA0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 310 #define DMA0_TRIG4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 311 #define DMA0_TRIG5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 312 #define DMA0_TRIG6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 313 #define DMA0_TRIG7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 314 #define DMA0_TRIG8_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 315 #define DMA0_TRIG9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 316 #define FC3_SCK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ 317 #define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ 318 #define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 319 #define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 320 #define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 321 #define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 322 #define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 323 #define ADC0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 324 #define ADC0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 325 #define DMA0_TRIG0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 326 #define DMA0_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 327 #define DMA0_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 328 #define DMA0_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 329 #define DMA0_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 330 #define DMA0_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 331 #define DMA0_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 332 #define DMA0_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 333 #define DMA0_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 334 #define DMA0_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 335 #define DMA0_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 336 #define DMA0_TRIG1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 337 #define DMA0_TRIG2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 338 #define DMA0_TRIG3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 339 #define DMA0_TRIG4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 340 #define DMA0_TRIG5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 341 #define DMA0_TRIG6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 342 #define DMA0_TRIG7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 343 #define DMA0_TRIG8_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 344 #define DMA0_TRIG9_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 345 #define FC3_RXD_SDA_MOSI_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 1) /* PIO0_12 */ 346 #define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 2) /* PIO0_12 */ 347 #define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 348 #define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 349 #define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 350 #define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 351 #define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_D, 0) /* PIO0_12 */ 352 #define ADC0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 353 #define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 354 #define DMA0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 355 #define DMA0_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 356 #define DMA0_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 357 #define DMA0_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 358 #define DMA0_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 359 #define DMA0_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 360 #define DMA0_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 361 #define DMA0_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 362 #define DMA0_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 363 #define DMA0_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 364 #define DMA0_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 365 #define DMA0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 366 #define DMA0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 367 #define DMA0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 368 #define DMA0_TRIG4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 369 #define DMA0_TRIG5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 370 #define DMA0_TRIG6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 371 #define DMA0_TRIG7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 372 #define DMA0_TRIG8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 373 #define DMA0_TRIG9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 374 #define FC3_TXD_SCL_MISO_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 1) /* PIO0_13 */ 375 #define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 376 #define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 377 #define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 378 #define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 379 #define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 0) /* PIO0_13 */ 380 #define SCT0_OUT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_D, 2) /* PIO0_13 */ 381 #define ADC0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 382 #define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 383 #define DMA0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 384 #define DMA0_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 385 #define DMA0_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 386 #define DMA0_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 387 #define DMA0_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 388 #define DMA0_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 389 #define DMA0_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 390 #define DMA0_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 391 #define DMA0_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 392 #define DMA0_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 393 #define DMA0_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 394 #define DMA0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 395 #define DMA0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 396 #define DMA0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 397 #define DMA0_TRIG4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 398 #define DMA0_TRIG5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 399 #define DMA0_TRIG6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 400 #define DMA0_TRIG7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 401 #define DMA0_TRIG8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 402 #define DMA0_TRIG9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 403 #define FC1_SCK_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 5) /* PIO0_14 */ 404 #define FC3_CTS_SDA_SSEL0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 1) /* PIO0_14 */ 405 #define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 406 #define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 407 #define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 408 #define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 409 #define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 0) /* PIO0_14 */ 410 #define SCT0_OUT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_D, 2) /* PIO0_14 */ 411 #define ADC0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 412 #define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 413 #define DMA0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 414 #define DMA0_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 415 #define DMA0_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 416 #define DMA0_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 417 #define DMA0_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 418 #define DMA0_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 419 #define DMA0_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 420 #define DMA0_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 421 #define DMA0_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 422 #define DMA0_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 423 #define DMA0_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 424 #define DMA0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 425 #define DMA0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 426 #define DMA0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 427 #define DMA0_TRIG4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 428 #define DMA0_TRIG5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 429 #define DMA0_TRIG6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 430 #define DMA0_TRIG7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 431 #define DMA0_TRIG8_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 432 #define DMA0_TRIG9_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 433 #define FC3_RTS_SCL_SSEL1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ 434 #define FC4_SCK_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 5) /* PIO0_15 */ 435 #define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 436 #define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 437 #define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 438 #define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 439 #define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 440 #define ADC0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 441 #define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 442 #define CTIMER3_MATCH1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ 443 #define DMA0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 444 #define DMA0_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 445 #define DMA0_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 446 #define DMA0_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 447 #define DMA0_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 448 #define DMA0_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 449 #define DMA0_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 450 #define DMA0_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 451 #define DMA0_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 452 #define DMA0_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 453 #define DMA0_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 454 #define DMA0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 455 #define DMA0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 456 #define DMA0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 457 #define DMA0_TRIG4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 458 #define DMA0_TRIG5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 459 #define DMA0_TRIG6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 460 #define DMA0_TRIG7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 461 #define DMA0_TRIG8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 462 #define DMA0_TRIG9_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 463 #define FC3_SSEL2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ 464 #define FC6_CTS_SDA_SSEL0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ 465 #define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 466 #define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 467 #define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 468 #define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 469 #define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 470 #define SWCLK_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 5) /* PIO0_16 */ 471 #define ADC0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 472 #define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 473 #define CTIMER3_MATCH2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ 474 #define DMA0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 475 #define DMA0_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 476 #define DMA0_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 477 #define DMA0_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 478 #define DMA0_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 479 #define DMA0_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 480 #define DMA0_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 481 #define DMA0_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 482 #define DMA0_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 483 #define DMA0_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 484 #define DMA0_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 485 #define DMA0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 486 #define DMA0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 487 #define DMA0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 488 #define DMA0_TRIG4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 489 #define DMA0_TRIG5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 490 #define DMA0_TRIG6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 491 #define DMA0_TRIG7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 492 #define DMA0_TRIG8_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 493 #define DMA0_TRIG9_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 494 #define FC3_SSEL3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ 495 #define FC6_RTS_SCL_SSEL1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ 496 #define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 497 #define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 498 #define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 499 #define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 500 #define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 501 #define SWDIO_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 5) /* PIO0_17 */ 502 #define ADC0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 503 #define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 504 #define CTIMER0_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 3) /* PIO0_18 */ 505 #define DMA0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 506 #define DMA0_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 507 #define DMA0_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 508 #define DMA0_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 509 #define DMA0_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 510 #define DMA0_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 511 #define DMA0_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 512 #define DMA0_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 513 #define DMA0_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 514 #define DMA0_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 515 #define DMA0_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 516 #define DMA0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 517 #define DMA0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 518 #define DMA0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 519 #define DMA0_TRIG4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 520 #define DMA0_TRIG5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 521 #define DMA0_TRIG6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 522 #define DMA0_TRIG7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 523 #define DMA0_TRIG8_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 524 #define DMA0_TRIG9_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 525 #define FC5_TXD_SCL_MISO_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 1) /* PIO0_18 */ 526 #define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 527 #define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 528 #define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 529 #define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 530 #define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 0) /* PIO0_18 */ 531 #define SCT0_OUT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_D, 2) /* PIO0_18 */ 532 #define ADC0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 533 #define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 534 #define CTIMER0_MATCH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ 535 #define DMA0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 536 #define DMA0_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 537 #define DMA0_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 538 #define DMA0_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 539 #define DMA0_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 540 #define DMA0_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 541 #define DMA0_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 542 #define DMA0_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 543 #define DMA0_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 544 #define DMA0_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 545 #define DMA0_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 546 #define DMA0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 547 #define DMA0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 548 #define DMA0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 549 #define DMA0_TRIG4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 550 #define DMA0_TRIG5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 551 #define DMA0_TRIG6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 552 #define DMA0_TRIG7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 553 #define DMA0_TRIG8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 554 #define DMA0_TRIG9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 555 #define FC5_SCK_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ 556 #define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 557 #define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 558 #define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 559 #define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 560 #define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 561 #define SCT0_OUT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ 562 #define ADC0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 563 #define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 564 #define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 565 #define DMA0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 566 #define DMA0_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 567 #define DMA0_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 568 #define DMA0_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 569 #define DMA0_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 570 #define DMA0_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 571 #define DMA0_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 572 #define DMA0_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 573 #define DMA0_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 574 #define DMA0_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 575 #define DMA0_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 576 #define DMA0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 577 #define DMA0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 578 #define DMA0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 579 #define DMA0_TRIG4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 580 #define DMA0_TRIG5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 581 #define DMA0_TRIG6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 582 #define DMA0_TRIG7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 583 #define DMA0_TRIG8_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 584 #define DMA0_TRIG9_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 585 #define FC0_SCK_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ 586 #define FC5_RXD_SDA_MOSI_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ 587 #define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 588 #define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 589 #define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 590 #define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 591 #define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 592 #define ADC0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 593 #define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 594 #define CLKOUT_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ 595 #define CTIMER3_MATCH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ 596 #define DMA0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 597 #define DMA0_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 598 #define DMA0_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 599 #define DMA0_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 600 #define DMA0_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 601 #define DMA0_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 602 #define DMA0_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 603 #define DMA0_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 604 #define DMA0_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 605 #define DMA0_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 606 #define DMA0_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 607 #define DMA0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 608 #define DMA0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 609 #define DMA0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 610 #define DMA0_TRIG4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 611 #define DMA0_TRIG5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 612 #define DMA0_TRIG6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 613 #define DMA0_TRIG7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 614 #define DMA0_TRIG8_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 615 #define DMA0_TRIG9_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 616 #define FC0_TXD_SCL_MISO_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ 617 #define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 618 #define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 619 #define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 620 #define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 621 #define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 622 #define ADC0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 623 #define ADC0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 624 #define CLKIN_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ 625 #define CTIMER3_MATCH3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ 626 #define DMA0_TRIG0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 627 #define DMA0_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 628 #define DMA0_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 629 #define DMA0_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 630 #define DMA0_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 631 #define DMA0_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 632 #define DMA0_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 633 #define DMA0_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 634 #define DMA0_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 635 #define DMA0_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 636 #define DMA0_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 637 #define DMA0_TRIG1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 638 #define DMA0_TRIG2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 639 #define DMA0_TRIG3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 640 #define DMA0_TRIG4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 641 #define DMA0_TRIG5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 642 #define DMA0_TRIG6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 643 #define DMA0_TRIG7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 644 #define DMA0_TRIG8_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 645 #define DMA0_TRIG9_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 646 #define FC0_RXD_SDA_MOSI_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ 647 #define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 648 #define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 649 #define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 650 #define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 651 #define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 652 #define ADC0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 653 #define ADC0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 654 #define CTIMER0_CAPTURE0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 3) /* PIO0_23 */ 655 #define DMA0_TRIG0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 656 #define DMA0_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 657 #define DMA0_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 658 #define DMA0_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 659 #define DMA0_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 660 #define DMA0_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 661 #define DMA0_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 662 #define DMA0_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 663 #define DMA0_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 664 #define DMA0_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 665 #define DMA0_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 666 #define DMA0_TRIG1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 667 #define DMA0_TRIG2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 668 #define DMA0_TRIG3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 669 #define DMA0_TRIG4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 670 #define DMA0_TRIG5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 671 #define DMA0_TRIG6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 672 #define DMA0_TRIG7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 673 #define DMA0_TRIG8_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 674 #define DMA0_TRIG9_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 675 #define FC1_RTS_SCL_SSEL1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 1) /* PIO0_23 */ 676 #define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 677 #define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 678 #define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 679 #define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 680 #define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 0) /* PIO0_23 */ 681 #define UTICK0_CAPTURE1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_D, 5) /* PIO0_23 */ 682 #define ADC0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 683 #define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 684 #define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ 685 #define CTIMER0_MATCH0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 5) /* PIO0_24 */ 686 #define DMA0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 687 #define DMA0_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 688 #define DMA0_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 689 #define DMA0_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 690 #define DMA0_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 691 #define DMA0_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 692 #define DMA0_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 693 #define DMA0_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 694 #define DMA0_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 695 #define DMA0_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 696 #define DMA0_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 697 #define DMA0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 698 #define DMA0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 699 #define DMA0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 700 #define DMA0_TRIG4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 701 #define DMA0_TRIG5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 702 #define DMA0_TRIG6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 703 #define DMA0_TRIG7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 704 #define DMA0_TRIG8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 705 #define DMA0_TRIG9_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 706 #define FC1_CTS_SDA_SSEL0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ 707 #define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 708 #define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 709 #define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 710 #define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 711 #define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 712 #define ADC0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 713 #define ADC0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 714 #define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ 715 #define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 5) /* PIO0_25 */ 716 #define DMA0_TRIG0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 717 #define DMA0_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 718 #define DMA0_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 719 #define DMA0_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 720 #define DMA0_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 721 #define DMA0_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 722 #define DMA0_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 723 #define DMA0_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 724 #define DMA0_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 725 #define DMA0_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 726 #define DMA0_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 727 #define DMA0_TRIG1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 728 #define DMA0_TRIG2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 729 #define DMA0_TRIG3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 730 #define DMA0_TRIG4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 731 #define DMA0_TRIG5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 732 #define DMA0_TRIG6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 733 #define DMA0_TRIG7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 734 #define DMA0_TRIG8_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 735 #define DMA0_TRIG9_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 736 #define FC4_RTS_SCL_SSEL1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ 737 #define FC6_CTS_SDA_SSEL0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ 738 #define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 739 #define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 740 #define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 741 #define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 742 #define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 743 #define ADC0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 744 #define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 745 #define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 746 #define DMA0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 747 #define DMA0_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 748 #define DMA0_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 749 #define DMA0_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 750 #define DMA0_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 751 #define DMA0_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 752 #define DMA0_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 753 #define DMA0_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 754 #define DMA0_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 755 #define DMA0_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 756 #define DMA0_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 757 #define DMA0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 758 #define DMA0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 759 #define DMA0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 760 #define DMA0_TRIG4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 761 #define DMA0_TRIG5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 762 #define DMA0_TRIG6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 763 #define DMA0_TRIG7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 764 #define DMA0_TRIG8_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 765 #define DMA0_TRIG9_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 766 #define FC4_CTS_SDA_SSEL0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ 767 #define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 768 #define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 769 #define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 770 #define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 771 #define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 772 #define ADC0_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 773 #define ADC0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 774 #define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 775 #define CTIMER0_CAPTURE1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ 776 #define CTIMER0_MATCH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ 777 #define CTIMER0_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ 778 #define DMA0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 779 #define DMA0_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 780 #define DMA0_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 781 #define DMA0_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 782 #define DMA0_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 783 #define DMA0_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 784 #define DMA0_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 785 #define DMA0_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 786 #define DMA0_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 787 #define DMA0_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 788 #define DMA0_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 789 #define DMA0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 790 #define DMA0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 791 #define DMA0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 792 #define DMA0_TRIG4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 793 #define DMA0_TRIG5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 794 #define DMA0_TRIG6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 795 #define DMA0_TRIG7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 796 #define DMA0_TRIG8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 797 #define DMA0_TRIG9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 798 #define FC1_RXD_SDA_MOSI_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ 799 #define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 800 #define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 801 #define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 802 #define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 803 #define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 804 #define SCT0_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 2) /* PIO0_29 */ 805 #define ADC0_CH1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 806 #define ADC0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 807 #define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 808 #define CTIMER0_CAPTURE2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ 809 #define CTIMER0_MATCH2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ 810 #define DMA0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 811 #define DMA0_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 812 #define DMA0_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 813 #define DMA0_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 814 #define DMA0_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 815 #define DMA0_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 816 #define DMA0_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 817 #define DMA0_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 818 #define DMA0_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 819 #define DMA0_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 820 #define DMA0_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 821 #define DMA0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 822 #define DMA0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 823 #define DMA0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 824 #define DMA0_TRIG4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 825 #define DMA0_TRIG5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 826 #define DMA0_TRIG6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 827 #define DMA0_TRIG7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 828 #define DMA0_TRIG8_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 829 #define DMA0_TRIG9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 830 #define FC1_TXD_SCL_MISO_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ 831 #define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 832 #define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 833 #define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 834 #define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 835 #define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 836 #define SCT0_OUT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 2) /* PIO0_30 */ 837 #define ADC0_CH2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 838 #define ADC0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 839 #define ADC0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 840 #define CTIMER0_CAPTURE3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 5) /* PIO0_31 */ 841 #define CTIMER0_MATCH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 6) /* PIO0_31 */ 842 #define DMA0_TRIG0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 843 #define DMA0_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 844 #define DMA0_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 845 #define DMA0_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 846 #define DMA0_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 847 #define DMA0_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 848 #define DMA0_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 849 #define DMA0_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 850 #define DMA0_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 851 #define DMA0_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 852 #define DMA0_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 853 #define DMA0_TRIG1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 854 #define DMA0_TRIG2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 855 #define DMA0_TRIG3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 856 #define DMA0_TRIG4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 857 #define DMA0_TRIG5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 858 #define DMA0_TRIG6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 859 #define DMA0_TRIG7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 860 #define DMA0_TRIG8_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 861 #define DMA0_TRIG9_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 862 #define FC2_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 2) /* PIO0_31 */ 863 #define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 864 #define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 865 #define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 866 #define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 867 #define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_D, 0) /* PIO0_31 */ 868 #define ADC0_CH3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 869 #define ADC0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 870 #define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 871 #define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 5) /* PIO1_0 */ 872 #define CTIMER3_MATCH1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ 873 #define DMA0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 874 #define DMA0_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 875 #define DMA0_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 876 #define DMA0_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 877 #define DMA0_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 878 #define DMA0_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 879 #define DMA0_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 880 #define DMA0_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 881 #define DMA0_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 882 #define DMA0_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 883 #define DMA0_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 884 #define DMA0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 885 #define DMA0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 886 #define DMA0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 887 #define DMA0_TRIG4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 888 #define DMA0_TRIG5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 889 #define DMA0_TRIG6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 890 #define DMA0_TRIG7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 891 #define DMA0_TRIG8_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 892 #define DMA0_TRIG9_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 893 #define FC2_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 2) /* PIO1_0 */ 894 #define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 895 #define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 896 #define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 897 #define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 898 #define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 899 #define ADC0_CH4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 900 #define ADC0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 901 #define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 902 #define DMA0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 903 #define DMA0_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 904 #define DMA0_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 905 #define DMA0_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 906 #define DMA0_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 907 #define DMA0_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 908 #define DMA0_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 909 #define DMA0_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 910 #define DMA0_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 911 #define DMA0_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 912 #define DMA0_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 913 #define DMA0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 914 #define DMA0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 915 #define DMA0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 916 #define DMA0_TRIG4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 917 #define DMA0_TRIG5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 918 #define DMA0_TRIG6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 919 #define DMA0_TRIG7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 920 #define DMA0_TRIG8_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 921 #define DMA0_TRIG9_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 922 #define FC4_TXD_SCL_MISO_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ 923 #define FC5_SSEL2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ 924 #define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 925 #define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 926 #define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 927 #define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 928 #define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 929 #define SCT0_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 930 #define ADC0_CH5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 931 #define ADC0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 932 #define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 933 #define DMA0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 934 #define DMA0_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 935 #define DMA0_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 936 #define DMA0_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 937 #define DMA0_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 938 #define DMA0_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 939 #define DMA0_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 940 #define DMA0_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 941 #define DMA0_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 942 #define DMA0_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 943 #define DMA0_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 944 #define DMA0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 945 #define DMA0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 946 #define DMA0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 947 #define DMA0_TRIG4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 948 #define DMA0_TRIG5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 949 #define DMA0_TRIG6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 950 #define DMA0_TRIG7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 951 #define DMA0_TRIG8_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 952 #define DMA0_TRIG9_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 953 #define FC4_RXD_SDA_MOSI_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ 954 #define FC5_SSEL3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ 955 #define FC7_SSEL3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 2) /* PIO1_2 */ 956 #define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 957 #define MCLK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ 958 #define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 959 #define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 960 #define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 961 #define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 962 #define SCT0_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ 963 #define ADC0_CH6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 964 #define ADC0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 965 #define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 966 #define CTIMER0_CAPTURE1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ 967 #define DMA0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 968 #define DMA0_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 969 #define DMA0_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 970 #define DMA0_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 971 #define DMA0_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 972 #define DMA0_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 973 #define DMA0_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 974 #define DMA0_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 975 #define DMA0_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 976 #define DMA0_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 977 #define DMA0_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 978 #define DMA0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 979 #define DMA0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 980 #define DMA0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 981 #define DMA0_TRIG4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 982 #define DMA0_TRIG5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 983 #define DMA0_TRIG6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 984 #define DMA0_TRIG7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 985 #define DMA0_TRIG8_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 986 #define DMA0_TRIG9_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 987 #define FC3_SCK_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ 988 #define FC7_SSEL2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 2) /* PIO1_3 */ 989 #define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 990 #define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 991 #define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 992 #define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 993 #define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 994 #define SCT0_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 3) /* PIO1_3 */ 995 #define USB0_UP_LED_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ 996 #define ADC0_CH7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 997 #define ADC0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 998 #define ADC0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 999 #define CTIMER0_MATCH1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 6) /* PIO1_4 */ 1000 #define DMA0_TRIG0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 1001 #define DMA0_TRIG10_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 1002 #define DMA0_TRIG11_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 1003 #define DMA0_TRIG12_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 1004 #define DMA0_TRIG13_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 1005 #define DMA0_TRIG14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 1006 #define DMA0_TRIG15_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 1007 #define DMA0_TRIG16_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 1008 #define DMA0_TRIG17_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 1009 #define DMA0_TRIG18_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 1010 #define DMA0_TRIG19_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 1011 #define DMA0_TRIG1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 1012 #define DMA0_TRIG2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 1013 #define DMA0_TRIG3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 1014 #define DMA0_TRIG4_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 1015 #define DMA0_TRIG5_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 1016 #define DMA0_TRIG6_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 1017 #define DMA0_TRIG7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 1018 #define DMA0_TRIG8_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 1019 #define DMA0_TRIG9_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 1020 #define FC3_TXD_SCL_MISO_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 5) /* PIO1_4 */ 1021 #define FC7_RTS_SCL_SSEL1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 2) /* PIO1_4 */ 1022 #define GPIO_PIO14_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 1023 #define PINT_PINT0_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 1024 #define PINT_PINT1_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 1025 #define PINT_PINT2_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 1026 #define PINT_PINT3_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 0) /* PIO1_4 */ 1027 #define SCT0_OUT7_PIO1_4 IOCON_MUX(36, IOCON_TYPE_D, 3) /* PIO1_4 */ 1028 #define ADC0_CH8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1029 #define ADC0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1030 #define ADC0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1031 #define CTIMER1_CAPTURE0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 3) /* PIO1_5 */ 1032 #define CTIMER1_MATCH3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 5) /* PIO1_5 */ 1033 #define DMA0_TRIG0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1034 #define DMA0_TRIG10_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1035 #define DMA0_TRIG11_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1036 #define DMA0_TRIG12_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1037 #define DMA0_TRIG13_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1038 #define DMA0_TRIG14_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1039 #define DMA0_TRIG15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1040 #define DMA0_TRIG16_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1041 #define DMA0_TRIG17_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1042 #define DMA0_TRIG18_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1043 #define DMA0_TRIG19_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1044 #define DMA0_TRIG1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1045 #define DMA0_TRIG2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1046 #define DMA0_TRIG3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1047 #define DMA0_TRIG4_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1048 #define DMA0_TRIG5_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1049 #define DMA0_TRIG6_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1050 #define DMA0_TRIG7_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1051 #define DMA0_TRIG8_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1052 #define DMA0_TRIG9_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1053 #define FC7_CTS_SDA_SSEL0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 2) /* PIO1_5 */ 1054 #define GPIO_PIO15_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1055 #define PINT_PINT0_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1056 #define PINT_PINT1_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1057 #define PINT_PINT2_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1058 #define PINT_PINT3_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 0) /* PIO1_5 */ 1059 #define USB0_FRAME_PIO1_5 IOCON_MUX(37, IOCON_TYPE_D, 7) /* PIO1_5 */ 1060 #define ADC0_CH9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1061 #define ADC0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1062 #define ADC0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1063 #define CTIMER1_CAPTURE2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 3) /* PIO1_6 */ 1064 #define CTIMER1_MATCH2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 5) /* PIO1_6 */ 1065 #define DMA0_TRIG0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1066 #define DMA0_TRIG10_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1067 #define DMA0_TRIG11_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1068 #define DMA0_TRIG12_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1069 #define DMA0_TRIG13_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1070 #define DMA0_TRIG14_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1071 #define DMA0_TRIG15_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1072 #define DMA0_TRIG16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1073 #define DMA0_TRIG17_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1074 #define DMA0_TRIG18_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1075 #define DMA0_TRIG19_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1076 #define DMA0_TRIG1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1077 #define DMA0_TRIG2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1078 #define DMA0_TRIG3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1079 #define DMA0_TRIG4_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1080 #define DMA0_TRIG5_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1081 #define DMA0_TRIG6_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1082 #define DMA0_TRIG7_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1083 #define DMA0_TRIG8_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1084 #define DMA0_TRIG9_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1085 #define FC7_SCK_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 2) /* PIO1_6 */ 1086 #define GPIO_PIO16_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1087 #define PINT_PINT0_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1088 #define PINT_PINT1_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1089 #define PINT_PINT2_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1090 #define PINT_PINT3_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 0) /* PIO1_6 */ 1091 #define USB0_VBUS_PIO1_6 IOCON_MUX(38, IOCON_TYPE_D, 7) /* PIO1_6 */ 1092 #define ADC0_CH10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1093 #define ADC0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1094 #define ADC0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1095 #define CTIMER1_CAPTURE2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 5) /* PIO1_7 */ 1096 #define CTIMER1_MATCH2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 3) /* PIO1_7 */ 1097 #define DMA0_TRIG0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1098 #define DMA0_TRIG10_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1099 #define DMA0_TRIG11_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1100 #define DMA0_TRIG12_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1101 #define DMA0_TRIG13_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1102 #define DMA0_TRIG14_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1103 #define DMA0_TRIG15_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1104 #define DMA0_TRIG16_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1105 #define DMA0_TRIG17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1106 #define DMA0_TRIG18_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1107 #define DMA0_TRIG19_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1108 #define DMA0_TRIG1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1109 #define DMA0_TRIG2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1110 #define DMA0_TRIG3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1111 #define DMA0_TRIG4_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1112 #define DMA0_TRIG5_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1113 #define DMA0_TRIG6_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1114 #define DMA0_TRIG7_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1115 #define DMA0_TRIG8_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1116 #define DMA0_TRIG9_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1117 #define FC7_RXD_SDA_MOSI_DATA_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 2) /* PIO1_7 */ 1118 #define GPIO_PIO17_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1119 #define PINT_PINT0_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1120 #define PINT_PINT1_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1121 #define PINT_PINT2_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1122 #define PINT_PINT3_PIO1_7 IOCON_MUX(39, IOCON_TYPE_D, 0) /* PIO1_7 */ 1123 #define ADC0_CH11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1124 #define ADC0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1125 #define ADC0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1126 #define CTIMER1_CAPTURE3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 5) /* PIO1_8 */ 1127 #define CTIMER1_MATCH3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 3) /* PIO1_8 */ 1128 #define DMA0_TRIG0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1129 #define DMA0_TRIG10_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1130 #define DMA0_TRIG11_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1131 #define DMA0_TRIG12_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1132 #define DMA0_TRIG13_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1133 #define DMA0_TRIG14_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1134 #define DMA0_TRIG15_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1135 #define DMA0_TRIG16_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1136 #define DMA0_TRIG17_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1137 #define DMA0_TRIG18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1138 #define DMA0_TRIG19_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1139 #define DMA0_TRIG1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1140 #define DMA0_TRIG2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1141 #define DMA0_TRIG3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1142 #define DMA0_TRIG4_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1143 #define DMA0_TRIG5_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1144 #define DMA0_TRIG6_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1145 #define DMA0_TRIG7_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1146 #define DMA0_TRIG8_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1147 #define DMA0_TRIG9_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1148 #define FC7_TXD_SCL_MISO_WS_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 2) /* PIO1_8 */ 1149 #define GPIO_PIO18_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1150 #define PINT_PINT0_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1151 #define PINT_PINT1_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1152 #define PINT_PINT2_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1153 #define PINT_PINT3_PIO1_8 IOCON_MUX(40, IOCON_TYPE_D, 0) /* PIO1_8 */ 1154 1155 #endif 1156
