1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2019 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #ifndef _FSL_SDRAMC_H_
9 #define _FSL_SDRAMC_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup sdramc
15 * @{
16 */
17
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 /*! @brief SDRAMC driver version 2.1.1. */
25 #define FSL_SDRAMC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
26 /*@}*/
27
28 /*! @brief SDRAM controller auto-refresh timing. */
29 typedef enum _sdramc_refresh_time
30 {
31 kSDRAMC_RefreshThreeClocks = 0x0U, /*!< The refresh timing with three bus clocks. */
32 kSDRAMC_RefreshSixClocks, /*!< The refresh timing with six bus clocks. */
33 kSDRAMC_RefreshNineClocks /*!< The refresh timing with nine bus clocks. */
34 } sdramc_refresh_time_t;
35
36 /*!
37 * @brief Setting latency for SDRAM controller timing specifications.
38 *
39 * The latency setting affects the following SDRAM timing specifications:
40 * - trcd: SRAS assertion to SCAS assertion \n
41 * - tcasl: SCAS assertion to data out \n
42 * - tras: ACTV command to Precharge command \n
43 * - trp: Precharge command to ACTV command \n
44 * - trwl, trdl: Last data input to Precharge command \n
45 * - tep: Last data out to Precharge command \n
46 * The details of the latency setting and timing specifications are shown in the following table list. \n
47 * latency trcd: tcasl tras trp trwl,trdl tep \n
48 * 0 1 bus clock 1 bus clock 2 bus clocks 1 bus clock 1 bus clock 1 bus clock \n
49 * 1 2 bus clock 2 bus clock 4 bus clocks 2 bus clock 1 bus clock 1 bus clock \n
50 * 2 3 bus clock 3 bus clock 6 bus clocks 3 bus clock 1 bus clock 1 bus clock \n
51 * 3 3 bus clock 3 bus clock 6 bus clocks 3 bus clock 1 bus clock 1 bus clock \n
52 */
53 typedef enum _sdramc_latency
54 {
55 kSDRAMC_LatencyZero = 0x0U, /*!< Latency 0. */
56 kSDRAMC_LatencyOne, /*!< Latency 1. */
57 kSDRAMC_LatencyTwo, /*!< Latency 2. */
58 kSDRAMC_LatencyThree, /*!< Latency 3. */
59 } sdramc_latency_t;
60
61 /*! @brief SDRAM controller command bit location. */
62 typedef enum _sdramc_command_bit_location
63 {
64 kSDRAMC_Commandbit17 = 0x0U, /*!< Command bit location is bit 17. */
65 kSDRAMC_Commandbit18, /*!< Command bit location is bit 18. */
66 kSDRAMC_Commandbit19, /*!< Command bit location is bit 19. */
67 kSDRAMC_Commandbit20, /*!< Command bit location is bit 20. */
68 kSDRAMC_Commandbit21, /*!< Command bit location is bit 21. */
69 kSDRAMC_Commandbit22, /*!< Command bit location is bit 22. */
70 kSDRAMC_Commandbit23, /*!< Command bit location is bit 23. */
71 kSDRAMC_Commandbit24 /*!< Command bit location is bit 24. */
72 } sdramc_command_bit_location_t;
73
74 /*! @brief SDRAM controller command. */
75 typedef enum _sdramc_command
76 {
77 kSDRAMC_ImrsCommand = 0x0U, /*!< Initiate MRS command. */
78 kSDRAMC_PrechargeCommand, /*!< Initiate precharge command. */
79 kSDRAMC_SelfrefreshEnterCommand, /*!< Enter self-refresh command. */
80 kSDRAMC_SelfrefreshExitCommand, /*!< Exit self-refresh command. */
81 kSDRAMC_AutoRefreshEnableCommand, /*!< Enable Auto refresh command. */
82 kSDRAMC_AutoRefreshDisableCommand, /*!< Disable Auto refresh command. */
83 } sdramc_command_t;
84
85 /*! @brief SDRAM port size. */
86 typedef enum _sdramc_port_size
87 {
88 kSDRAMC_PortSize32Bit = 0x0U, /*!< 32-Bit port size. */
89 kSDRAMC_PortSize8Bit, /*!< 8-Bit port size. */
90 kSDRAMC_PortSize16Bit /*!< 16-Bit port size. */
91 } sdramc_port_size_t;
92
93 /*! @brief SDRAM controller block selection. */
94 typedef enum _sdramc_block_selection
95 {
96 kSDRAMC_Block0 = 0x0U, /*!< Select SDRAM block 0. */
97 kSDRAMC_Block1, /*!< Select SDRAM block 1. */
98 } sdramc_block_selection_t;
99
100 /*! @brief SDRAM controller block control configuration structure. */
101 typedef struct _sdramc_blockctl_config
102 {
103 sdramc_block_selection_t block; /*!< The block number. */
104 sdramc_port_size_t portSize; /*!< The port size of the associated SDRAM block. */
105 sdramc_command_bit_location_t location; /*!< The command bit location. */
106 sdramc_latency_t latency; /*!< The latency for some timing specifications. */
107 uint32_t address; /*!< The base address of the SDRAM block. */
108 uint32_t addressMask; /*!< The base address mask of the SDRAM block. */
109 } sdramc_blockctl_config_t;
110
111 /*! @brief SDRAM controller refresh timing configuration structure. */
112 typedef struct _sdramc_refresh_config
113 {
114 sdramc_refresh_time_t refreshTime; /*!< Trc:The number of bus clocks inserted
115 between a REF and next ACTIVE command. */
116 uint32_t sdramRefreshRow; /*!< The SDRAM refresh time each row: ns/row. */
117 uint32_t busClock_Hz; /*!< The bus clock for SDRAMC. */
118 } sdramc_refresh_config_t;
119
120 /*!
121 * @brief SDRAM controller configuration structure.
122 *
123 * Defines a configure structure and uses the SDRAMC_Configure() function to make necessary
124 * initializations.
125 */
126 typedef struct _sdramc_config_t
127 {
128 sdramc_refresh_config_t *refreshConfig; /*!< Refresh timing configure structure pointer. */
129 sdramc_blockctl_config_t *blockConfig; /*!< Block configure structure pointer. If both SDRAM
130 blocks are used, use the two continuous blockConfig. */
131 uint8_t numBlockConfig; /*!< SDRAM block numbers for configuration. */
132 } sdramc_config_t;
133
134 /*******************************************************************************
135 * API
136 ******************************************************************************/
137
138 #if defined(__cplusplus)
139 extern "C" {
140 #endif
141
142 /*!
143 * @name SDRAM Controller Initialization and De-initialization
144 * @{
145 */
146
147 /*!
148 * @brief Initializes the SDRAM controller.
149 * This function ungates the SDRAM controller clock and initializes the SDRAM controller.
150 * This function must be called before calling any other SDRAM controller driver functions.
151 * Example
152 @code
153 sdramc_refresh_config_t refreshConfig;
154 sdramc_blockctl_config_t blockConfig;
155 sdramc_config_t config;
156
157 refreshConfig.refreshTime = kSDRAM_RefreshThreeClocks;
158 refreshConfig.sdramRefreshRow = 15625;
159 refreshConfig.busClock = 60000000;
160
161 blockConfig.block = kSDRAMC_Block0;
162 blockConfig.portSize = kSDRAMC_PortSize16Bit;
163 blockConfig.location = kSDRAMC_Commandbit19;
164 blockConfig.latency = kSDRAMC_RefreshThreeClocks;
165 blockConfig.address = SDRAM_START_ADDRESS;
166 blockConfig.addressMask = 0x7c0000;
167
168 config.refreshConfig = &refreshConfig,
169 config.blockConfig = &blockConfig,
170 config.totalBlocks = 1;
171
172 SDRAMC_Init(SDRAM, &config);
173 @endcode
174 *
175 * @param base SDRAM controller peripheral base address.
176 * @param configure The SDRAM configuration structure pointer.
177 */
178 void SDRAMC_Init(SDRAM_Type *base, sdramc_config_t *configure);
179
180 /*!
181 * @brief Deinitializes the SDRAM controller module and gates the clock.
182 * This function gates the SDRAM controller clock. As a result, the SDRAM
183 * controller module doesn't work after calling this function.
184 *
185 * @param base SDRAM controller peripheral base address.
186 */
187 void SDRAMC_Deinit(SDRAM_Type *base);
188
189 /* @} */
190
191 /*!
192 * @name SDRAM Controller Basic Operation
193 * @{
194 */
195
196 /*!
197 * @brief Sends the SDRAM command.
198 * This function sends commands to SDRAM. The commands are precharge command, initialization MRS command,
199 * auto-refresh enable/disable command, and self-refresh enter/exit commands.
200 * Note that the self-refresh enter/exit commands are all blocks setting and "block"
201 * is ignored. Ensure to set the correct "block" when send other commands.
202 *
203 * @param base SDRAM controller peripheral base address.
204 * @param block The block selection.
205 * @param command The SDRAM command, see "sdramc_command_t".
206 * kSDRAMC_ImrsCommand - Initialize MRS command \n
207 * kSDRAMC_PrechargeCommand - Initialize precharge command \n
208 * kSDRAMC_SelfrefreshEnterCommand - Enter self-refresh command \n
209 * kSDRAMC_SelfrefreshExitCommand - Exit self-refresh command \n
210 * kSDRAMC_AutoRefreshEnableCommand - Enable auto refresh command \n
211 * kSDRAMC_AutoRefreshDisableCommand - Disable auto refresh command
212 */
213 void SDRAMC_SendCommand(SDRAM_Type *base, sdramc_block_selection_t block, sdramc_command_t command);
214
215 /*!
216 * @brief Enables/disables the write protection.
217 *
218 * @param base SDRAM peripheral base address.
219 * @param block The block which is selected.
220 * @param enable True enable write protection, false disable write protection.
221 */
SDRAMC_EnableWriteProtect(SDRAM_Type * base,sdramc_block_selection_t block,bool enable)222 static inline void SDRAMC_EnableWriteProtect(SDRAM_Type *base, sdramc_block_selection_t block, bool enable)
223 {
224 if (enable)
225 {
226 base->BLOCK[block].CM |= SDRAM_CM_WP_MASK;
227 }
228 else
229 {
230 base->BLOCK[block].CM &= ~SDRAM_CM_WP_MASK;
231 }
232 }
233
234 /*!
235 * @brief Enables/disables the valid operation.
236 *
237 * @param base SDRAM peripheral base address.
238 * @param block The block which is selected.
239 * @param enable True enable the valid operation; false disable the valid operation.
240 */
SDRAMC_EnableOperateValid(SDRAM_Type * base,sdramc_block_selection_t block,bool enable)241 static inline void SDRAMC_EnableOperateValid(SDRAM_Type *base, sdramc_block_selection_t block, bool enable)
242 {
243 if (enable)
244 {
245 base->BLOCK[block].CM |= SDRAM_CM_V_MASK;
246 }
247 else
248 {
249 base->BLOCK[block].CM &= ~SDRAM_CM_V_MASK;
250 }
251 }
252
253 /* @} */
254
255 #if defined(__cplusplus)
256 }
257 #endif
258
259 /*! @}*/
260
261 #endif /* _FSL_SDRAMC_H_*/
262
