1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2020 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #ifndef _FSL_LPSPI_H_
9 #define _FSL_LPSPI_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup lpspi_driver
15 * @{
16 */
17
18 /**********************************************************************************************************************
19 * Definitions
20 *********************************************************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 /*! @brief LPSPI driver version 2.0.5. */
25 #define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))
26 /*@}*/
27
28 #ifndef LPSPI_DUMMY_DATA
29 /*! @brief LPSPI dummy data if no Tx data.*/
30 #define LPSPI_DUMMY_DATA (0x00U) /*!< Dummy data used for tx if there is not txData. */
31 #endif
32
33 /*! @brief Retry times for waiting flag. */
34 #ifndef SPI_RETRY_TIMES
35 #define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */
36 #endif
37
38 /*! @brief Global variable for dummy data value setting. */
39 extern volatile uint8_t g_lpspiDummyData[];
40
41 /*! @brief Status for the LPSPI driver.*/
42 enum
43 {
44 kStatus_LPSPI_Busy = MAKE_STATUS(kStatusGroup_LPSPI, 0), /*!< LPSPI transfer is busy.*/
45 kStatus_LPSPI_Error = MAKE_STATUS(kStatusGroup_LPSPI, 1), /*!< LPSPI driver error. */
46 kStatus_LPSPI_Idle = MAKE_STATUS(kStatusGroup_LPSPI, 2), /*!< LPSPI is idle.*/
47 kStatus_LPSPI_OutOfRange = MAKE_STATUS(kStatusGroup_LPSPI, 3), /*!< LPSPI transfer out Of range. */
48 kStatus_LPSPI_Timeout = MAKE_STATUS(kStatusGroup_LPSPI, 4) /*!< LPSPI timeout polling status flags. */
49 };
50
51 /*! @brief LPSPI status flags in SPIx_SR register.*/
52 enum _lpspi_flags
53 {
54 kLPSPI_TxDataRequestFlag = LPSPI_SR_TDF_MASK, /*!< Transmit data flag */
55 kLPSPI_RxDataReadyFlag = LPSPI_SR_RDF_MASK, /*!< Receive data flag */
56 kLPSPI_WordCompleteFlag = LPSPI_SR_WCF_MASK, /*!< Word Complete flag */
57 kLPSPI_FrameCompleteFlag = LPSPI_SR_FCF_MASK, /*!< Frame Complete flag */
58 kLPSPI_TransferCompleteFlag = LPSPI_SR_TCF_MASK, /*!< Transfer Complete flag */
59 kLPSPI_TransmitErrorFlag = LPSPI_SR_TEF_MASK, /*!< Transmit Error flag (FIFO underrun) */
60 kLPSPI_ReceiveErrorFlag = LPSPI_SR_REF_MASK, /*!< Receive Error flag (FIFO overrun) */
61 kLPSPI_DataMatchFlag = LPSPI_SR_DMF_MASK, /*!< Data Match flag */
62 kLPSPI_ModuleBusyFlag = LPSPI_SR_MBF_MASK, /*!< Module Busy flag */
63 kLPSPI_AllStatusFlag = (LPSPI_SR_TDF_MASK | LPSPI_SR_RDF_MASK | LPSPI_SR_WCF_MASK | LPSPI_SR_FCF_MASK |
64 LPSPI_SR_TCF_MASK | LPSPI_SR_TEF_MASK | LPSPI_SR_REF_MASK | LPSPI_SR_DMF_MASK |
65 LPSPI_SR_MBF_MASK) /*!< Used for clearing all w1c status flags */
66 };
67
68 /*! @brief LPSPI interrupt source.*/
69 enum _lpspi_interrupt_enable
70 {
71 kLPSPI_TxInterruptEnable = LPSPI_IER_TDIE_MASK, /*!< Transmit data interrupt enable */
72 kLPSPI_RxInterruptEnable = LPSPI_IER_RDIE_MASK, /*!< Receive data interrupt enable */
73 kLPSPI_WordCompleteInterruptEnable = LPSPI_IER_WCIE_MASK, /*!< Word complete interrupt enable */
74 kLPSPI_FrameCompleteInterruptEnable = LPSPI_IER_FCIE_MASK, /*!< Frame complete interrupt enable */
75 kLPSPI_TransferCompleteInterruptEnable = LPSPI_IER_TCIE_MASK, /*!< Transfer complete interrupt enable */
76 kLPSPI_TransmitErrorInterruptEnable = LPSPI_IER_TEIE_MASK, /*!< Transmit error interrupt enable(FIFO underrun)*/
77 kLPSPI_ReceiveErrorInterruptEnable = LPSPI_IER_REIE_MASK, /*!< Receive Error interrupt enable (FIFO overrun) */
78 kLPSPI_DataMatchInterruptEnable = LPSPI_IER_DMIE_MASK, /*!< Data Match interrupt enable */
79 kLPSPI_AllInterruptEnable =
80 (LPSPI_IER_TDIE_MASK | LPSPI_IER_RDIE_MASK | LPSPI_IER_WCIE_MASK | LPSPI_IER_FCIE_MASK | LPSPI_IER_TCIE_MASK |
81 LPSPI_IER_TEIE_MASK | LPSPI_IER_REIE_MASK | LPSPI_IER_DMIE_MASK) /*!< All above interrupts enable.*/
82 };
83
84 /*! @brief LPSPI DMA source.*/
85 enum _lpspi_dma_enable
86 {
87 kLPSPI_TxDmaEnable = LPSPI_DER_TDDE_MASK, /*!< Transmit data DMA enable */
88 kLPSPI_RxDmaEnable = LPSPI_DER_RDDE_MASK /*!< Receive data DMA enable */
89 };
90
91 /*! @brief LPSPI master or slave mode configuration.*/
92 typedef enum _lpspi_master_slave_mode
93 {
94 kLPSPI_Master = 1U, /*!< LPSPI peripheral operates in master mode.*/
95 kLPSPI_Slave = 0U /*!< LPSPI peripheral operates in slave mode.*/
96 } lpspi_master_slave_mode_t;
97
98 /*! @brief LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).*/
99 typedef enum _lpspi_which_pcs_config
100 {
101 kLPSPI_Pcs0 = 0U, /*!< PCS[0] */
102 kLPSPI_Pcs1 = 1U, /*!< PCS[1] */
103 kLPSPI_Pcs2 = 2U, /*!< PCS[2] */
104 kLPSPI_Pcs3 = 3U /*!< PCS[3] */
105 } lpspi_which_pcs_t;
106
107 /*! @brief LPSPI Peripheral Chip Select (PCS) Polarity configuration.*/
108 typedef enum _lpspi_pcs_polarity_config
109 {
110 kLPSPI_PcsActiveHigh = 1U, /*!< PCS Active High (idles low) */
111 kLPSPI_PcsActiveLow = 0U /*!< PCS Active Low (idles high) */
112 } lpspi_pcs_polarity_config_t;
113
114 /*! @brief LPSPI Peripheral Chip Select (PCS) Polarity.*/
115 enum _lpspi_pcs_polarity
116 {
117 kLPSPI_Pcs0ActiveLow = 1U << 0, /*!< Pcs0 Active Low (idles high). */
118 kLPSPI_Pcs1ActiveLow = 1U << 1, /*!< Pcs1 Active Low (idles high). */
119 kLPSPI_Pcs2ActiveLow = 1U << 2, /*!< Pcs2 Active Low (idles high). */
120 kLPSPI_Pcs3ActiveLow = 1U << 3, /*!< Pcs3 Active Low (idles high). */
121 kLPSPI_PcsAllActiveLow = 0xFU /*!< Pcs0 to Pcs5 Active Low (idles high). */
122 };
123
124 /*! @brief LPSPI clock polarity configuration.*/
125 typedef enum _lpspi_clock_polarity
126 {
127 kLPSPI_ClockPolarityActiveHigh = 0U, /*!< CPOL=0. Active-high LPSPI clock (idles low)*/
128 kLPSPI_ClockPolarityActiveLow = 1U /*!< CPOL=1. Active-low LPSPI clock (idles high)*/
129 } lpspi_clock_polarity_t;
130
131 /*! @brief LPSPI clock phase configuration.*/
132 typedef enum _lpspi_clock_phase
133 {
134 kLPSPI_ClockPhaseFirstEdge = 0U, /*!< CPHA=0. Data is captured on the leading edge of the SCK and changed on the
135 following edge.*/
136 kLPSPI_ClockPhaseSecondEdge = 1U /*!< CPHA=1. Data is changed on the leading edge of the SCK and captured on the
137 following edge.*/
138 } lpspi_clock_phase_t;
139
140 /*! @brief LPSPI data shifter direction options.*/
141 typedef enum _lpspi_shift_direction
142 {
143 kLPSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit.*/
144 kLPSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit.*/
145 } lpspi_shift_direction_t;
146
147 /*! @brief LPSPI Host Request select configuration. */
148 typedef enum _lpspi_host_request_select
149 {
150 kLPSPI_HostReqExtPin = 0U, /*!< Host Request is an ext pin. */
151 kLPSPI_HostReqInternalTrigger = 1U /*!< Host Request is an internal trigger. */
152 } lpspi_host_request_select_t;
153
154 /*! @brief LPSPI Match configuration options. */
155 typedef enum _lpspi_match_config
156 {
157 kLPSI_MatchDisabled = 0x0U, /*!< LPSPI Match Disabled. */
158 kLPSI_1stWordEqualsM0orM1 = 0x2U, /*!< LPSPI Match Enabled. */
159 kLPSI_AnyWordEqualsM0orM1 = 0x3U, /*!< LPSPI Match Enabled. */
160 kLPSI_1stWordEqualsM0and2ndWordEqualsM1 = 0x4U, /*!< LPSPI Match Enabled. */
161 kLPSI_AnyWordEqualsM0andNxtWordEqualsM1 = 0x5U, /*!< LPSPI Match Enabled. */
162 kLPSI_1stWordAndM1EqualsM0andM1 = 0x6U, /*!< LPSPI Match Enabled. */
163 kLPSI_AnyWordAndM1EqualsM0andM1 = 0x7U, /*!< LPSPI Match Enabled. */
164 } lpspi_match_config_t;
165
166 /*! @brief LPSPI pin (SDO and SDI) configuration. */
167 typedef enum _lpspi_pin_config
168 {
169 kLPSPI_SdiInSdoOut = 0U, /*!< LPSPI SDI input, SDO output. */
170 kLPSPI_SdiInSdiOut = 1U, /*!< LPSPI SDI input, SDI output. */
171 kLPSPI_SdoInSdoOut = 2U, /*!< LPSPI SDO input, SDO output. */
172 kLPSPI_SdoInSdiOut = 3U /*!< LPSPI SDO input, SDI output. */
173 } lpspi_pin_config_t;
174
175 /*! @brief LPSPI data output configuration. */
176 typedef enum _lpspi_data_out_config
177 {
178 kLpspiDataOutRetained = 0U, /*!< Data out retains last value when chip select is de-asserted */
179 kLpspiDataOutTristate = 1U /*!< Data out is tristated when chip select is de-asserted */
180 } lpspi_data_out_config_t;
181
182 /*! @brief LPSPI transfer width configuration. */
183 typedef enum _lpspi_transfer_width
184 {
185 kLPSPI_SingleBitXfer = 0U, /*!< 1-bit shift at a time, data out on SDO, in on SDI (normal mode) */
186 kLPSPI_TwoBitXfer = 1U, /*!< 2-bits shift out on SDO/SDI and in on SDO/SDI */
187 kLPSPI_FourBitXfer = 2U /*!< 4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2] */
188 } lpspi_transfer_width_t;
189
190 /*! @brief LPSPI delay type selection.*/
191 typedef enum _lpspi_delay_type
192 {
193 kLPSPI_PcsToSck = 1U, /*!< PCS-to-SCK delay. */
194 kLPSPI_LastSckToPcs, /*!< Last SCK edge to PCS delay. */
195 kLPSPI_BetweenTransfer /*!< Delay between transfers. */
196 } lpspi_delay_type_t;
197
198 #define LPSPI_MASTER_PCS_SHIFT (4U) /*!< LPSPI master PCS shift macro , internal used. */
199 #define LPSPI_MASTER_PCS_MASK (0xF0U) /*!< LPSPI master PCS shift macro , internal used. */
200
201 /*! @brief Use this enumeration for LPSPI master transfer configFlags. */
202 enum _lpspi_transfer_config_flag_for_master
203 {
204 kLPSPI_MasterPcs0 = 0U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS0 signal */
205 kLPSPI_MasterPcs1 = 1U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS1 signal */
206 kLPSPI_MasterPcs2 = 2U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS2 signal */
207 kLPSPI_MasterPcs3 = 3U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS3 signal */
208
209 kLPSPI_MasterPcsContinuous = 1U << 20, /*!< Is PCS signal continuous */
210
211 kLPSPI_MasterByteSwap =
212 1U << 22 /*!< Is master swap the byte.
213 * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set
214 * lpspi_shift_direction_t to MSB).
215 * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used
216 * or not, the waveform is 1 2 3 4 5 6 7 8.
217 * 2. If you set bitPerFrame = 16 :
218 * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag.
219 * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.
220 * 3. If you set bitPerFrame = 32 :
221 * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag.
222 * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.
223 */
224 };
225
226 #define LPSPI_SLAVE_PCS_SHIFT (4U) /*!< LPSPI slave PCS shift macro , internal used. */
227 #define LPSPI_SLAVE_PCS_MASK (0xF0U) /*!< LPSPI slave PCS shift macro , internal used. */
228
229 /*! @brief Use this enumeration for LPSPI slave transfer configFlags. */
230 enum _lpspi_transfer_config_flag_for_slave
231 {
232 kLPSPI_SlavePcs0 = 0U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS0 signal */
233 kLPSPI_SlavePcs1 = 1U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS1 signal */
234 kLPSPI_SlavePcs2 = 2U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS2 signal */
235 kLPSPI_SlavePcs3 = 3U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS3 signal */
236
237 kLPSPI_SlaveByteSwap =
238 1U << 22 /*!< Is slave swap the byte.
239 * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set
240 * lpspi_shift_direction_t to MSB).
241 * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used
242 * or not, the waveform is 1 2 3 4 5 6 7 8.
243 * 2. If you set bitPerFrame = 16 :
244 * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag.
245 * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.
246 * 3. If you set bitPerFrame = 32 :
247 * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag.
248 * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.
249 */
250 };
251
252 /*! @brief LPSPI transfer state, which is used for LPSPI transactional API state machine. */
253 enum _lpspi_transfer_state
254 {
255 kLPSPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver. */
256 kLPSPI_Busy, /*!< Transfer queue is not finished. */
257 kLPSPI_Error /*!< Transfer error. */
258 };
259
260 /*! @brief LPSPI master configuration structure.*/
261 typedef struct _lpspi_master_config
262 {
263 uint32_t baudRate; /*!< Baud Rate for LPSPI. */
264 uint32_t bitsPerFrame; /*!< Bits per frame, minimum 8, maximum 4096.*/
265 lpspi_clock_polarity_t cpol; /*!< Clock polarity. */
266 lpspi_clock_phase_t cpha; /*!< Clock phase. */
267 lpspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */
268
269 uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time in nanoseconds, setting to 0 sets the minimum delay.
270 It sets the boundary value if out of range.*/
271 uint32_t lastSckToPcsDelayInNanoSec; /*!< Last SCK to PCS delay time in nanoseconds, setting to 0 sets the minimum
272 delay. It sets the boundary value if out of range.*/
273 uint32_t betweenTransferDelayInNanoSec; /*!< After the SCK delay time with nanoseconds, setting to 0 sets the
274 minimum delay. It sets the boundary value if out of range.*/
275
276 lpspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (PCS). */
277 lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low */
278
279 lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data
280 *during single bit transfers.*/
281
282 lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated
283 * between accesses (LPSPI_PCS is negated). */
284 } lpspi_master_config_t;
285
286 /*! @brief LPSPI slave configuration structure.*/
287 typedef struct _lpspi_slave_config
288 {
289 uint32_t bitsPerFrame; /*!< Bits per frame, minimum 8, maximum 4096.*/
290 lpspi_clock_polarity_t cpol; /*!< Clock polarity. */
291 lpspi_clock_phase_t cpha; /*!< Clock phase. */
292 lpspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */
293
294 lpspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (pcs) */
295 lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low */
296
297 lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data
298 *during single bit transfers.*/
299
300 lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated
301 * between accesses (LPSPI_PCS is negated). */
302 } lpspi_slave_config_t;
303
304 /*!
305 * @brief Forward declaration of the _lpspi_master_handle typedefs.
306 */
307 typedef struct _lpspi_master_handle lpspi_master_handle_t;
308
309 /*!
310 * @brief Forward declaration of the _lpspi_slave_handle typedefs.
311 */
312 typedef struct _lpspi_slave_handle lpspi_slave_handle_t;
313
314 /*!
315 * @brief Master completion callback function pointer type.
316 *
317 * @param base LPSPI peripheral address.
318 * @param handle Pointer to the handle for the LPSPI master.
319 * @param status Success or error code describing whether the transfer is completed.
320 * @param userData Arbitrary pointer-dataSized value passed from the application.
321 */
322 typedef void (*lpspi_master_transfer_callback_t)(LPSPI_Type *base,
323 lpspi_master_handle_t *handle,
324 status_t status,
325 void *userData);
326
327 /*!
328 * @brief Slave completion callback function pointer type.
329 *
330 * @param base LPSPI peripheral address.
331 * @param handle Pointer to the handle for the LPSPI slave.
332 * @param status Success or error code describing whether the transfer is completed.
333 * @param userData Arbitrary pointer-dataSized value passed from the application.
334 */
335 typedef void (*lpspi_slave_transfer_callback_t)(LPSPI_Type *base,
336 lpspi_slave_handle_t *handle,
337 status_t status,
338 void *userData);
339
340 /*! @brief LPSPI master/slave transfer structure.*/
341 typedef struct _lpspi_transfer
342 {
343 uint8_t *txData; /*!< Send buffer. */
344 uint8_t *rxData; /*!< Receive buffer. */
345 volatile size_t dataSize; /*!< Transfer bytes. */
346
347 uint32_t configFlags; /*!< Transfer transfer configuration flags. Set from _lpspi_transfer_config_flag_for_master if
348 the transfer is used for master or _lpspi_transfer_config_flag_for_slave enumeration if the
349 transfer is used for slave.*/
350 } lpspi_transfer_t;
351
352 /*! @brief LPSPI master transfer handle structure used for transactional API. */
353 struct _lpspi_master_handle
354 {
355 volatile bool isPcsContinuous; /*!< Is PCS continuous in transfer. */
356 volatile bool writeTcrInIsr; /*!< A flag that whether should write TCR in ISR. */
357
358 volatile bool isByteSwap; /*!< A flag that whether should byte swap. */
359
360 volatile uint8_t fifoSize; /*!< FIFO dataSize. */
361
362 volatile uint8_t rxWatermark; /*!< Rx watermark. */
363
364 volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */
365 volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */
366
367 uint8_t *volatile txData; /*!< Send buffer. */
368 uint8_t *volatile rxData; /*!< Receive buffer. */
369 volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
370 volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/
371
372 volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */
373 volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */
374
375 uint32_t totalByteCount; /*!< Number of transfer bytes*/
376
377 uint32_t txBuffIfNull; /*!< Used if the txData is NULL. */
378
379 volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/
380
381 lpspi_master_transfer_callback_t callback; /*!< Completion callback. */
382 void *userData; /*!< Callback user data. */
383 };
384
385 /*! @brief LPSPI slave transfer handle structure used for transactional API. */
386 struct _lpspi_slave_handle
387 {
388 volatile bool isByteSwap; /*!< A flag that whether should byte swap. */
389
390 volatile uint8_t fifoSize; /*!< FIFO dataSize. */
391
392 volatile uint8_t rxWatermark; /*!< Rx watermark. */
393
394 volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */
395 volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */
396
397 uint8_t *volatile txData; /*!< Send buffer. */
398 uint8_t *volatile rxData; /*!< Receive buffer. */
399
400 volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
401 volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/
402
403 volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */
404 volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */
405
406 uint32_t totalByteCount; /*!< Number of transfer bytes*/
407
408 volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/
409
410 volatile uint32_t errorCount; /*!< Error count for slave transfer.*/
411
412 lpspi_slave_transfer_callback_t callback; /*!< Completion callback. */
413 void *userData; /*!< Callback user data. */
414 };
415
416 /**********************************************************************************************************************
417 * API
418 *********************************************************************************************************************/
419 #if defined(__cplusplus)
420 extern "C" {
421 #endif /*_cplusplus*/
422
423 /*!
424 * @name Initialization and deinitialization
425 * @{
426 */
427
428 /*!
429 * @brief Initializes the LPSPI master.
430 *
431 * @param base LPSPI peripheral address.
432 * @param masterConfig Pointer to structure lpspi_master_config_t.
433 * @param srcClock_Hz Module source input clock in Hertz
434 */
435 void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz);
436
437 /*!
438 * @brief Sets the lpspi_master_config_t structure to default values.
439 *
440 * This API initializes the configuration structure for LPSPI_MasterInit().
441 * The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified
442 * before calling the LPSPI_MasterInit().
443 * Example:
444 * @code
445 * lpspi_master_config_t masterConfig;
446 * LPSPI_MasterGetDefaultConfig(&masterConfig);
447 * @endcode
448 * @param masterConfig pointer to lpspi_master_config_t structure
449 */
450 void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig);
451
452 /*!
453 * @brief LPSPI slave configuration.
454 *
455 * @param base LPSPI peripheral address.
456 * @param slaveConfig Pointer to a structure lpspi_slave_config_t.
457 */
458 void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig);
459
460 /*!
461 * @brief Sets the lpspi_slave_config_t structure to default values.
462 *
463 * This API initializes the configuration structure for LPSPI_SlaveInit().
464 * The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified
465 * before calling the LPSPI_SlaveInit().
466 * Example:
467 * @code
468 * lpspi_slave_config_t slaveConfig;
469 * LPSPI_SlaveGetDefaultConfig(&slaveConfig);
470 * @endcode
471 * @param slaveConfig pointer to lpspi_slave_config_t structure.
472 */
473 void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig);
474
475 /*!
476 * @brief De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock.
477 * @param base LPSPI peripheral address.
478 */
479 void LPSPI_Deinit(LPSPI_Type *base);
480
481 /*!
482 * @brief Restores the LPSPI peripheral to reset state. Note that this function
483 * sets all registers to reset state. As a result, the LPSPI module can't work after calling
484 * this API.
485 * @param base LPSPI peripheral address.
486 */
487 void LPSPI_Reset(LPSPI_Type *base);
488
489 /*!
490 * @brief Get the LPSPI instance from peripheral base address.
491 *
492 * @param base LPSPI peripheral base address.
493 * @return LPSPI instance.
494 */
495 uint32_t LPSPI_GetInstance(LPSPI_Type *base);
496
497 /*!
498 * @brief Enables the LPSPI peripheral and sets the MCR MDIS to 0.
499 *
500 * @param base LPSPI peripheral address.
501 * @param enable Pass true to enable module, false to disable module.
502 */
LPSPI_Enable(LPSPI_Type * base,bool enable)503 static inline void LPSPI_Enable(LPSPI_Type *base, bool enable)
504 {
505 if (enable)
506 {
507 base->CR |= LPSPI_CR_MEN_MASK;
508 }
509 else
510 {
511 base->CR &= ~LPSPI_CR_MEN_MASK;
512 }
513 }
514
515 /*!
516 *@}
517 */
518
519 /*!
520 * @name Status
521 * @{
522 */
523
524 /*!
525 * @brief Gets the LPSPI status flag state.
526 * @param base LPSPI peripheral address.
527 * @return The LPSPI status(in SR register).
528 */
LPSPI_GetStatusFlags(LPSPI_Type * base)529 static inline uint32_t LPSPI_GetStatusFlags(LPSPI_Type *base)
530 {
531 return (base->SR);
532 }
533
534 /*!
535 * @brief Gets the LPSPI Tx FIFO size.
536 * @param base LPSPI peripheral address.
537 * @return The LPSPI Tx FIFO size.
538 */
LPSPI_GetTxFifoSize(LPSPI_Type * base)539 static inline uint8_t LPSPI_GetTxFifoSize(LPSPI_Type *base)
540 {
541 return (1U << ((base->PARAM & LPSPI_PARAM_TXFIFO_MASK) >> LPSPI_PARAM_TXFIFO_SHIFT));
542 }
543
544 /*!
545 * @brief Gets the LPSPI Rx FIFO size.
546 * @param base LPSPI peripheral address.
547 * @return The LPSPI Rx FIFO size.
548 */
LPSPI_GetRxFifoSize(LPSPI_Type * base)549 static inline uint8_t LPSPI_GetRxFifoSize(LPSPI_Type *base)
550 {
551 return (1U << ((base->PARAM & LPSPI_PARAM_RXFIFO_MASK) >> LPSPI_PARAM_RXFIFO_SHIFT));
552 }
553
554 /*!
555 * @brief Gets the LPSPI Tx FIFO count.
556 * @param base LPSPI peripheral address.
557 * @return The number of words in the transmit FIFO.
558 */
LPSPI_GetTxFifoCount(LPSPI_Type * base)559 static inline uint32_t LPSPI_GetTxFifoCount(LPSPI_Type *base)
560 {
561 return ((base->FSR & LPSPI_FSR_TXCOUNT_MASK) >> LPSPI_FSR_TXCOUNT_SHIFT);
562 }
563
564 /*!
565 * @brief Gets the LPSPI Rx FIFO count.
566 * @param base LPSPI peripheral address.
567 * @return The number of words in the receive FIFO.
568 */
LPSPI_GetRxFifoCount(LPSPI_Type * base)569 static inline uint32_t LPSPI_GetRxFifoCount(LPSPI_Type *base)
570 {
571 return ((base->FSR & LPSPI_FSR_RXCOUNT_MASK) >> LPSPI_FSR_RXCOUNT_SHIFT);
572 }
573
574 /*!
575 * @brief Clears the LPSPI status flag.
576 *
577 * This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the
578 * desired status flag bit to clear. The list of status flags is defined in the _lpspi_flags.
579 * Example usage:
580 * @code
581 * LPSPI_ClearStatusFlags(base, kLPSPI_TxDataRequestFlag|kLPSPI_RxDataReadyFlag);
582 * @endcode
583 *
584 * @param base LPSPI peripheral address.
585 * @param statusFlags The status flag used from type _lpspi_flags.
586 */
LPSPI_ClearStatusFlags(LPSPI_Type * base,uint32_t statusFlags)587 static inline void LPSPI_ClearStatusFlags(LPSPI_Type *base, uint32_t statusFlags)
588 {
589 base->SR = statusFlags; /*!< The status flags are cleared by writing 1 (w1c).*/
590 }
591
592 /*!
593 *@}
594 */
595
596 /*!
597 * @name Interrupts
598 * @{
599 */
600
601 /*!
602 * @brief Enables the LPSPI interrupts.
603 *
604 * This function configures the various interrupt masks of the LPSPI. The parameters are base and an interrupt mask.
605 * Note that, for Tx fill and Rx FIFO drain requests, enabling the interrupt request disables the DMA request.
606 *
607 * @code
608 * LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable );
609 * @endcode
610 *
611 * @param base LPSPI peripheral address.
612 * @param mask The interrupt mask; Use the enum _lpspi_interrupt_enable.
613 */
LPSPI_EnableInterrupts(LPSPI_Type * base,uint32_t mask)614 static inline void LPSPI_EnableInterrupts(LPSPI_Type *base, uint32_t mask)
615 {
616 base->IER |= mask;
617 }
618
619 /*!
620 * @brief Disables the LPSPI interrupts.
621 *
622 * @code
623 * LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable );
624 * @endcode
625 *
626 * @param base LPSPI peripheral address.
627 * @param mask The interrupt mask; Use the enum _lpspi_interrupt_enable.
628 */
LPSPI_DisableInterrupts(LPSPI_Type * base,uint32_t mask)629 static inline void LPSPI_DisableInterrupts(LPSPI_Type *base, uint32_t mask)
630 {
631 base->IER &= ~mask;
632 }
633
634 /*!
635 *@}
636 */
637
638 /*!
639 * @name DMA Control
640 * @{
641 */
642
643 /*!
644 * @brief Enables the LPSPI DMA request.
645 *
646 * This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask.
647 * @code
648 * LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);
649 * @endcode
650 *
651 * @param base LPSPI peripheral address.
652 * @param mask The interrupt mask; Use the enum _lpspi_dma_enable.
653 */
LPSPI_EnableDMA(LPSPI_Type * base,uint32_t mask)654 static inline void LPSPI_EnableDMA(LPSPI_Type *base, uint32_t mask)
655 {
656 base->DER |= mask;
657 }
658
659 /*!
660 * @brief Disables the LPSPI DMA request.
661 *
662 * This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask.
663 * @code
664 * SPI_DisableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);
665 * @endcode
666 *
667 * @param base LPSPI peripheral address.
668 * @param mask The interrupt mask; Use the enum _lpspi_dma_enable.
669 */
LPSPI_DisableDMA(LPSPI_Type * base,uint32_t mask)670 static inline void LPSPI_DisableDMA(LPSPI_Type *base, uint32_t mask)
671 {
672 base->DER &= ~mask;
673 }
674
675 /*!
676 * @brief Gets the LPSPI Transmit Data Register address for a DMA operation.
677 *
678 * This function gets the LPSPI Transmit Data Register address because this value is needed
679 * for the DMA operation.
680 * This function can be used for either master or slave mode.
681 *
682 * @param base LPSPI peripheral address.
683 * @return The LPSPI Transmit Data Register address.
684 */
LPSPI_GetTxRegisterAddress(LPSPI_Type * base)685 static inline uint32_t LPSPI_GetTxRegisterAddress(LPSPI_Type *base)
686 {
687 return (uint32_t) & (base->TDR);
688 }
689
690 /*!
691 * @brief Gets the LPSPI Receive Data Register address for a DMA operation.
692 *
693 * This function gets the LPSPI Receive Data Register address because this value is needed
694 * for the DMA operation.
695 * This function can be used for either master or slave mode.
696 *
697 * @param base LPSPI peripheral address.
698 * @return The LPSPI Receive Data Register address.
699 */
LPSPI_GetRxRegisterAddress(LPSPI_Type * base)700 static inline uint32_t LPSPI_GetRxRegisterAddress(LPSPI_Type *base)
701 {
702 return (uint32_t) & (base->RDR);
703 }
704
705 /*!
706 *@}
707 */
708
709 /*!
710 * @name Bus Operations
711 * @{
712 */
713
714 /*!
715 * @brief Check the argument for transfer .
716 *
717 * @param transfer the transfer struct to be used.
718 * @param bitsPerFrame The bit size of one frame.
719 * @param bytesPerFrame The byte size of one frame.
720 * @return Return true for right and false for wrong.
721 */
722 bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFrame, uint32_t bytesPerFrame);
723
724 /*!
725 * @brief Configures the LPSPI for either master or slave.
726 *
727 * Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0).
728 *
729 * @param base LPSPI peripheral address.
730 * @param mode Mode setting (master or slave) of type lpspi_master_slave_mode_t.
731 */
LPSPI_SetMasterSlaveMode(LPSPI_Type * base,lpspi_master_slave_mode_t mode)732 static inline void LPSPI_SetMasterSlaveMode(LPSPI_Type *base, lpspi_master_slave_mode_t mode)
733 {
734 base->CFGR1 = (base->CFGR1 & (~LPSPI_CFGR1_MASTER_MASK)) | LPSPI_CFGR1_MASTER(mode);
735 }
736
737 /*!
738 * @brief Returns whether the LPSPI module is in master mode.
739 *
740 * @param base LPSPI peripheral address.
741 * @return Returns true if the module is in master mode or false if the module is in slave mode.
742 */
LPSPI_IsMaster(LPSPI_Type * base)743 static inline bool LPSPI_IsMaster(LPSPI_Type *base)
744 {
745 return (bool)((base->CFGR1) & LPSPI_CFGR1_MASTER_MASK);
746 }
747
748 /*!
749 * @brief Flushes the LPSPI FIFOs.
750 *
751 * @param base LPSPI peripheral address.
752 * @param flushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO.
753 * @param flushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO.
754 */
LPSPI_FlushFifo(LPSPI_Type * base,bool flushTxFifo,bool flushRxFifo)755 static inline void LPSPI_FlushFifo(LPSPI_Type *base, bool flushTxFifo, bool flushRxFifo)
756 {
757 base->CR |= ((uint32_t)flushTxFifo << LPSPI_CR_RTF_SHIFT) | ((uint32_t)flushRxFifo << LPSPI_CR_RRF_SHIFT);
758 }
759
760 /*!
761 * @brief Sets the transmit and receive FIFO watermark values.
762 *
763 * This function allows the user to set the receive and transmit FIFO watermarks. The function
764 * does not compare the watermark settings to the FIFO size. The FIFO watermark should not be
765 * equal to or greater than the FIFO size. It is up to the higher level driver to make this check.
766 *
767 * @param base LPSPI peripheral address.
768 * @param txWater The TX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated.
769 * @param rxWater The RX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated.
770 */
LPSPI_SetFifoWatermarks(LPSPI_Type * base,uint32_t txWater,uint32_t rxWater)771 static inline void LPSPI_SetFifoWatermarks(LPSPI_Type *base, uint32_t txWater, uint32_t rxWater)
772 {
773 base->FCR = LPSPI_FCR_TXWATER(txWater) | LPSPI_FCR_RXWATER(rxWater);
774 }
775
776 /*!
777 * @brief Configures all LPSPI peripheral chip select polarities simultaneously.
778 *
779 * Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0).
780 *
781 * This is an example: PCS0 and PCS1 set to active low and other PCSs set to active high. Note that the number of
782 * PCS is device-specific.
783 * @code
784 * LPSPI_SetAllPcsPolarity(base, kLPSPI_Pcs0ActiveLow | kLPSPI_Pcs1ActiveLow);
785 * @endcode
786 *
787 * @param base LPSPI peripheral address.
788 * @param mask The PCS polarity mask; Use the enum _lpspi_pcs_polarity.
789 */
LPSPI_SetAllPcsPolarity(LPSPI_Type * base,uint32_t mask)790 static inline void LPSPI_SetAllPcsPolarity(LPSPI_Type *base, uint32_t mask)
791 {
792 base->CFGR1 = (base->CFGR1 & ~LPSPI_CFGR1_PCSPOL_MASK) | LPSPI_CFGR1_PCSPOL(~mask);
793 }
794
795 /*!
796 * @brief Configures the frame size.
797 *
798 * The minimum frame size is 8-bits and the maximum frame size is 4096-bits. If the frame size is less than or equal
799 * to 32-bits, the word size and frame size are identical. If the frame size is greater than 32-bits, the word
800 * size is 32-bits for each word except the last (the last word contains the remainder bits if the frame size is not
801 * divisible by 32). The minimum word size is 2-bits. A frame size of 33-bits (or similar) is not supported.
802 *
803 * Note 1: The transmit command register should be initialized before enabling the LPSPI in slave mode, although
804 * the command register does not update until after the LPSPI is enabled. After it is enabled, the transmit command
805 * register
806 * should only be changed if the LPSPI is idle.
807 *
808 * Note 2: The transmit and command FIFO is a combined FIFO that includes both transmit data and command words. That
809 * means the TCR register should be written to when the Tx FIFO is not full.
810 *
811 * @param base LPSPI peripheral address.
812 * @param frameSize The frame size in number of bits.
813 */
LPSPI_SetFrameSize(LPSPI_Type * base,uint32_t frameSize)814 static inline void LPSPI_SetFrameSize(LPSPI_Type *base, uint32_t frameSize)
815 {
816 base->TCR = (base->TCR & ~LPSPI_TCR_FRAMESZ_MASK) | LPSPI_TCR_FRAMESZ(frameSize - 1U);
817 }
818
819 /*!
820 * @brief Sets the LPSPI baud rate in bits per second.
821 *
822 * This function takes in the desired bitsPerSec (baud rate) and calculates the nearest
823 * possible baud rate without exceeding the desired baud rate and returns the
824 * calculated baud rate in bits-per-second. It requires the caller to provide
825 * the frequency of the module source clock (in Hertz). Note that the baud rate
826 * does not go into effect until the Transmit Control Register (TCR) is programmed
827 * with the prescale value. Hence, this function returns the prescale tcrPrescaleValue
828 * parameter for later programming in the TCR. The higher level
829 * peripheral driver should alert the user of an out of range baud rate input.
830 *
831 * Note that the LPSPI module must first be disabled before configuring this.
832 * Note that the LPSPI module must be configured for master mode before configuring this.
833 *
834 * @param base LPSPI peripheral address.
835 * @param baudRate_Bps The desired baud rate in bits per second.
836 * @param srcClock_Hz Module source input clock in Hertz.
837 * @param tcrPrescaleValue The TCR prescale value needed to program the TCR.
838 * @return The actual calculated baud rate. This function may also return a "0" if the
839 * LPSPI is not configured for master mode or if the LPSPI module is not disabled.
840 */
841
842 uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base,
843 uint32_t baudRate_Bps,
844 uint32_t srcClock_Hz,
845 uint32_t *tcrPrescaleValue);
846
847 /*!
848 * @brief Manually configures a specific LPSPI delay parameter (module must be disabled to
849 * change the delay values).
850 *
851 * This function configures the following:
852 * SCK to PCS delay, or
853 * PCS to SCK delay, or
854 * The configurations must occur between the transfer delay.
855 *
856 * The delay names are available in type lpspi_delay_type_t.
857 *
858 * The user passes the desired delay along with the delay value.
859 * This allows the user to directly set the delay values if they have
860 * pre-calculated them or if they simply wish to manually increment the value.
861 *
862 * Note that the LPSPI module must first be disabled before configuring this.
863 * Note that the LPSPI module must be configured for master mode before configuring this.
864 *
865 * @param base LPSPI peripheral address.
866 * @param scaler The 8-bit delay value 0x00 to 0xFF (255).
867 * @param whichDelay The desired delay to configure, must be of type lpspi_delay_type_t.
868 */
869 void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay);
870
871 /*!
872 * @brief Calculates the delay based on the desired delay input in nanoseconds (module must be
873 * disabled to change the delay values).
874 *
875 * This function calculates the values for the following:
876 * SCK to PCS delay, or
877 * PCS to SCK delay, or
878 * The configurations must occur between the transfer delay.
879 *
880 * The delay names are available in type lpspi_delay_type_t.
881 *
882 * The user passes the desired delay and the desired delay value in
883 * nano-seconds. The function calculates the value needed for the desired delay parameter
884 * and returns the actual calculated delay because an exact delay match may not be possible. In this
885 * case, the closest match is calculated without going below the desired delay value input.
886 * It is possible to input a very large delay value that exceeds the capability of the part, in
887 * which case the maximum supported delay is returned. It is up to the higher level
888 * peripheral driver to alert the user of an out of range delay input.
889 *
890 * Note that the LPSPI module must be configured for master mode before configuring this. And note that
891 * the delayTime = LPSPI_clockSource / (PRESCALE * Delay_scaler).
892 *
893 * @param base LPSPI peripheral address.
894 * @param delayTimeInNanoSec The desired delay value in nano-seconds.
895 * @param whichDelay The desired delay to configuration, which must be of type lpspi_delay_type_t.
896 * @param srcClock_Hz Module source input clock in Hertz.
897 * @return actual Calculated delay value in nano-seconds.
898 */
899 uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base,
900 uint32_t delayTimeInNanoSec,
901 lpspi_delay_type_t whichDelay,
902 uint32_t srcClock_Hz);
903
904 /*!
905 * @brief Writes data into the transmit data buffer.
906 *
907 * This function writes data passed in by the user to the Transmit Data Register (TDR).
908 * The user can pass up to 32-bits of data to load into the TDR. If the frame size exceeds 32-bits,
909 * the user has to manage sending the data one 32-bit word at a time.
910 * Any writes to the TDR result in an immediate push to the transmit FIFO.
911 * This function can be used for either master or slave modes.
912 *
913 * @param base LPSPI peripheral address.
914 * @param data The data word to be sent.
915 */
LPSPI_WriteData(LPSPI_Type * base,uint32_t data)916 static inline void LPSPI_WriteData(LPSPI_Type *base, uint32_t data)
917 {
918 base->TDR = data;
919 }
920
921 /*!
922 * @brief Reads data from the data buffer.
923 *
924 * This function reads the data from the Receive Data Register (RDR).
925 * This function can be used for either master or slave mode.
926 *
927 * @param base LPSPI peripheral address.
928 * @return The data read from the data buffer.
929 */
LPSPI_ReadData(LPSPI_Type * base)930 static inline uint32_t LPSPI_ReadData(LPSPI_Type *base)
931 {
932 return (base->RDR);
933 }
934
935 /*!
936 * @brief Set up the dummy data.
937 *
938 * @param base LPSPI peripheral address.
939 * @param dummyData Data to be transferred when tx buffer is NULL.
940 * Note:
941 * This API has no effect when LPSPI in slave interrupt mode, because driver
942 * will set the TXMSK bit to 1 if txData is NULL, no data is loaded from transmit
943 * FIFO and output pin is tristated.
944 */
945 void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData);
946
947 /*!
948 *@}
949 */
950
951 /*!
952 * @name Transactional
953 * @{
954 */
955 /*Transactional APIs*/
956
957 /*!
958 * @brief Initializes the LPSPI master handle.
959 *
960 * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a
961 * specified LPSPI instance, call this API once to get the initialized handle.
962
963 * @param base LPSPI peripheral address.
964 * @param handle LPSPI handle pointer to lpspi_master_handle_t.
965 * @param callback DSPI callback.
966 * @param userData callback function parameter.
967 */
968 void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base,
969 lpspi_master_handle_t *handle,
970 lpspi_master_transfer_callback_t callback,
971 void *userData);
972
973 /*!
974 * @brief LPSPI master transfer data using a polling method.
975 *
976 * This function transfers data using a polling method. This is a blocking function, which does not return until all
977 * transfers have been
978 * completed.
979 *
980 * Note:
981 * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4.
982 * For bytesPerFrame greater than 4:
983 * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4.
984 * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
985 *
986 * @param base LPSPI peripheral address.
987 * @param transfer pointer to lpspi_transfer_t structure.
988 * @return status of status_t.
989 */
990 status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer);
991
992 /*!
993 * @brief LPSPI master transfer data using an interrupt method.
994 *
995 * This function transfers data using an interrupt method. This is a non-blocking function, which returns right away.
996 * When all data
997 * is transferred, the callback function is called.
998 *
999 * Note:
1000 * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4.
1001 * For bytesPerFrame greater than 4:
1002 * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4.
1003 * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
1004 *
1005 * @param base LPSPI peripheral address.
1006 * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state.
1007 * @param transfer pointer to lpspi_transfer_t structure.
1008 * @return status of status_t.
1009 */
1010 status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer);
1011
1012 /*!
1013 * @brief Gets the master transfer remaining bytes.
1014 *
1015 * This function gets the master transfer remaining bytes.
1016 *
1017 * @param base LPSPI peripheral address.
1018 * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state.
1019 * @param count Number of bytes transferred so far by the non-blocking transaction.
1020 * @return status of status_t.
1021 */
1022 status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count);
1023
1024 /*!
1025 * @brief LPSPI master abort transfer which uses an interrupt method.
1026 *
1027 * This function aborts a transfer which uses an interrupt method.
1028 *
1029 * @param base LPSPI peripheral address.
1030 * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state.
1031 */
1032 void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle);
1033
1034 /*!
1035 * @brief LPSPI Master IRQ handler function.
1036 *
1037 * This function processes the LPSPI transmit and receive IRQ.
1038 *
1039 * @param base LPSPI peripheral address.
1040 * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state.
1041 */
1042 void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *handle);
1043
1044 /*!
1045 * @brief Initializes the LPSPI slave handle.
1046 *
1047 * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a
1048 * specified LPSPI instance, call this API once to get the initialized handle.
1049 *
1050 * @param base LPSPI peripheral address.
1051 * @param handle LPSPI handle pointer to lpspi_slave_handle_t.
1052 * @param callback DSPI callback.
1053 * @param userData callback function parameter.
1054 */
1055 void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base,
1056 lpspi_slave_handle_t *handle,
1057 lpspi_slave_transfer_callback_t callback,
1058 void *userData);
1059
1060 /*!
1061 * @brief LPSPI slave transfer data using an interrupt method.
1062 *
1063 * This function transfer data using an interrupt method. This is a non-blocking function, which returns right away.
1064 * When all data
1065 * is transferred, the callback function is called.
1066 *
1067 * Note:
1068 * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4.
1069 * For bytesPerFrame greater than 4:
1070 * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4.
1071 * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
1072 *
1073 * @param base LPSPI peripheral address.
1074 * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state.
1075 * @param transfer pointer to lpspi_transfer_t structure.
1076 * @return status of status_t.
1077 */
1078 status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer);
1079
1080 /*!
1081 * @brief Gets the slave transfer remaining bytes.
1082 *
1083 * This function gets the slave transfer remaining bytes.
1084 *
1085 * @param base LPSPI peripheral address.
1086 * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state.
1087 * @param count Number of bytes transferred so far by the non-blocking transaction.
1088 * @return status of status_t.
1089 */
1090 status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count);
1091
1092 /*!
1093 * @brief LPSPI slave aborts a transfer which uses an interrupt method.
1094 *
1095 * This function aborts a transfer which uses an interrupt method.
1096 *
1097 * @param base LPSPI peripheral address.
1098 * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state.
1099 */
1100 void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle);
1101
1102 /*!
1103 * @brief LPSPI Slave IRQ handler function.
1104 *
1105 * This function processes the LPSPI transmit and receives an IRQ.
1106 *
1107 * @param base LPSPI peripheral address.
1108 * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state.
1109 */
1110 void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle);
1111
1112 /*!
1113 *@}
1114 */
1115
1116 #if defined(__cplusplus)
1117 }
1118 #endif
1119
1120 /*! @}*/
1121
1122 #endif /*_FSL_LPSPI_H_*/
1123
