1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2020,2021 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #ifndef _FSL_LPSPI_H_
9 #define _FSL_LPSPI_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup lpspi_driver
15 * @{
16 */
17
18 /**********************************************************************************************************************
19 * Definitions
20 *********************************************************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 /*! @brief LPSPI driver version. */
25 #define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
26 /*@}*/
27
28 #ifndef LPSPI_DUMMY_DATA
29 /*! @brief LPSPI dummy data if no Tx data.*/
30 #define LPSPI_DUMMY_DATA (0x00U) /*!< Dummy data used for tx if there is not txData. */
31 #endif
32
33 /*! @brief Retry times for waiting flag. */
34 #ifndef SPI_RETRY_TIMES
35 #define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */
36 #endif
37
38 /*! @brief Global variable for dummy data value setting. */
39 extern volatile uint8_t g_lpspiDummyData[];
40
41 /*! @brief Status for the LPSPI driver.*/
42 enum
43 {
44 kStatus_LPSPI_Busy = MAKE_STATUS(kStatusGroup_LPSPI, 0), /*!< LPSPI transfer is busy.*/
45 kStatus_LPSPI_Error = MAKE_STATUS(kStatusGroup_LPSPI, 1), /*!< LPSPI driver error. */
46 kStatus_LPSPI_Idle = MAKE_STATUS(kStatusGroup_LPSPI, 2), /*!< LPSPI is idle.*/
47 kStatus_LPSPI_OutOfRange = MAKE_STATUS(kStatusGroup_LPSPI, 3), /*!< LPSPI transfer out Of range. */
48 kStatus_LPSPI_Timeout = MAKE_STATUS(kStatusGroup_LPSPI, 4) /*!< LPSPI timeout polling status flags. */
49 };
50
51 /*! @brief LPSPI status flags in SPIx_SR register.*/
52 enum _lpspi_flags
53 {
54 kLPSPI_TxDataRequestFlag = LPSPI_SR_TDF_MASK, /*!< Transmit data flag */
55 kLPSPI_RxDataReadyFlag = LPSPI_SR_RDF_MASK, /*!< Receive data flag */
56 kLPSPI_WordCompleteFlag = LPSPI_SR_WCF_MASK, /*!< Word Complete flag */
57 kLPSPI_FrameCompleteFlag = LPSPI_SR_FCF_MASK, /*!< Frame Complete flag */
58 kLPSPI_TransferCompleteFlag = LPSPI_SR_TCF_MASK, /*!< Transfer Complete flag */
59 kLPSPI_TransmitErrorFlag = LPSPI_SR_TEF_MASK, /*!< Transmit Error flag (FIFO underrun) */
60 kLPSPI_ReceiveErrorFlag = LPSPI_SR_REF_MASK, /*!< Receive Error flag (FIFO overrun) */
61 kLPSPI_DataMatchFlag = LPSPI_SR_DMF_MASK, /*!< Data Match flag */
62 kLPSPI_ModuleBusyFlag = LPSPI_SR_MBF_MASK, /*!< Module Busy flag */
63 kLPSPI_AllStatusFlag = (LPSPI_SR_TDF_MASK | LPSPI_SR_RDF_MASK | LPSPI_SR_WCF_MASK | LPSPI_SR_FCF_MASK |
64 LPSPI_SR_TCF_MASK | LPSPI_SR_TEF_MASK | LPSPI_SR_REF_MASK | LPSPI_SR_DMF_MASK |
65 LPSPI_SR_MBF_MASK) /*!< Used for clearing all w1c status flags */
66 };
67
68 /*! @brief LPSPI interrupt source.*/
69 enum _lpspi_interrupt_enable
70 {
71 kLPSPI_TxInterruptEnable = LPSPI_IER_TDIE_MASK, /*!< Transmit data interrupt enable */
72 kLPSPI_RxInterruptEnable = LPSPI_IER_RDIE_MASK, /*!< Receive data interrupt enable */
73 kLPSPI_WordCompleteInterruptEnable = LPSPI_IER_WCIE_MASK, /*!< Word complete interrupt enable */
74 kLPSPI_FrameCompleteInterruptEnable = LPSPI_IER_FCIE_MASK, /*!< Frame complete interrupt enable */
75 kLPSPI_TransferCompleteInterruptEnable = LPSPI_IER_TCIE_MASK, /*!< Transfer complete interrupt enable */
76 kLPSPI_TransmitErrorInterruptEnable = LPSPI_IER_TEIE_MASK, /*!< Transmit error interrupt enable(FIFO underrun)*/
77 kLPSPI_ReceiveErrorInterruptEnable = LPSPI_IER_REIE_MASK, /*!< Receive Error interrupt enable (FIFO overrun) */
78 kLPSPI_DataMatchInterruptEnable = LPSPI_IER_DMIE_MASK, /*!< Data Match interrupt enable */
79 kLPSPI_AllInterruptEnable =
80 (LPSPI_IER_TDIE_MASK | LPSPI_IER_RDIE_MASK | LPSPI_IER_WCIE_MASK | LPSPI_IER_FCIE_MASK | LPSPI_IER_TCIE_MASK |
81 LPSPI_IER_TEIE_MASK | LPSPI_IER_REIE_MASK | LPSPI_IER_DMIE_MASK) /*!< All above interrupts enable.*/
82 };
83
84 /*! @brief LPSPI DMA source.*/
85 enum _lpspi_dma_enable
86 {
87 kLPSPI_TxDmaEnable = LPSPI_DER_TDDE_MASK, /*!< Transmit data DMA enable */
88 kLPSPI_RxDmaEnable = LPSPI_DER_RDDE_MASK /*!< Receive data DMA enable */
89 };
90
91 /*! @brief LPSPI master or slave mode configuration.*/
92 typedef enum _lpspi_master_slave_mode
93 {
94 kLPSPI_Master = 1U, /*!< LPSPI peripheral operates in master mode.*/
95 kLPSPI_Slave = 0U /*!< LPSPI peripheral operates in slave mode.*/
96 } lpspi_master_slave_mode_t;
97
98 /*! @brief LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).*/
99 typedef enum _lpspi_which_pcs_config
100 {
101 kLPSPI_Pcs0 = 0U, /*!< PCS[0] */
102 kLPSPI_Pcs1 = 1U, /*!< PCS[1] */
103 kLPSPI_Pcs2 = 2U, /*!< PCS[2] */
104 kLPSPI_Pcs3 = 3U /*!< PCS[3] */
105 } lpspi_which_pcs_t;
106
107 /*! @brief LPSPI Peripheral Chip Select (PCS) Polarity configuration.*/
108 typedef enum _lpspi_pcs_polarity_config
109 {
110 kLPSPI_PcsActiveHigh = 1U, /*!< PCS Active High (idles low) */
111 kLPSPI_PcsActiveLow = 0U /*!< PCS Active Low (idles high) */
112 } lpspi_pcs_polarity_config_t;
113
114 /*! @brief LPSPI Peripheral Chip Select (PCS) Polarity.*/
115 enum _lpspi_pcs_polarity
116 {
117 kLPSPI_Pcs0ActiveLow = 1U << 0, /*!< Pcs0 Active Low (idles high). */
118 kLPSPI_Pcs1ActiveLow = 1U << 1, /*!< Pcs1 Active Low (idles high). */
119 kLPSPI_Pcs2ActiveLow = 1U << 2, /*!< Pcs2 Active Low (idles high). */
120 kLPSPI_Pcs3ActiveLow = 1U << 3, /*!< Pcs3 Active Low (idles high). */
121 kLPSPI_PcsAllActiveLow = 0xFU /*!< Pcs0 to Pcs5 Active Low (idles high). */
122 };
123
124 /*! @brief LPSPI clock polarity configuration.*/
125 typedef enum _lpspi_clock_polarity
126 {
127 kLPSPI_ClockPolarityActiveHigh = 0U, /*!< CPOL=0. Active-high LPSPI clock (idles low)*/
128 kLPSPI_ClockPolarityActiveLow = 1U /*!< CPOL=1. Active-low LPSPI clock (idles high)*/
129 } lpspi_clock_polarity_t;
130
131 /*! @brief LPSPI clock phase configuration.*/
132 typedef enum _lpspi_clock_phase
133 {
134 kLPSPI_ClockPhaseFirstEdge = 0U, /*!< CPHA=0. Data is captured on the leading edge of the SCK and changed on the
135 following edge.*/
136 kLPSPI_ClockPhaseSecondEdge = 1U /*!< CPHA=1. Data is changed on the leading edge of the SCK and captured on the
137 following edge.*/
138 } lpspi_clock_phase_t;
139
140 /*! @brief LPSPI data shifter direction options.*/
141 typedef enum _lpspi_shift_direction
142 {
143 kLPSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit.*/
144 kLPSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit.*/
145 } lpspi_shift_direction_t;
146
147 /*! @brief LPSPI Host Request select configuration. */
148 typedef enum _lpspi_host_request_select
149 {
150 kLPSPI_HostReqExtPin = 0U, /*!< Host Request is an ext pin. */
151 kLPSPI_HostReqInternalTrigger = 1U /*!< Host Request is an internal trigger. */
152 } lpspi_host_request_select_t;
153
154 /*! @brief LPSPI Match configuration options. */
155 typedef enum _lpspi_match_config
156 {
157 kLPSI_MatchDisabled = 0x0U, /*!< LPSPI Match Disabled. */
158 kLPSI_1stWordEqualsM0orM1 = 0x2U, /*!< LPSPI Match Enabled. */
159 kLPSI_AnyWordEqualsM0orM1 = 0x3U, /*!< LPSPI Match Enabled. */
160 kLPSI_1stWordEqualsM0and2ndWordEqualsM1 = 0x4U, /*!< LPSPI Match Enabled. */
161 kLPSI_AnyWordEqualsM0andNxtWordEqualsM1 = 0x5U, /*!< LPSPI Match Enabled. */
162 kLPSI_1stWordAndM1EqualsM0andM1 = 0x6U, /*!< LPSPI Match Enabled. */
163 kLPSI_AnyWordAndM1EqualsM0andM1 = 0x7U, /*!< LPSPI Match Enabled. */
164 } lpspi_match_config_t;
165
166 /*! @brief LPSPI pin (SDO and SDI) configuration. */
167 typedef enum _lpspi_pin_config
168 {
169 kLPSPI_SdiInSdoOut = 0U, /*!< LPSPI SDI input, SDO output. */
170 kLPSPI_SdiInSdiOut = 1U, /*!< LPSPI SDI input, SDI output. */
171 kLPSPI_SdoInSdoOut = 2U, /*!< LPSPI SDO input, SDO output. */
172 kLPSPI_SdoInSdiOut = 3U /*!< LPSPI SDO input, SDI output. */
173 } lpspi_pin_config_t;
174
175 /*! @brief LPSPI data output configuration. */
176 typedef enum _lpspi_data_out_config
177 {
178 kLpspiDataOutRetained = 0U, /*!< Data out retains last value when chip select is de-asserted */
179 kLpspiDataOutTristate = 1U /*!< Data out is tristated when chip select is de-asserted */
180 } lpspi_data_out_config_t;
181
182 /*! @brief LPSPI transfer width configuration. */
183 typedef enum _lpspi_transfer_width
184 {
185 kLPSPI_SingleBitXfer = 0U, /*!< 1-bit shift at a time, data out on SDO, in on SDI (normal mode) */
186 kLPSPI_TwoBitXfer = 1U, /*!< 2-bits shift out on SDO/SDI and in on SDO/SDI */
187 kLPSPI_FourBitXfer = 2U /*!< 4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2] */
188 } lpspi_transfer_width_t;
189
190 /*! @brief LPSPI delay type selection.*/
191 typedef enum _lpspi_delay_type
192 {
193 kLPSPI_PcsToSck = 1U, /*!< PCS-to-SCK delay. */
194 kLPSPI_LastSckToPcs, /*!< Last SCK edge to PCS delay. */
195 kLPSPI_BetweenTransfer /*!< Delay between transfers. */
196 } lpspi_delay_type_t;
197
198 #define LPSPI_MASTER_PCS_SHIFT (4U) /*!< LPSPI master PCS shift macro , internal used. */
199 #define LPSPI_MASTER_PCS_MASK (0xF0U) /*!< LPSPI master PCS shift macro , internal used. */
200
201 /*! @brief Use this enumeration for LPSPI master transfer configFlags. */
202 enum _lpspi_transfer_config_flag_for_master
203 {
204 kLPSPI_MasterPcs0 = 0U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS0 signal */
205 kLPSPI_MasterPcs1 = 1U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS1 signal */
206 kLPSPI_MasterPcs2 = 2U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS2 signal */
207 kLPSPI_MasterPcs3 = 3U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS3 signal */
208
209 kLPSPI_MasterPcsContinuous = 1U << 20, /*!< Is PCS signal continuous */
210
211 kLPSPI_MasterByteSwap =
212 1U << 22 /*!< Is master swap the byte.
213 * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set
214 * lpspi_shift_direction_t to MSB).
215 * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used
216 * or not, the waveform is 1 2 3 4 5 6 7 8.
217 * 2. If you set bitPerFrame = 16 :
218 * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag.
219 * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.
220 * 3. If you set bitPerFrame = 32 :
221 * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag.
222 * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.
223 */
224 };
225
226 #define LPSPI_SLAVE_PCS_SHIFT (4U) /*!< LPSPI slave PCS shift macro , internal used. */
227 #define LPSPI_SLAVE_PCS_MASK (0xF0U) /*!< LPSPI slave PCS shift macro , internal used. */
228
229 /*! @brief Use this enumeration for LPSPI slave transfer configFlags. */
230 enum _lpspi_transfer_config_flag_for_slave
231 {
232 kLPSPI_SlavePcs0 = 0U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS0 signal */
233 kLPSPI_SlavePcs1 = 1U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS1 signal */
234 kLPSPI_SlavePcs2 = 2U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS2 signal */
235 kLPSPI_SlavePcs3 = 3U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS3 signal */
236
237 kLPSPI_SlaveByteSwap =
238 1U << 22 /*!< Is slave swap the byte.
239 * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set
240 * lpspi_shift_direction_t to MSB).
241 * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used
242 * or not, the waveform is 1 2 3 4 5 6 7 8.
243 * 2. If you set bitPerFrame = 16 :
244 * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag.
245 * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.
246 * 3. If you set bitPerFrame = 32 :
247 * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag.
248 * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.
249 */
250 };
251
252 /*! @brief LPSPI transfer state, which is used for LPSPI transactional API state machine. */
253 enum _lpspi_transfer_state
254 {
255 kLPSPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver. */
256 kLPSPI_Busy, /*!< Transfer queue is not finished. */
257 kLPSPI_Error /*!< Transfer error. */
258 };
259
260 /*! @brief LPSPI master configuration structure.*/
261 typedef struct _lpspi_master_config
262 {
263 uint32_t baudRate; /*!< Baud Rate for LPSPI. */
264 uint32_t bitsPerFrame; /*!< Bits per frame, minimum 8, maximum 4096.*/
265 lpspi_clock_polarity_t cpol; /*!< Clock polarity. */
266 lpspi_clock_phase_t cpha; /*!< Clock phase. */
267 lpspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */
268
269 uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time in nanoseconds, setting to 0 sets the minimum delay.
270 It sets the boundary value if out of range.*/
271 uint32_t lastSckToPcsDelayInNanoSec; /*!< Last SCK to PCS delay time in nanoseconds, setting to 0 sets the minimum
272 delay. It sets the boundary value if out of range.*/
273 uint32_t betweenTransferDelayInNanoSec; /*!< After the SCK delay time with nanoseconds, setting to 0 sets the
274 minimum delay. It sets the boundary value if out of range.*/
275
276 lpspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (PCS). */
277 lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low */
278
279 lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data
280 *during single bit transfers.*/
281
282 lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated
283 * between accesses (LPSPI_PCS is negated). */
284 } lpspi_master_config_t;
285
286 /*! @brief LPSPI slave configuration structure.*/
287 typedef struct _lpspi_slave_config
288 {
289 uint32_t bitsPerFrame; /*!< Bits per frame, minimum 8, maximum 4096.*/
290 lpspi_clock_polarity_t cpol; /*!< Clock polarity. */
291 lpspi_clock_phase_t cpha; /*!< Clock phase. */
292 lpspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */
293
294 lpspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (pcs) */
295 lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low */
296
297 lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data
298 *during single bit transfers.*/
299
300 lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated
301 * between accesses (LPSPI_PCS is negated). */
302 } lpspi_slave_config_t;
303
304 /*!
305 * @brief Forward declaration of the _lpspi_master_handle typedefs.
306 */
307 typedef struct _lpspi_master_handle lpspi_master_handle_t;
308
309 /*!
310 * @brief Forward declaration of the _lpspi_slave_handle typedefs.
311 */
312 typedef struct _lpspi_slave_handle lpspi_slave_handle_t;
313
314 /*!
315 * @brief Master completion callback function pointer type.
316 *
317 * @param base LPSPI peripheral address.
318 * @param handle Pointer to the handle for the LPSPI master.
319 * @param status Success or error code describing whether the transfer is completed.
320 * @param userData Arbitrary pointer-dataSized value passed from the application.
321 */
322 typedef void (*lpspi_master_transfer_callback_t)(LPSPI_Type *base,
323 lpspi_master_handle_t *handle,
324 status_t status,
325 void *userData);
326
327 /*!
328 * @brief Slave completion callback function pointer type.
329 *
330 * @param base LPSPI peripheral address.
331 * @param handle Pointer to the handle for the LPSPI slave.
332 * @param status Success or error code describing whether the transfer is completed.
333 * @param userData Arbitrary pointer-dataSized value passed from the application.
334 */
335 typedef void (*lpspi_slave_transfer_callback_t)(LPSPI_Type *base,
336 lpspi_slave_handle_t *handle,
337 status_t status,
338 void *userData);
339
340 /*! @brief LPSPI master/slave transfer structure.*/
341 typedef struct _lpspi_transfer
342 {
343 uint8_t *txData; /*!< Send buffer. */
344 uint8_t *rxData; /*!< Receive buffer. */
345 volatile size_t dataSize; /*!< Transfer bytes. */
346
347 uint32_t configFlags; /*!< Transfer transfer configuration flags. Set from _lpspi_transfer_config_flag_for_master if
348 the transfer is used for master or _lpspi_transfer_config_flag_for_slave enumeration if the
349 transfer is used for slave.*/
350 } lpspi_transfer_t;
351
352 /*! @brief LPSPI master transfer handle structure used for transactional API. */
353 struct _lpspi_master_handle
354 {
355 volatile bool isPcsContinuous; /*!< Is PCS continuous in transfer. */
356 volatile bool writeTcrInIsr; /*!< A flag that whether should write TCR in ISR. */
357
358 volatile bool isByteSwap; /*!< A flag that whether should byte swap. */
359 volatile bool isTxMask; /*!< A flag that whether TCR[TXMSK] is set. */
360 volatile uint16_t bytesPerFrame; /*!< Number of bytes in each frame */
361
362 volatile uint8_t fifoSize; /*!< FIFO dataSize. */
363
364 volatile uint8_t rxWatermark; /*!< Rx watermark. */
365
366 volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */
367 volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */
368
369 uint8_t *volatile txData; /*!< Send buffer. */
370 uint8_t *volatile rxData; /*!< Receive buffer. */
371 volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
372 volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/
373
374 volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */
375 volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */
376
377 uint32_t totalByteCount; /*!< Number of transfer bytes*/
378
379 uint32_t txBuffIfNull; /*!< Used if the txData is NULL. */
380
381 volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/
382
383 lpspi_master_transfer_callback_t callback; /*!< Completion callback. */
384 void *userData; /*!< Callback user data. */
385 };
386
387 /*! @brief LPSPI slave transfer handle structure used for transactional API. */
388 struct _lpspi_slave_handle
389 {
390 volatile bool isByteSwap; /*!< A flag that whether should byte swap. */
391
392 volatile uint8_t fifoSize; /*!< FIFO dataSize. */
393
394 volatile uint8_t rxWatermark; /*!< Rx watermark. */
395
396 volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */
397 volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */
398
399 uint8_t *volatile txData; /*!< Send buffer. */
400 uint8_t *volatile rxData; /*!< Receive buffer. */
401
402 volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
403 volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/
404
405 volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */
406 volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */
407
408 uint32_t totalByteCount; /*!< Number of transfer bytes*/
409
410 volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/
411
412 volatile uint32_t errorCount; /*!< Error count for slave transfer.*/
413
414 lpspi_slave_transfer_callback_t callback; /*!< Completion callback. */
415 void *userData; /*!< Callback user data. */
416 };
417
418 /**********************************************************************************************************************
419 * API
420 *********************************************************************************************************************/
421 #if defined(__cplusplus)
422 extern "C" {
423 #endif /*_cplusplus*/
424
425 /*!
426 * @name Initialization and deinitialization
427 * @{
428 */
429
430 /*!
431 * @brief Initializes the LPSPI master.
432 *
433 * @param base LPSPI peripheral address.
434 * @param masterConfig Pointer to structure lpspi_master_config_t.
435 * @param srcClock_Hz Module source input clock in Hertz
436 */
437 void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz);
438
439 /*!
440 * @brief Sets the lpspi_master_config_t structure to default values.
441 *
442 * This API initializes the configuration structure for LPSPI_MasterInit().
443 * The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified
444 * before calling the LPSPI_MasterInit().
445 * Example:
446 * @code
447 * lpspi_master_config_t masterConfig;
448 * LPSPI_MasterGetDefaultConfig(&masterConfig);
449 * @endcode
450 * @param masterConfig pointer to lpspi_master_config_t structure
451 */
452 void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig);
453
454 /*!
455 * @brief LPSPI slave configuration.
456 *
457 * @param base LPSPI peripheral address.
458 * @param slaveConfig Pointer to a structure lpspi_slave_config_t.
459 */
460 void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig);
461
462 /*!
463 * @brief Sets the lpspi_slave_config_t structure to default values.
464 *
465 * This API initializes the configuration structure for LPSPI_SlaveInit().
466 * The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified
467 * before calling the LPSPI_SlaveInit().
468 * Example:
469 * @code
470 * lpspi_slave_config_t slaveConfig;
471 * LPSPI_SlaveGetDefaultConfig(&slaveConfig);
472 * @endcode
473 * @param slaveConfig pointer to lpspi_slave_config_t structure.
474 */
475 void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig);
476
477 /*!
478 * @brief De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock.
479 * @param base LPSPI peripheral address.
480 */
481 void LPSPI_Deinit(LPSPI_Type *base);
482
483 /*!
484 * @brief Restores the LPSPI peripheral to reset state. Note that this function
485 * sets all registers to reset state. As a result, the LPSPI module can't work after calling
486 * this API.
487 * @param base LPSPI peripheral address.
488 */
489 void LPSPI_Reset(LPSPI_Type *base);
490
491 /*!
492 * @brief Get the LPSPI instance from peripheral base address.
493 *
494 * @param base LPSPI peripheral base address.
495 * @return LPSPI instance.
496 */
497 uint32_t LPSPI_GetInstance(LPSPI_Type *base);
498
499 /*!
500 * @brief Enables the LPSPI peripheral and sets the MCR MDIS to 0.
501 *
502 * @param base LPSPI peripheral address.
503 * @param enable Pass true to enable module, false to disable module.
504 */
LPSPI_Enable(LPSPI_Type * base,bool enable)505 static inline void LPSPI_Enable(LPSPI_Type *base, bool enable)
506 {
507 if (enable)
508 {
509 base->CR |= LPSPI_CR_MEN_MASK;
510 }
511 else
512 {
513 base->CR &= ~LPSPI_CR_MEN_MASK;
514 }
515 }
516
517 /*!
518 *@}
519 */
520
521 /*!
522 * @name Status
523 * @{
524 */
525
526 /*!
527 * @brief Gets the LPSPI status flag state.
528 * @param base LPSPI peripheral address.
529 * @return The LPSPI status(in SR register).
530 */
LPSPI_GetStatusFlags(LPSPI_Type * base)531 static inline uint32_t LPSPI_GetStatusFlags(LPSPI_Type *base)
532 {
533 return (base->SR);
534 }
535
536 /*!
537 * @brief Gets the LPSPI Tx FIFO size.
538 * @param base LPSPI peripheral address.
539 * @return The LPSPI Tx FIFO size.
540 */
LPSPI_GetTxFifoSize(LPSPI_Type * base)541 static inline uint8_t LPSPI_GetTxFifoSize(LPSPI_Type *base)
542 {
543 return (1U << ((base->PARAM & LPSPI_PARAM_TXFIFO_MASK) >> LPSPI_PARAM_TXFIFO_SHIFT));
544 }
545
546 /*!
547 * @brief Gets the LPSPI Rx FIFO size.
548 * @param base LPSPI peripheral address.
549 * @return The LPSPI Rx FIFO size.
550 */
LPSPI_GetRxFifoSize(LPSPI_Type * base)551 static inline uint8_t LPSPI_GetRxFifoSize(LPSPI_Type *base)
552 {
553 return (1U << ((base->PARAM & LPSPI_PARAM_RXFIFO_MASK) >> LPSPI_PARAM_RXFIFO_SHIFT));
554 }
555
556 /*!
557 * @brief Gets the LPSPI Tx FIFO count.
558 * @param base LPSPI peripheral address.
559 * @return The number of words in the transmit FIFO.
560 */
LPSPI_GetTxFifoCount(LPSPI_Type * base)561 static inline uint32_t LPSPI_GetTxFifoCount(LPSPI_Type *base)
562 {
563 return ((base->FSR & LPSPI_FSR_TXCOUNT_MASK) >> LPSPI_FSR_TXCOUNT_SHIFT);
564 }
565
566 /*!
567 * @brief Gets the LPSPI Rx FIFO count.
568 * @param base LPSPI peripheral address.
569 * @return The number of words in the receive FIFO.
570 */
LPSPI_GetRxFifoCount(LPSPI_Type * base)571 static inline uint32_t LPSPI_GetRxFifoCount(LPSPI_Type *base)
572 {
573 return ((base->FSR & LPSPI_FSR_RXCOUNT_MASK) >> LPSPI_FSR_RXCOUNT_SHIFT);
574 }
575
576 /*!
577 * @brief Clears the LPSPI status flag.
578 *
579 * This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the
580 * desired status flag bit to clear. The list of status flags is defined in the _lpspi_flags.
581 * Example usage:
582 * @code
583 * LPSPI_ClearStatusFlags(base, kLPSPI_TxDataRequestFlag|kLPSPI_RxDataReadyFlag);
584 * @endcode
585 *
586 * @param base LPSPI peripheral address.
587 * @param statusFlags The status flag used from type _lpspi_flags.
588 */
LPSPI_ClearStatusFlags(LPSPI_Type * base,uint32_t statusFlags)589 static inline void LPSPI_ClearStatusFlags(LPSPI_Type *base, uint32_t statusFlags)
590 {
591 base->SR = statusFlags; /*!< The status flags are cleared by writing 1 (w1c).*/
592 }
593
594 /*!
595 *@}
596 */
597
598 /*!
599 * @name Interrupts
600 * @{
601 */
602
603 /*!
604 * @brief Enables the LPSPI interrupts.
605 *
606 * This function configures the various interrupt masks of the LPSPI. The parameters are base and an interrupt mask.
607 * Note that, for Tx fill and Rx FIFO drain requests, enabling the interrupt request disables the DMA request.
608 *
609 * @code
610 * LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable );
611 * @endcode
612 *
613 * @param base LPSPI peripheral address.
614 * @param mask The interrupt mask; Use the enum _lpspi_interrupt_enable.
615 */
LPSPI_EnableInterrupts(LPSPI_Type * base,uint32_t mask)616 static inline void LPSPI_EnableInterrupts(LPSPI_Type *base, uint32_t mask)
617 {
618 base->IER |= mask;
619 }
620
621 /*!
622 * @brief Disables the LPSPI interrupts.
623 *
624 * @code
625 * LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable );
626 * @endcode
627 *
628 * @param base LPSPI peripheral address.
629 * @param mask The interrupt mask; Use the enum _lpspi_interrupt_enable.
630 */
LPSPI_DisableInterrupts(LPSPI_Type * base,uint32_t mask)631 static inline void LPSPI_DisableInterrupts(LPSPI_Type *base, uint32_t mask)
632 {
633 base->IER &= ~mask;
634 }
635
636 /*!
637 *@}
638 */
639
640 /*!
641 * @name DMA Control
642 * @{
643 */
644
645 /*!
646 * @brief Enables the LPSPI DMA request.
647 *
648 * This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask.
649 * @code
650 * LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);
651 * @endcode
652 *
653 * @param base LPSPI peripheral address.
654 * @param mask The interrupt mask; Use the enum _lpspi_dma_enable.
655 */
LPSPI_EnableDMA(LPSPI_Type * base,uint32_t mask)656 static inline void LPSPI_EnableDMA(LPSPI_Type *base, uint32_t mask)
657 {
658 base->DER |= mask;
659 }
660
661 /*!
662 * @brief Disables the LPSPI DMA request.
663 *
664 * This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask.
665 * @code
666 * SPI_DisableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);
667 * @endcode
668 *
669 * @param base LPSPI peripheral address.
670 * @param mask The interrupt mask; Use the enum _lpspi_dma_enable.
671 */
LPSPI_DisableDMA(LPSPI_Type * base,uint32_t mask)672 static inline void LPSPI_DisableDMA(LPSPI_Type *base, uint32_t mask)
673 {
674 base->DER &= ~mask;
675 }
676
677 /*!
678 * @brief Gets the LPSPI Transmit Data Register address for a DMA operation.
679 *
680 * This function gets the LPSPI Transmit Data Register address because this value is needed
681 * for the DMA operation.
682 * This function can be used for either master or slave mode.
683 *
684 * @param base LPSPI peripheral address.
685 * @return The LPSPI Transmit Data Register address.
686 */
LPSPI_GetTxRegisterAddress(LPSPI_Type * base)687 static inline uint32_t LPSPI_GetTxRegisterAddress(LPSPI_Type *base)
688 {
689 return (uint32_t) & (base->TDR);
690 }
691
692 /*!
693 * @brief Gets the LPSPI Receive Data Register address for a DMA operation.
694 *
695 * This function gets the LPSPI Receive Data Register address because this value is needed
696 * for the DMA operation.
697 * This function can be used for either master or slave mode.
698 *
699 * @param base LPSPI peripheral address.
700 * @return The LPSPI Receive Data Register address.
701 */
LPSPI_GetRxRegisterAddress(LPSPI_Type * base)702 static inline uint32_t LPSPI_GetRxRegisterAddress(LPSPI_Type *base)
703 {
704 return (uint32_t) & (base->RDR);
705 }
706
707 /*!
708 *@}
709 */
710
711 /*!
712 * @name Bus Operations
713 * @{
714 */
715
716 /*!
717 * @brief Check the argument for transfer .
718 *
719 * @param base LPSPI peripheral address.
720 * @param transfer the transfer struct to be used.
721 * @param isEdma True to check for EDMA transfer, false to check interrupt non-blocking transfer
722 * @return Return true for right and false for wrong.
723 */
724 bool LPSPI_CheckTransferArgument(LPSPI_Type *base, lpspi_transfer_t *transfer, bool isEdma);
725
726 /*!
727 * @brief Configures the LPSPI for either master or slave.
728 *
729 * Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0).
730 *
731 * @param base LPSPI peripheral address.
732 * @param mode Mode setting (master or slave) of type lpspi_master_slave_mode_t.
733 */
LPSPI_SetMasterSlaveMode(LPSPI_Type * base,lpspi_master_slave_mode_t mode)734 static inline void LPSPI_SetMasterSlaveMode(LPSPI_Type *base, lpspi_master_slave_mode_t mode)
735 {
736 base->CFGR1 = (base->CFGR1 & (~LPSPI_CFGR1_MASTER_MASK)) | LPSPI_CFGR1_MASTER(mode);
737 }
738
739 /*!
740 * @brief Configures the peripheral chip select used for the transfer.
741 *
742 * @param base LPSPI peripheral address.
743 * @param select LPSPI Peripheral Chip Select (PCS) configuration.
744 */
LPSPI_SelectTransferPCS(LPSPI_Type * base,lpspi_which_pcs_t select)745 static inline void LPSPI_SelectTransferPCS(LPSPI_Type *base, lpspi_which_pcs_t select)
746 {
747 base->TCR = (base->TCR & (~LPSPI_TCR_PCS_MASK)) | LPSPI_TCR_PCS((uint8_t)select);
748 }
749
750 /*!
751 * @brief Set the PCS signal to continuous or uncontinuous mode.
752 *
753 * @note In master mode, continuous transfer will keep the PCS asserted at the end of the frame size, until a command
754 * word is received that starts a new frame. So PCS must be set back to uncontinuous when transfer finishes.
755 * In slave mode, when continuous transfer is enabled, the LPSPI will only transmit the first frame size bits, after
756 * that the LPSPI will transmit received data back (assuming a 32-bit shift register).
757 *
758 * @param base LPSPI peripheral address.
759 * @param IsContinous True to set the transfer PCS to continuous mode, false to set to uncontinuous mode.
760 */
LPSPI_SetPCSContinous(LPSPI_Type * base,bool IsContinous)761 static inline void LPSPI_SetPCSContinous(LPSPI_Type *base, bool IsContinous)
762 {
763 if (IsContinous)
764 {
765 base->TCR |= LPSPI_TCR_CONT_MASK;
766 }
767 else
768 {
769 base->TCR &= LPSPI_TCR_CONT_MASK;
770 }
771 }
772
773 /*!
774 * @brief Returns whether the LPSPI module is in master mode.
775 *
776 * @param base LPSPI peripheral address.
777 * @return Returns true if the module is in master mode or false if the module is in slave mode.
778 */
LPSPI_IsMaster(LPSPI_Type * base)779 static inline bool LPSPI_IsMaster(LPSPI_Type *base)
780 {
781 return (bool)((base->CFGR1) & LPSPI_CFGR1_MASTER_MASK);
782 }
783
784 /*!
785 * @brief Flushes the LPSPI FIFOs.
786 *
787 * @param base LPSPI peripheral address.
788 * @param flushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO.
789 * @param flushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO.
790 */
LPSPI_FlushFifo(LPSPI_Type * base,bool flushTxFifo,bool flushRxFifo)791 static inline void LPSPI_FlushFifo(LPSPI_Type *base, bool flushTxFifo, bool flushRxFifo)
792 {
793 base->CR |= ((uint32_t)flushTxFifo << LPSPI_CR_RTF_SHIFT) | ((uint32_t)flushRxFifo << LPSPI_CR_RRF_SHIFT);
794 }
795
796 /*!
797 * @brief Sets the transmit and receive FIFO watermark values.
798 *
799 * This function allows the user to set the receive and transmit FIFO watermarks. The function
800 * does not compare the watermark settings to the FIFO size. The FIFO watermark should not be
801 * equal to or greater than the FIFO size. It is up to the higher level driver to make this check.
802 *
803 * @param base LPSPI peripheral address.
804 * @param txWater The TX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated.
805 * @param rxWater The RX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated.
806 */
LPSPI_SetFifoWatermarks(LPSPI_Type * base,uint32_t txWater,uint32_t rxWater)807 static inline void LPSPI_SetFifoWatermarks(LPSPI_Type *base, uint32_t txWater, uint32_t rxWater)
808 {
809 base->FCR = LPSPI_FCR_TXWATER(txWater) | LPSPI_FCR_RXWATER(rxWater);
810 }
811
812 /*!
813 * @brief Configures all LPSPI peripheral chip select polarities simultaneously.
814 *
815 * Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0).
816 *
817 * This is an example: PCS0 and PCS1 set to active low and other PCSs set to active high. Note that the number of
818 * PCS is device-specific.
819 * @code
820 * LPSPI_SetAllPcsPolarity(base, kLPSPI_Pcs0ActiveLow | kLPSPI_Pcs1ActiveLow);
821 * @endcode
822 *
823 * @param base LPSPI peripheral address.
824 * @param mask The PCS polarity mask; Use the enum _lpspi_pcs_polarity.
825 */
LPSPI_SetAllPcsPolarity(LPSPI_Type * base,uint32_t mask)826 static inline void LPSPI_SetAllPcsPolarity(LPSPI_Type *base, uint32_t mask)
827 {
828 base->CFGR1 = (base->CFGR1 & ~LPSPI_CFGR1_PCSPOL_MASK) | LPSPI_CFGR1_PCSPOL(~mask);
829 }
830
831 /*!
832 * @brief Configures the frame size.
833 *
834 * The minimum frame size is 8-bits and the maximum frame size is 4096-bits. If the frame size is less than or equal
835 * to 32-bits, the word size and frame size are identical. If the frame size is greater than 32-bits, the word
836 * size is 32-bits for each word except the last (the last word contains the remainder bits if the frame size is not
837 * divisible by 32). The minimum word size is 2-bits. A frame size of 33-bits (or similar) is not supported.
838 *
839 * Note 1: The transmit command register should be initialized before enabling the LPSPI in slave mode, although
840 * the command register does not update until after the LPSPI is enabled. After it is enabled, the transmit command
841 * register
842 * should only be changed if the LPSPI is idle.
843 *
844 * Note 2: The transmit and command FIFO is a combined FIFO that includes both transmit data and command words. That
845 * means the TCR register should be written to when the Tx FIFO is not full.
846 *
847 * @param base LPSPI peripheral address.
848 * @param frameSize The frame size in number of bits.
849 */
LPSPI_SetFrameSize(LPSPI_Type * base,uint32_t frameSize)850 static inline void LPSPI_SetFrameSize(LPSPI_Type *base, uint32_t frameSize)
851 {
852 base->TCR = (base->TCR & ~LPSPI_TCR_FRAMESZ_MASK) | LPSPI_TCR_FRAMESZ(frameSize - 1U);
853 }
854
855 /*!
856 * @brief Sets the LPSPI baud rate in bits per second.
857 *
858 * This function takes in the desired bitsPerSec (baud rate) and calculates the nearest
859 * possible baud rate without exceeding the desired baud rate and returns the
860 * calculated baud rate in bits-per-second. It requires the caller to provide
861 * the frequency of the module source clock (in Hertz). Note that the baud rate
862 * does not go into effect until the Transmit Control Register (TCR) is programmed
863 * with the prescale value. Hence, this function returns the prescale tcrPrescaleValue
864 * parameter for later programming in the TCR. The higher level
865 * peripheral driver should alert the user of an out of range baud rate input.
866 *
867 * Note that the LPSPI module must first be disabled before configuring this.
868 * Note that the LPSPI module must be configured for master mode before configuring this.
869 *
870 * @param base LPSPI peripheral address.
871 * @param baudRate_Bps The desired baud rate in bits per second.
872 * @param srcClock_Hz Module source input clock in Hertz.
873 * @param tcrPrescaleValue The TCR prescale value needed to program the TCR.
874 * @return The actual calculated baud rate. This function may also return a "0" if the
875 * LPSPI is not configured for master mode or if the LPSPI module is not disabled.
876 */
877
878 uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base,
879 uint32_t baudRate_Bps,
880 uint32_t srcClock_Hz,
881 uint32_t *tcrPrescaleValue);
882
883 /*!
884 * @brief Manually configures a specific LPSPI delay parameter (module must be disabled to
885 * change the delay values).
886 *
887 * This function configures the following:
888 * SCK to PCS delay, or
889 * PCS to SCK delay, or
890 * The configurations must occur between the transfer delay.
891 *
892 * The delay names are available in type lpspi_delay_type_t.
893 *
894 * The user passes the desired delay along with the delay value.
895 * This allows the user to directly set the delay values if they have
896 * pre-calculated them or if they simply wish to manually increment the value.
897 *
898 * Note that the LPSPI module must first be disabled before configuring this.
899 * Note that the LPSPI module must be configured for master mode before configuring this.
900 *
901 * @param base LPSPI peripheral address.
902 * @param scaler The 8-bit delay value 0x00 to 0xFF (255).
903 * @param whichDelay The desired delay to configure, must be of type lpspi_delay_type_t.
904 */
905 void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay);
906
907 /*!
908 * @brief Calculates the delay based on the desired delay input in nanoseconds (module must be
909 * disabled to change the delay values).
910 *
911 * This function calculates the values for the following:
912 * SCK to PCS delay, or
913 * PCS to SCK delay, or
914 * The configurations must occur between the transfer delay.
915 *
916 * The delay names are available in type lpspi_delay_type_t.
917 *
918 * The user passes the desired delay and the desired delay value in
919 * nano-seconds. The function calculates the value needed for the desired delay parameter
920 * and returns the actual calculated delay because an exact delay match may not be possible. In this
921 * case, the closest match is calculated without going below the desired delay value input.
922 * It is possible to input a very large delay value that exceeds the capability of the part, in
923 * which case the maximum supported delay is returned. It is up to the higher level
924 * peripheral driver to alert the user of an out of range delay input.
925 *
926 * Note that the LPSPI module must be configured for master mode before configuring this. And note that
927 * the delayTime = LPSPI_clockSource / (PRESCALE * Delay_scaler).
928 *
929 * @param base LPSPI peripheral address.
930 * @param delayTimeInNanoSec The desired delay value in nano-seconds.
931 * @param whichDelay The desired delay to configuration, which must be of type lpspi_delay_type_t.
932 * @param srcClock_Hz Module source input clock in Hertz.
933 * @return actual Calculated delay value in nano-seconds.
934 */
935 uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base,
936 uint32_t delayTimeInNanoSec,
937 lpspi_delay_type_t whichDelay,
938 uint32_t srcClock_Hz);
939
940 /*!
941 * @brief Writes data into the transmit data buffer.
942 *
943 * This function writes data passed in by the user to the Transmit Data Register (TDR).
944 * The user can pass up to 32-bits of data to load into the TDR. If the frame size exceeds 32-bits,
945 * the user has to manage sending the data one 32-bit word at a time.
946 * Any writes to the TDR result in an immediate push to the transmit FIFO.
947 * This function can be used for either master or slave modes.
948 *
949 * @param base LPSPI peripheral address.
950 * @param data The data word to be sent.
951 */
LPSPI_WriteData(LPSPI_Type * base,uint32_t data)952 static inline void LPSPI_WriteData(LPSPI_Type *base, uint32_t data)
953 {
954 base->TDR = data;
955 }
956
957 /*!
958 * @brief Reads data from the data buffer.
959 *
960 * This function reads the data from the Receive Data Register (RDR).
961 * This function can be used for either master or slave mode.
962 *
963 * @param base LPSPI peripheral address.
964 * @return The data read from the data buffer.
965 */
LPSPI_ReadData(LPSPI_Type * base)966 static inline uint32_t LPSPI_ReadData(LPSPI_Type *base)
967 {
968 return (base->RDR);
969 }
970
971 /*!
972 * @brief Set up the dummy data.
973 *
974 * @param base LPSPI peripheral address.
975 * @param dummyData Data to be transferred when tx buffer is NULL.
976 * Note:
977 * This API has no effect when LPSPI in slave interrupt mode, because driver
978 * will set the TXMSK bit to 1 if txData is NULL, no data is loaded from transmit
979 * FIFO and output pin is tristated.
980 */
981 void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData);
982
983 /*!
984 *@}
985 */
986
987 /*!
988 * @name Transactional
989 * @{
990 */
991 /*Transactional APIs*/
992
993 /*!
994 * @brief Initializes the LPSPI master handle.
995 *
996 * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a
997 * specified LPSPI instance, call this API once to get the initialized handle.
998
999 * @param base LPSPI peripheral address.
1000 * @param handle LPSPI handle pointer to lpspi_master_handle_t.
1001 * @param callback DSPI callback.
1002 * @param userData callback function parameter.
1003 */
1004 void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base,
1005 lpspi_master_handle_t *handle,
1006 lpspi_master_transfer_callback_t callback,
1007 void *userData);
1008
1009 /*!
1010 * @brief LPSPI master transfer data using a polling method.
1011 *
1012 * This function transfers data using a polling method. This is a blocking function, which does not return until all
1013 * transfers have been
1014 * completed.
1015 *
1016 * Note:
1017 * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4.
1018 * For bytesPerFrame greater than 4:
1019 * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4.
1020 * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
1021 *
1022 * @param base LPSPI peripheral address.
1023 * @param transfer pointer to lpspi_transfer_t structure.
1024 * @return status of status_t.
1025 */
1026 status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer);
1027
1028 /*!
1029 * @brief LPSPI master transfer data using an interrupt method.
1030 *
1031 * This function transfers data using an interrupt method. This is a non-blocking function, which returns right away.
1032 * When all data is transferred, the callback function is called.
1033 *
1034 * Note:
1035 * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4.
1036 * For bytesPerFrame greater than 4:
1037 * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4.
1038 * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
1039 *
1040 * @param base LPSPI peripheral address.
1041 * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state.
1042 * @param transfer pointer to lpspi_transfer_t structure.
1043 * @return status of status_t.
1044 */
1045 status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer);
1046
1047 /*!
1048 * @brief Gets the master transfer remaining bytes.
1049 *
1050 * This function gets the master transfer remaining bytes.
1051 *
1052 * @param base LPSPI peripheral address.
1053 * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state.
1054 * @param count Number of bytes transferred so far by the non-blocking transaction.
1055 * @return status of status_t.
1056 */
1057 status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count);
1058
1059 /*!
1060 * @brief LPSPI master abort transfer which uses an interrupt method.
1061 *
1062 * This function aborts a transfer which uses an interrupt method.
1063 *
1064 * @param base LPSPI peripheral address.
1065 * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state.
1066 */
1067 void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle);
1068
1069 /*!
1070 * @brief LPSPI Master IRQ handler function.
1071 *
1072 * This function processes the LPSPI transmit and receive IRQ.
1073 *
1074 * @param base LPSPI peripheral address.
1075 * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state.
1076 */
1077 void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *handle);
1078
1079 /*!
1080 * @brief Initializes the LPSPI slave handle.
1081 *
1082 * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a
1083 * specified LPSPI instance, call this API once to get the initialized handle.
1084 *
1085 * @param base LPSPI peripheral address.
1086 * @param handle LPSPI handle pointer to lpspi_slave_handle_t.
1087 * @param callback DSPI callback.
1088 * @param userData callback function parameter.
1089 */
1090 void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base,
1091 lpspi_slave_handle_t *handle,
1092 lpspi_slave_transfer_callback_t callback,
1093 void *userData);
1094
1095 /*!
1096 * @brief LPSPI slave transfer data using an interrupt method.
1097 *
1098 * This function transfer data using an interrupt method. This is a non-blocking function, which returns right away.
1099 * When all data is transferred, the callback function is called.
1100 *
1101 * Note:
1102 * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4.
1103 * For bytesPerFrame greater than 4:
1104 * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4.
1105 * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
1106 *
1107 * @param base LPSPI peripheral address.
1108 * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state.
1109 * @param transfer pointer to lpspi_transfer_t structure.
1110 * @return status of status_t.
1111 */
1112 status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer);
1113
1114 /*!
1115 * @brief Gets the slave transfer remaining bytes.
1116 *
1117 * This function gets the slave transfer remaining bytes.
1118 *
1119 * @param base LPSPI peripheral address.
1120 * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state.
1121 * @param count Number of bytes transferred so far by the non-blocking transaction.
1122 * @return status of status_t.
1123 */
1124 status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count);
1125
1126 /*!
1127 * @brief LPSPI slave aborts a transfer which uses an interrupt method.
1128 *
1129 * This function aborts a transfer which uses an interrupt method.
1130 *
1131 * @param base LPSPI peripheral address.
1132 * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state.
1133 */
1134 void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle);
1135
1136 /*!
1137 * @brief LPSPI Slave IRQ handler function.
1138 *
1139 * This function processes the LPSPI transmit and receives an IRQ.
1140 *
1141 * @param base LPSPI peripheral address.
1142 * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state.
1143 */
1144 void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle);
1145
1146 /*!
1147 *@}
1148 */
1149
1150 #if defined(__cplusplus)
1151 }
1152 #endif
1153
1154 /*! @}*/
1155
1156 #endif /*_FSL_LPSPI_H_*/
1157
