1 /* 2 ** ################################################################### 3 ** Compilers: Keil ARM C/C++ Compiler 4 ** Freescale C/C++ for Embedded ARM 5 ** GNU C Compiler 6 ** GNU C Compiler - CodeSourcery Sourcery G++ 7 ** IAR ANSI C/C++ Compiler for ARM 8 ** 9 ** Reference manual: MKW40Z160RM, Rev. 1.1, 4/2015 10 ** Version: rev. 1.2, 2015-05-07 11 ** Build: b150513 12 ** 13 ** Abstract: 14 ** Provides a system configuration function and a global variable that 15 ** contains the system frequency. It configures the device and initializes 16 ** the oscillator (PLL) that is part of the microcontroller device. 17 ** 18 ** Copyright (c) 2015 Freescale Semiconductor, Inc. 19 ** All rights reserved. 20 ** 21 ** Redistribution and use in source and binary forms, with or without modification, 22 ** are permitted provided that the following conditions are met: 23 ** 24 ** o Redistributions of source code must retain the above copyright notice, this list 25 ** of conditions and the following disclaimer. 26 ** 27 ** o Redistributions in binary form must reproduce the above copyright notice, this 28 ** list of conditions and the following disclaimer in the documentation and/or 29 ** other materials provided with the distribution. 30 ** 31 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its 32 ** contributors may be used to endorse or promote products derived from this 33 ** software without specific prior written permission. 34 ** 35 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 36 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 37 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 38 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 39 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 41 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 42 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 44 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45 ** 46 ** http: www.freescale.com 47 ** mail: support@freescale.com 48 ** 49 ** Revisions: 50 ** - rev. 1.0 (2014-07-17) 51 ** Initial version. 52 ** - rev. 1.1 (2015-03-05) 53 ** Update with reference manual rev 1.0 54 ** - rev. 1.2 (2015-05-07) 55 ** Update with reference manual rev 1.1 56 ** 57 ** ################################################################### 58 */ 59 60 /*! 61 * @file MKW40Z4 62 * @version 1.2 63 * @date 2015-05-07 64 * @brief Device specific configuration file for MKW40Z4 (header file) 65 * 66 * Provides a system configuration function and a global variable that contains 67 * the system frequency. It configures the device and initializes the oscillator 68 * (PLL) that is part of the microcontroller device. 69 */ 70 71 #ifndef SYSTEM_MKW40Z4_H_ 72 #define SYSTEM_MKW40Z4_H_ /**< Symbol preventing repeated inclusion */ 73 74 #ifdef __cplusplus 75 extern "C" { 76 #endif 77 78 #include <stdint.h> 79 80 81 #ifndef DISABLE_WDOG 82 #define DISABLE_WDOG 1 83 #endif 84 85 /* MCG mode constants */ 86 87 #define MCG_MODE_FEI 0U 88 #define MCG_MODE_FBI 1U 89 #define MCG_MODE_BLPI 2U 90 #define MCG_MODE_FEE 3U 91 #define MCG_MODE_FBE 4U 92 #define MCG_MODE_BLPE 5U 93 94 /* Predefined clock setups 95 To select a specific clock setup, define symbol CLOCK_SETUP with a selected value. 96 E.g.: #define CLOCK_SETUP 0 97 98 0 ... Default part configuration 99 Multipurpose Clock Generator (MCG) in FEI mode. 100 Reference clock source for MCG module: Slow internal reference clock 101 Core clock = 20.97152MHz 102 Bus clock = 20.97152MHz 103 1 ... Maximum achievable clock frequency configuration 104 Multipurpose Clock Generator (MCG) in FEE mode. 105 Reference clock source for MCG module: System oscillator reference clock 106 Core clock = 75MHz 107 Bus clock = 25MHz 108 2 ... Chip internally clocked, ready for Very Low Power Run mode 109 Multipurpose Clock Generator (MCG) in BLPI mode. 110 Reference clock source for MCG module: Fast internal reference clock 111 Core clock = 4MHz 112 Bus clock = 0.8MHz 113 3 ... Chip externally clocked, ready for Very Low Power Run mode 114 Multipurpose Clock Generator (MCG) in BLPE mode. 115 Reference clock source for MCG module: System oscillator reference clock 116 Core clock = 3.333333333333MHz 117 Bus clock = 0.833333333333MHz 118 4 ... Chip externally clocked 119 Multipurpose Clock Generator (MCG) in BLPE mode. 120 Reference clock source for MCG module: System oscillator reference clock 121 Core clock = 32MHz 122 Bus clock = 16MHz 123 */ 124 125 /* Define clock source values */ 126 127 #define CPU_XTAL_CLK_HZ 32000000u /* Value of the external crystal or oscillator clock frequency in Hz */ 128 #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ 129 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ 130 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ 131 132 /* RF oscillator setting */ 133 #define SYSTEM_RSIM_CONTROL_VALUE 0xC00100U /* Enable RF oscillator in Run/Wait mode */ 134 135 /* Low power mode enable */ 136 137 /* SMC_PMPROT: ?=0,?=0,AVLP=1,?=0,?=0,?=0,AVLLS=1,?=0 */ 138 #define SYSTEM_SMC_PMPROT_VALUE (SMC_PMPROT_AVLP_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLLS_MASK) /* Mask of allowed low power modes used to initialize power modes protection register */ 139 140 /* Internal reference clock trim */ 141 142 /* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */ 143 /* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */ 144 /* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */ 145 /* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */ 146 147 /* System clock */ 148 149 #ifdef CLOCK_SETUP 150 #if (CLOCK_SETUP == 0) 151 #define DEFAULT_SYSTEM_CLOCK 20971520UL /* Default System clock value */ 152 #define MCG_MODE MCG_MODE_FEI /* Clock generator mode */ 153 /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ 154 #define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */ 155 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */ 156 #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */ 157 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ 158 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ 159 /* MCG_C6: CME=0 */ 160 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */ 161 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ 162 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ 163 /* MCG_C7: OSCSEL=0 */ 164 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */ 165 /* SIM_SOPT1: OSC32KSEL=3 */ 166 #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000UL /* SIM_SOPT1 */ 167 /* SIM_SOPT2: TPMSRC=0 */ 168 #define SYSTEM_SIM_SOPT2_VALUE 0x00UL /* SIM_SOPT2 */ 169 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=0 */ 170 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00UL /* SIM_CLKDIV1 */ 171 #elif (CLOCK_SETUP == 1) 172 #define DEFAULT_SYSTEM_CLOCK 47972352UL /* Default System clock value */ 173 #define MCG_MODE MCG_MODE_FEI /* Clock generator mode */ 174 /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ 175 #define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */ 176 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */ 177 #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */ 178 /* MCG_C4: DMX32=1,DRST_DRS=1,FCTRIM=0,SCFTRIM=0 */ 179 #define SYSTEM_MCG_C4_VALUE 0xA0U /* MCG_C4 */ 180 /* MCG_C6: CME=0 */ 181 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */ 182 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ 183 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ 184 /* MCG_C7: OSCSEL=0 */ 185 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */ 186 /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ 187 #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000UL /* SIM_SOPT1 */ 188 /* SIM_SOPT2: TPMSRC=0 */ 189 #define SYSTEM_SIM_SOPT2_VALUE 0x00UL /* SIM_SOPT2 */ 190 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */ 191 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00010000UL /* SIM_CLKDIV1 */ 192 #elif (CLOCK_SETUP == 2) 193 #define DEFAULT_SYSTEM_CLOCK 4000000UL /* Default System clock value */ 194 #define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */ 195 /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ 196 #define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */ 197 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=1 */ 198 #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */ 199 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ 200 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ 201 /* MCG_C6: CME=0 */ 202 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */ 203 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ 204 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ 205 /* MCG_C7: OSCSEL=0 */ 206 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */ 207 /* SIM_SOPT1: OSC32KSEL=3 */ 208 #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000UL /* SIM_SOPT1 */ 209 /* SIM_SOPT2: TPMSRC=0 */ 210 #define SYSTEM_SIM_SOPT2_VALUE 0x00UL /* SIM_SOPT2 */ 211 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=4 */ 212 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000UL /* SIM_CLKDIV1 */ 213 #elif (CLOCK_SETUP == 3) 214 #define DEFAULT_SYSTEM_CLOCK 4000000UL /* Default System clock value */ 215 #define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */ 216 /* MCG_C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ 217 #define SYSTEM_MCG_C1_VALUE 0xAAU /* MCG_C1 */ 218 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=1 */ 219 #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */ 220 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ 221 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ 222 /* MCG_C6: CME=0 */ 223 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */ 224 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ 225 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ 226 /* MCG_C7: OSCSEL=0 */ 227 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */ 228 /* SIM_SOPT1: OSC32KSEL=3 */ 229 #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000UL /* SIM_SOPT1 */ 230 /* SIM_SOPT2: TPMSRC=0 */ 231 #define SYSTEM_SIM_SOPT2_VALUE 0x00UL /* SIM_SOPT2 */ 232 /* SIM_CLKDIV1: OUTDIV1=7,OUTDIV4=3 */ 233 #define SYSTEM_SIM_CLKDIV1_VALUE 0x70030000UL /* SIM_CLKDIV1 */ 234 #elif (CLOCK_SETUP == 4) 235 #define DEFAULT_SYSTEM_CLOCK 32000000UL /* Default System clock value */ 236 #define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */ 237 /* MCG_C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ 238 #define SYSTEM_MCG_C1_VALUE 0xAAU /* MCG_C1 */ 239 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=1 */ 240 #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */ 241 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ 242 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */ 243 /* MCG_C6: CME=0 */ 244 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */ 245 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */ 246 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */ 247 /* MCG_C7: OSCSEL=0 */ 248 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */ 249 /* SIM_SOPT1: OSC32KSEL=3 */ 250 #define SYSTEM_SIM_SOPT1_VALUE 0x000C0000UL /* SIM_SOPT1 */ 251 /* SIM_SOPT2: TPMSRC=0 */ 252 #define SYSTEM_SIM_SOPT2_VALUE 0x00UL /* SIM_SOPT2 */ 253 /* SIM_CLKDIV1: OUTDIV1=7,OUTDIV4=3 */ 254 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00010000UL /* SIM_CLKDIV1 */ 255 #endif 256 #else 257 #define DEFAULT_SYSTEM_CLOCK 20971520U /* Default System clock value */ 258 #endif 259 260 261 /** 262 * @brief System clock frequency (core clock) 263 * 264 * The system clock frequency supplied to the SysTick timer and the processor 265 * core clock. This variable can be used by the user application to setup the 266 * SysTick timer or configure other parameters. It may also be used by debugger to 267 * query the frequency of the debug timer or configure the trace clock speed 268 * SystemCoreClock is initialized with a correct predefined value. 269 */ 270 extern uint32_t SystemCoreClock; 271 272 /** 273 * @brief Setup the microcontroller system. 274 * 275 * Typically this function configures the oscillator (PLL) that is part of the 276 * microcontroller device. For systems with variable clock speed it also updates 277 * the variable SystemCoreClock. SystemInit is called from startup_device file. 278 */ 279 void SystemInit (void); 280 281 /** 282 * @brief Updates the SystemCoreClock variable. 283 * 284 * It must be called whenever the core clock is changed during program 285 * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates 286 * the current core clock. 287 */ 288 void SystemCoreClockUpdate (void); 289 290 #ifdef __cplusplus 291 } 292 #endif 293 294 #endif /* #if !defined(SYSTEM_MKW40Z4_H_) */ 295
