1 /* 2 ** ################################################################### 3 ** Version: rev. 1.7, 2015-06-08 4 ** Build: b200409 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2020 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2014-07-30) 20 ** Initial version 21 ** - rev. 1.1 (2014-08-28) 22 ** Update of startup files - possibility to override DefaultISR added. 23 ** - rev. 1.2 (2014-11-07) 24 ** Update according to the new version of reference manual Rev. 1 Draft A. 25 ** - rev. 1.3 (2015-01-21) 26 ** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances 27 ** - rev. 1.4 (2015-05-19) 28 ** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT. 29 ** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC. 30 ** Added features for PDB and PORT. 31 ** - rev. 1.5 (2015-05-25) 32 ** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS 33 ** - rev. 1.6 (2015-05-27) 34 ** Several USB features added. 35 ** - rev. 1.7 (2015-06-08) 36 ** FTM features BUS_CLOCK and FAST_CLOCK removed. 37 ** 38 ** ################################################################### 39 */ 40 41 #ifndef _MK80F25615_FEATURES_H_ 42 #define _MK80F25615_FEATURES_H_ 43 44 /* SOC module features */ 45 46 /* @brief ADC16 availability on the SoC. */ 47 #define FSL_FEATURE_SOC_ADC16_COUNT (1) 48 /* @brief AIPS availability on the SoC. */ 49 #define FSL_FEATURE_SOC_AIPS_COUNT (2) 50 /* @brief AXBS availability on the SoC. */ 51 #define FSL_FEATURE_SOC_AXBS_COUNT (1) 52 /* @brief MMCAU availability on the SoC. */ 53 #define FSL_FEATURE_SOC_MMCAU_COUNT (1) 54 /* @brief CMP availability on the SoC. */ 55 #define FSL_FEATURE_SOC_CMP_COUNT (2) 56 /* @brief CMT availability on the SoC. */ 57 #define FSL_FEATURE_SOC_CMT_COUNT (1) 58 /* @brief CRC availability on the SoC. */ 59 #define FSL_FEATURE_SOC_CRC_COUNT (1) 60 /* @brief DAC availability on the SoC. */ 61 #define FSL_FEATURE_SOC_DAC_COUNT (1) 62 /* @brief EDMA availability on the SoC. */ 63 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 64 /* @brief DMAMUX availability on the SoC. */ 65 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 66 /* @brief DSPI availability on the SoC. */ 67 #define FSL_FEATURE_SOC_DSPI_COUNT (3) 68 /* @brief EMVSIM availability on the SoC. */ 69 #define FSL_FEATURE_SOC_EMVSIM_COUNT (2) 70 /* @brief EWM availability on the SoC. */ 71 #define FSL_FEATURE_SOC_EWM_COUNT (1) 72 /* @brief FB availability on the SoC. */ 73 #define FSL_FEATURE_SOC_FB_COUNT (1) 74 /* @brief FLEXIO availability on the SoC. */ 75 #define FSL_FEATURE_SOC_FLEXIO_COUNT (1) 76 /* @brief FMC availability on the SoC. */ 77 #define FSL_FEATURE_SOC_FMC_COUNT (1) 78 /* @brief FTFA availability on the SoC. */ 79 #define FSL_FEATURE_SOC_FTFA_COUNT (1) 80 /* @brief FTM availability on the SoC. */ 81 #define FSL_FEATURE_SOC_FTM_COUNT (4) 82 /* @brief GPIO availability on the SoC. */ 83 #define FSL_FEATURE_SOC_GPIO_COUNT (5) 84 /* @brief I2C availability on the SoC. */ 85 #define FSL_FEATURE_SOC_I2C_COUNT (4) 86 /* @brief I2S availability on the SoC. */ 87 #define FSL_FEATURE_SOC_I2S_COUNT (1) 88 /* @brief LLWU availability on the SoC. */ 89 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 90 /* @brief LMEM availability on the SoC. */ 91 #define FSL_FEATURE_SOC_LMEM_COUNT (1) 92 /* @brief LPTMR availability on the SoC. */ 93 #define FSL_FEATURE_SOC_LPTMR_COUNT (2) 94 /* @brief LPUART availability on the SoC. */ 95 #define FSL_FEATURE_SOC_LPUART_COUNT (5) 96 /* @brief MCG availability on the SoC. */ 97 #define FSL_FEATURE_SOC_MCG_COUNT (1) 98 /* @brief MCM availability on the SoC. */ 99 #define FSL_FEATURE_SOC_MCM_COUNT (1) 100 /* @brief SYSMPU availability on the SoC. */ 101 #define FSL_FEATURE_SOC_SYSMPU_COUNT (1) 102 /* @brief OSC availability on the SoC. */ 103 #define FSL_FEATURE_SOC_OSC_COUNT (1) 104 /* @brief PDB availability on the SoC. */ 105 #define FSL_FEATURE_SOC_PDB_COUNT (1) 106 /* @brief PIT availability on the SoC. */ 107 #define FSL_FEATURE_SOC_PIT_COUNT (1) 108 /* @brief PMC availability on the SoC. */ 109 #define FSL_FEATURE_SOC_PMC_COUNT (1) 110 /* @brief PORT availability on the SoC. */ 111 #define FSL_FEATURE_SOC_PORT_COUNT (5) 112 /* @brief QuadSPI availability on the SoC. */ 113 #define FSL_FEATURE_SOC_QuadSPI_COUNT (1) 114 /* @brief RCM availability on the SoC. */ 115 #define FSL_FEATURE_SOC_RCM_COUNT (1) 116 /* @brief RFSYS availability on the SoC. */ 117 #define FSL_FEATURE_SOC_RFSYS_COUNT (1) 118 /* @brief RFVBAT availability on the SoC. */ 119 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1) 120 /* @brief RTC availability on the SoC. */ 121 #define FSL_FEATURE_SOC_RTC_COUNT (1) 122 /* @brief SDHC availability on the SoC. */ 123 #define FSL_FEATURE_SOC_SDHC_COUNT (1) 124 /* @brief SDRAM availability on the SoC. */ 125 #define FSL_FEATURE_SOC_SDRAM_COUNT (1) 126 /* @brief SIM availability on the SoC. */ 127 #define FSL_FEATURE_SOC_SIM_COUNT (1) 128 /* @brief SMC availability on the SoC. */ 129 #define FSL_FEATURE_SOC_SMC_COUNT (1) 130 /* @brief TPM availability on the SoC. */ 131 #define FSL_FEATURE_SOC_TPM_COUNT (2) 132 /* @brief TRNG availability on the SoC. */ 133 #define FSL_FEATURE_SOC_TRNG_COUNT (1) 134 /* @brief TSI availability on the SoC. */ 135 #define FSL_FEATURE_SOC_TSI_COUNT (1) 136 /* @brief USB availability on the SoC. */ 137 #define FSL_FEATURE_SOC_USB_COUNT (1) 138 /* @brief USBDCD availability on the SoC. */ 139 #define FSL_FEATURE_SOC_USBDCD_COUNT (1) 140 /* @brief VREF availability on the SoC. */ 141 #define FSL_FEATURE_SOC_VREF_COUNT (1) 142 /* @brief WDOG availability on the SoC. */ 143 #define FSL_FEATURE_SOC_WDOG_COUNT (1) 144 145 /* ADC16 module features */ 146 147 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ 148 #define FSL_FEATURE_ADC16_HAS_PGA (0) 149 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ 150 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) 151 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ 152 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) 153 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ 154 #define FSL_FEATURE_ADC16_HAS_DMA (1) 155 /* @brief Has differential mode (bitfield SC1x[DIFF]). */ 156 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) 157 /* @brief Has FIFO (bit SC4[AFDEP]). */ 158 #define FSL_FEATURE_ADC16_HAS_FIFO (0) 159 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ 160 #define FSL_FEATURE_ADC16_FIFO_SIZE (0) 161 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ 162 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) 163 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ 164 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) 165 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ 166 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) 167 /* @brief Has HW averaging (bit SC3[AVGE]). */ 168 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) 169 /* @brief Has offset correction (register OFS). */ 170 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) 171 /* @brief Maximum ADC resolution. */ 172 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) 173 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ 174 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) 175 176 /* CMP module features */ 177 178 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ 179 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) 180 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */ 181 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) 182 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ 183 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) 184 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ 185 #define FSL_FEATURE_CMP_HAS_DMA (1) 186 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ 187 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) 188 /* @brief Has DAC Test function in CMP (register DACTEST). */ 189 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0) 190 191 /* CRC module features */ 192 193 /* @brief Has data register with name CRC */ 194 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 195 196 /* DAC module features */ 197 198 /* @brief Define the size of hardware buffer */ 199 #define FSL_FEATURE_DAC_BUFFER_SIZE (16) 200 /* @brief Define whether the buffer supports watermark event detection or not. */ 201 #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) 202 /* @brief Define whether the buffer supports watermark selection detection or not. */ 203 #define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) 204 /* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ 205 #define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) 206 /* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ 207 #define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) 208 /* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ 209 #define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) 210 /* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ 211 #define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) 212 /* @brief Define whether FIFO buffer mode is available or not. */ 213 #define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (1) 214 /* @brief Define whether swing buffer mode is available or not.. */ 215 #define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1) 216 217 /* EDMA module features */ 218 219 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ 220 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (32) 221 /* @brief Total number of DMA channels on all modules. */ 222 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 32) 223 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ 224 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (2) 225 /* @brief Has DMA_Error interrupt vector. */ 226 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) 227 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ 228 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32) 229 /* @brief Channel IRQ entry shared offset. */ 230 #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (16) 231 /* @brief If 8 bytes transfer supported. */ 232 #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (0) 233 /* @brief If 16 bytes transfer supported. */ 234 #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) 235 236 /* DMAMUX module features */ 237 238 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 239 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32) 240 /* @brief Total number of DMA channels on all modules. */ 241 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 32) 242 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 243 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 244 245 /* EWM module features */ 246 247 /* @brief Has clock select (register CLKCTRL). */ 248 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) 249 /* @brief Has clock prescaler (register CLKPRESCALER). */ 250 #define FSL_FEATURE_EWM_HAS_PRESCALER (1) 251 252 /* FLEXBUS module features */ 253 254 /* No feature definitions */ 255 256 /* FLEXIO module features */ 257 258 /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ 259 #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) 260 /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ 261 #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) 262 /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ 263 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) 264 /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ 265 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) 266 /* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ 267 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) 268 /* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 269 #define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) 270 /* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 271 #define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) 272 /* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ 273 #define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) 274 /* @brief Reset value of the FLEXIO_VERID register */ 275 #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001) 276 /* @brief Reset value of the FLEXIO_PARAM register */ 277 #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x10200808) 278 /* @brief Flexio DMA request base channel */ 279 #define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (16) 280 281 /* FLASH module features */ 282 283 /* @brief Is of type FTFA. */ 284 #define FSL_FEATURE_FLASH_IS_FTFA (1) 285 /* @brief Is of type FTFE. */ 286 #define FSL_FEATURE_FLASH_IS_FTFE (0) 287 /* @brief Is of type FTFL. */ 288 #define FSL_FEATURE_FLASH_IS_FTFL (0) 289 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 290 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) 291 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 292 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 293 /* @brief Has EEPROM region protection (register FEPROT). */ 294 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 295 /* @brief Has data flash region protection (register FDPROT). */ 296 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 297 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 298 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) 299 /* @brief Has flash cache control in FMC module. */ 300 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) 301 /* @brief Has flash cache control in MCM module. */ 302 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) 303 /* @brief Has flash cache control in MSCM module. */ 304 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 305 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 306 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 307 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 308 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 309 /* @brief P-Flash start address. */ 310 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 311 /* @brief P-Flash block count. */ 312 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 313 /* @brief P-Flash block size. */ 314 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144) 315 /* @brief P-Flash sector size. */ 316 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096) 317 /* @brief P-Flash write unit size. */ 318 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 319 /* @brief P-Flash data path width. */ 320 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16) 321 /* @brief P-Flash block swap feature. */ 322 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 323 /* @brief P-Flash protection region count. */ 324 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 325 /* @brief Has FlexNVM memory. */ 326 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 327 /* @brief Has FlexNVM alias. */ 328 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 329 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 330 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 331 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 332 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 333 /* @brief FlexNVM block count. */ 334 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 335 /* @brief FlexNVM block size. */ 336 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 337 /* @brief FlexNVM sector size. */ 338 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 339 /* @brief FlexNVM write unit size. */ 340 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 341 /* @brief FlexNVM data path width. */ 342 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 343 /* @brief Has FlexRAM memory. */ 344 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) 345 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 346 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) 347 /* @brief FlexRAM size. */ 348 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) 349 /* @brief Has 0x00 Read 1s Block command. */ 350 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 351 /* @brief Has 0x01 Read 1s Section command. */ 352 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 353 /* @brief Has 0x02 Program Check command. */ 354 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 355 /* @brief Has 0x03 Read Resource command. */ 356 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 357 /* @brief Has 0x06 Program Longword command. */ 358 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 359 /* @brief Has 0x07 Program Phrase command. */ 360 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 361 /* @brief Has 0x08 Erase Flash Block command. */ 362 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 363 /* @brief Has 0x09 Erase Flash Sector command. */ 364 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 365 /* @brief Has 0x0B Program Section command. */ 366 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) 367 /* @brief Has 0x40 Read 1s All Blocks command. */ 368 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 369 /* @brief Has 0x41 Read Once command. */ 370 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 371 /* @brief Has 0x43 Program Once command. */ 372 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 373 /* @brief Has 0x44 Erase All Blocks command. */ 374 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 375 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 376 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 377 /* @brief Has 0x46 Swap Control command. */ 378 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 379 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 380 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) 381 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 382 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 383 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 384 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 385 /* @brief Has 0x80 Program Partition command. */ 386 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 387 /* @brief Has 0x81 Set FlexRAM Function command. */ 388 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 389 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 390 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16) 391 /* @brief P-Flash Erase sector command address alignment. */ 392 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16) 393 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 394 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16) 395 /* @brief P-Flash Read resource command address alignment. */ 396 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 397 /* @brief P-Flash Program check command address alignment. */ 398 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 399 /* @brief P-Flash Program check command address alignment. */ 400 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 401 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 402 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 403 /* @brief FlexNVM Erase sector command address alignment. */ 404 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 405 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 406 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 407 /* @brief FlexNVM Read resource command address alignment. */ 408 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 409 /* @brief FlexNVM Program check command address alignment. */ 410 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 411 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 412 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU) 413 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 414 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) 415 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 416 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) 417 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 418 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU) 419 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 420 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) 421 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 422 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 423 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 424 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 425 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 426 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 427 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 428 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU) 429 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 430 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) 431 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 432 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) 433 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 434 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU) 435 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 436 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) 437 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 438 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 439 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 440 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 441 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 442 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU) 443 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 444 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 445 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 446 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 447 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 448 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 449 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 450 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) 451 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 452 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) 453 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 454 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) 455 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 456 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) 457 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 458 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) 459 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 460 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) 461 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 462 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) 463 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 464 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 465 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 466 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 467 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 468 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 469 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 470 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 471 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 472 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 473 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 474 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) 475 476 /* FTM module features */ 477 478 /* @brief Number of channels. */ 479 #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ 480 (((x) == FTM0) ? (8) : \ 481 (((x) == FTM1) ? (2) : \ 482 (((x) == FTM2) ? (2) : \ 483 (((x) == FTM3) ? (8) : (-1))))) 484 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 485 #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1) 486 /* @brief Has extended deadtime value. */ 487 #define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0) 488 /* @brief Enable pwm output for the module. */ 489 #define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0) 490 /* @brief Has half-cycle reload for the module. */ 491 #define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0) 492 /* @brief Has reload interrupt. */ 493 #define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0) 494 /* @brief Has reload initialization trigger. */ 495 #define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0) 496 /* @brief Has DMA support, bitfield CnSC[DMA]. */ 497 #define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (1) 498 /* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */ 499 #define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (0) 500 /* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */ 501 #define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (0) 502 /* @brief Has no QDCTRL. */ 503 #define FSL_FEATURE_FTM_HAS_NO_QDCTRL (0) 504 /* @brief If instance has only TPM function. */ 505 #define FSL_FEATURE_FTM_IS_TPM_ONLY_INSTANCEn(x) (0) 506 507 /* GPIO module features */ 508 509 /* @brief Has GPIO attribute checker register (GACR). */ 510 #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) 511 512 /* I2C module features */ 513 514 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ 515 #define FSL_FEATURE_I2C_HAS_SMBUS (1) 516 /* @brief Maximum supported baud rate in kilobit per second. */ 517 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) 518 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ 519 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) 520 /* @brief Has DMA support (register bit C1[DMAEN]). */ 521 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) 522 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ 523 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) 524 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ 525 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) 526 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ 527 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) 528 /* @brief Maximum width of the glitch filter in number of bus clocks. */ 529 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) 530 /* @brief Has control of the drive capability of the I2C pins. */ 531 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) 532 /* @brief Has double buffering support (register S2). */ 533 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1) 534 /* @brief Has double buffer enable. */ 535 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0) 536 537 /* SAI module features */ 538 539 /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ 540 #define FSL_FEATURE_SAI_FIFO_COUNT (8) 541 /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ 542 #define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (2) 543 /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ 544 #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) 545 /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ 546 #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) 547 /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ 548 #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) 549 /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ 550 #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) 551 /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ 552 #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) 553 /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ 554 #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) 555 /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ 556 #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1) 557 /* @brief Ihe interrupt source number */ 558 #define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) 559 /* @brief Has register of MCR. */ 560 #define FSL_FEATURE_SAI_HAS_MCR (1) 561 /* @brief Has register of MDR */ 562 #define FSL_FEATURE_SAI_HAS_MDR (1) 563 /* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ 564 #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) 565 /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ 566 #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (0) 567 568 /* LLWU module features */ 569 570 #if defined(CPU_MK80FN256CAx15) || defined(CPU_MK80FN256VDC15) 571 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 572 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (26) 573 /* @brief Has pins 8-15 connected to LLWU device. */ 574 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 575 /* @brief Maximum number of internal modules connected to LLWU device. */ 576 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) 577 /* @brief Number of digital filters. */ 578 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (4) 579 /* @brief Has MF register. */ 580 #define FSL_FEATURE_LLWU_HAS_MF (1) 581 /* @brief Has PF register. */ 582 #define FSL_FEATURE_LLWU_HAS_PF (1) 583 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 584 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 585 /* @brief Has no internal module wakeup flag register. */ 586 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 587 /* @brief Has external pin 0 connected to LLWU device. */ 588 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 589 /* @brief Index of port of external pin. */ 590 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) 591 /* @brief Number of external pin port on specified port. */ 592 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) 593 /* @brief Has external pin 1 connected to LLWU device. */ 594 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) 595 /* @brief Index of port of external pin. */ 596 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX) 597 /* @brief Number of external pin port on specified port. */ 598 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) 599 /* @brief Has external pin 2 connected to LLWU device. */ 600 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) 601 /* @brief Index of port of external pin. */ 602 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX) 603 /* @brief Number of external pin port on specified port. */ 604 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4) 605 /* @brief Has external pin 3 connected to LLWU device. */ 606 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 607 /* @brief Index of port of external pin. */ 608 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 609 /* @brief Number of external pin port on specified port. */ 610 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 611 /* @brief Has external pin 4 connected to LLWU device. */ 612 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) 613 /* @brief Index of port of external pin. */ 614 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) 615 /* @brief Number of external pin port on specified port. */ 616 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) 617 /* @brief Has external pin 5 connected to LLWU device. */ 618 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 619 /* @brief Index of port of external pin. */ 620 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 621 /* @brief Number of external pin port on specified port. */ 622 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 623 /* @brief Has external pin 6 connected to LLWU device. */ 624 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 625 /* @brief Index of port of external pin. */ 626 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 627 /* @brief Number of external pin port on specified port. */ 628 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 629 /* @brief Has external pin 7 connected to LLWU device. */ 630 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 631 /* @brief Index of port of external pin. */ 632 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 633 /* @brief Number of external pin port on specified port. */ 634 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 635 /* @brief Has external pin 8 connected to LLWU device. */ 636 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 637 /* @brief Index of port of external pin. */ 638 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 639 /* @brief Number of external pin port on specified port. */ 640 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 641 /* @brief Has external pin 9 connected to LLWU device. */ 642 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 643 /* @brief Index of port of external pin. */ 644 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 645 /* @brief Number of external pin port on specified port. */ 646 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 647 /* @brief Has external pin 10 connected to LLWU device. */ 648 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 649 /* @brief Index of port of external pin. */ 650 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 651 /* @brief Number of external pin port on specified port. */ 652 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 653 /* @brief Has external pin 11 connected to LLWU device. */ 654 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) 655 /* @brief Index of port of external pin. */ 656 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) 657 /* @brief Number of external pin port on specified port. */ 658 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) 659 /* @brief Has external pin 12 connected to LLWU device. */ 660 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 661 /* @brief Index of port of external pin. */ 662 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) 663 /* @brief Number of external pin port on specified port. */ 664 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 665 /* @brief Has external pin 13 connected to LLWU device. */ 666 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 667 /* @brief Index of port of external pin. */ 668 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) 669 /* @brief Number of external pin port on specified port. */ 670 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) 671 /* @brief Has external pin 14 connected to LLWU device. */ 672 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 673 /* @brief Index of port of external pin. */ 674 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 675 /* @brief Number of external pin port on specified port. */ 676 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 677 /* @brief Has external pin 15 connected to LLWU device. */ 678 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 679 /* @brief Index of port of external pin. */ 680 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 681 /* @brief Number of external pin port on specified port. */ 682 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 683 /* @brief Has external pin 16 connected to LLWU device. */ 684 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1) 685 /* @brief Index of port of external pin. */ 686 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOE_IDX) 687 /* @brief Number of external pin port on specified port. */ 688 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (6) 689 /* @brief Has external pin 17 connected to LLWU device. */ 690 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1) 691 /* @brief Index of port of external pin. */ 692 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOE_IDX) 693 /* @brief Number of external pin port on specified port. */ 694 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (9) 695 /* @brief Has external pin 18 connected to LLWU device. */ 696 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (1) 697 /* @brief Index of port of external pin. */ 698 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (GPIOE_IDX) 699 /* @brief Number of external pin port on specified port. */ 700 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (10) 701 /* @brief Has external pin 19 connected to LLWU device. */ 702 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) 703 /* @brief Index of port of external pin. */ 704 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) 705 /* @brief Number of external pin port on specified port. */ 706 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) 707 /* @brief Has external pin 20 connected to LLWU device. */ 708 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) 709 /* @brief Index of port of external pin. */ 710 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) 711 /* @brief Number of external pin port on specified port. */ 712 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) 713 /* @brief Has external pin 21 connected to LLWU device. */ 714 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1) 715 /* @brief Index of port of external pin. */ 716 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOA_IDX) 717 /* @brief Number of external pin port on specified port. */ 718 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (21) 719 /* @brief Has external pin 22 connected to LLWU device. */ 720 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (1) 721 /* @brief Index of port of external pin. */ 722 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (GPIOA_IDX) 723 /* @brief Number of external pin port on specified port. */ 724 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (10) 725 /* @brief Has external pin 23 connected to LLWU device. */ 726 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (1) 727 /* @brief Index of port of external pin. */ 728 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (GPIOA_IDX) 729 /* @brief Number of external pin port on specified port. */ 730 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (11) 731 /* @brief Has external pin 24 connected to LLWU device. */ 732 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (1) 733 /* @brief Index of port of external pin. */ 734 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (GPIOD_IDX) 735 /* @brief Number of external pin port on specified port. */ 736 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (8) 737 /* @brief Has external pin 25 connected to LLWU device. */ 738 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (1) 739 /* @brief Index of port of external pin. */ 740 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (GPIOD_IDX) 741 /* @brief Number of external pin port on specified port. */ 742 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (11) 743 /* @brief Has external pin 26 connected to LLWU device. */ 744 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 745 /* @brief Index of port of external pin. */ 746 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 747 /* @brief Number of external pin port on specified port. */ 748 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 749 /* @brief Has external pin 27 connected to LLWU device. */ 750 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 751 /* @brief Index of port of external pin. */ 752 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 753 /* @brief Number of external pin port on specified port. */ 754 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 755 /* @brief Has external pin 28 connected to LLWU device. */ 756 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 757 /* @brief Index of port of external pin. */ 758 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 759 /* @brief Number of external pin port on specified port. */ 760 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 761 /* @brief Has external pin 29 connected to LLWU device. */ 762 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 763 /* @brief Index of port of external pin. */ 764 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 765 /* @brief Number of external pin port on specified port. */ 766 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 767 /* @brief Has external pin 30 connected to LLWU device. */ 768 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 769 /* @brief Index of port of external pin. */ 770 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 771 /* @brief Number of external pin port on specified port. */ 772 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 773 /* @brief Has external pin 31 connected to LLWU device. */ 774 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 775 /* @brief Index of port of external pin. */ 776 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 777 /* @brief Number of external pin port on specified port. */ 778 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 779 /* @brief Has internal module 0 connected to LLWU device. */ 780 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 781 /* @brief Has internal module 1 connected to LLWU device. */ 782 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 783 /* @brief Has internal module 2 connected to LLWU device. */ 784 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 785 /* @brief Has internal module 3 connected to LLWU device. */ 786 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) 787 /* @brief Has internal module 4 connected to LLWU device. */ 788 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) 789 /* @brief Has internal module 5 connected to LLWU device. */ 790 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) 791 /* @brief Has internal module 6 connected to LLWU device. */ 792 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 793 /* @brief Has internal module 7 connected to LLWU device. */ 794 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) 795 /* @brief Has Version ID Register (LLWU_VERID). */ 796 #define FSL_FEATURE_LLWU_HAS_VERID (0) 797 /* @brief Has Parameter Register (LLWU_PARAM). */ 798 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 799 /* @brief Width of registers of the LLWU. */ 800 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 801 /* @brief Has DMA Enable register (LLWU_DE). */ 802 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 803 #elif defined(CPU_MK80FN256VLL15) 804 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 805 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (19) 806 /* @brief Has pins 8-15 connected to LLWU device. */ 807 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 808 /* @brief Maximum number of internal modules connected to LLWU device. */ 809 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) 810 /* @brief Number of digital filters. */ 811 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (4) 812 /* @brief Has MF register. */ 813 #define FSL_FEATURE_LLWU_HAS_MF (1) 814 /* @brief Has PF register. */ 815 #define FSL_FEATURE_LLWU_HAS_PF (1) 816 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 817 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 818 /* @brief Has no internal module wakeup flag register. */ 819 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 820 /* @brief Has external pin 0 connected to LLWU device. */ 821 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 822 /* @brief Index of port of external pin. */ 823 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) 824 /* @brief Number of external pin port on specified port. */ 825 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) 826 /* @brief Has external pin 1 connected to LLWU device. */ 827 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) 828 /* @brief Index of port of external pin. */ 829 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX) 830 /* @brief Number of external pin port on specified port. */ 831 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) 832 /* @brief Has external pin 2 connected to LLWU device. */ 833 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) 834 /* @brief Index of port of external pin. */ 835 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX) 836 /* @brief Number of external pin port on specified port. */ 837 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4) 838 /* @brief Has external pin 3 connected to LLWU device. */ 839 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 840 /* @brief Index of port of external pin. */ 841 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 842 /* @brief Number of external pin port on specified port. */ 843 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 844 /* @brief Has external pin 4 connected to LLWU device. */ 845 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) 846 /* @brief Index of port of external pin. */ 847 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) 848 /* @brief Number of external pin port on specified port. */ 849 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) 850 /* @brief Has external pin 5 connected to LLWU device. */ 851 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 852 /* @brief Index of port of external pin. */ 853 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 854 /* @brief Number of external pin port on specified port. */ 855 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 856 /* @brief Has external pin 6 connected to LLWU device. */ 857 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 858 /* @brief Index of port of external pin. */ 859 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 860 /* @brief Number of external pin port on specified port. */ 861 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 862 /* @brief Has external pin 7 connected to LLWU device. */ 863 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 864 /* @brief Index of port of external pin. */ 865 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 866 /* @brief Number of external pin port on specified port. */ 867 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 868 /* @brief Has external pin 8 connected to LLWU device. */ 869 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 870 /* @brief Index of port of external pin. */ 871 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 872 /* @brief Number of external pin port on specified port. */ 873 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 874 /* @brief Has external pin 9 connected to LLWU device. */ 875 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 876 /* @brief Index of port of external pin. */ 877 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 878 /* @brief Number of external pin port on specified port. */ 879 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 880 /* @brief Has external pin 10 connected to LLWU device. */ 881 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 882 /* @brief Index of port of external pin. */ 883 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 884 /* @brief Number of external pin port on specified port. */ 885 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 886 /* @brief Has external pin 11 connected to LLWU device. */ 887 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) 888 /* @brief Index of port of external pin. */ 889 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) 890 /* @brief Number of external pin port on specified port. */ 891 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) 892 /* @brief Has external pin 12 connected to LLWU device. */ 893 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 894 /* @brief Index of port of external pin. */ 895 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) 896 /* @brief Number of external pin port on specified port. */ 897 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 898 /* @brief Has external pin 13 connected to LLWU device. */ 899 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 900 /* @brief Index of port of external pin. */ 901 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) 902 /* @brief Number of external pin port on specified port. */ 903 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) 904 /* @brief Has external pin 14 connected to LLWU device. */ 905 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 906 /* @brief Index of port of external pin. */ 907 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 908 /* @brief Number of external pin port on specified port. */ 909 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 910 /* @brief Has external pin 15 connected to LLWU device. */ 911 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 912 /* @brief Index of port of external pin. */ 913 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 914 /* @brief Number of external pin port on specified port. */ 915 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 916 /* @brief Has external pin 16 connected to LLWU device. */ 917 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1) 918 /* @brief Index of port of external pin. */ 919 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOE_IDX) 920 /* @brief Number of external pin port on specified port. */ 921 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (6) 922 /* @brief Has external pin 17 connected to LLWU device. */ 923 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1) 924 /* @brief Index of port of external pin. */ 925 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOE_IDX) 926 /* @brief Number of external pin port on specified port. */ 927 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (9) 928 /* @brief Has external pin 18 connected to LLWU device. */ 929 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (1) 930 /* @brief Index of port of external pin. */ 931 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (GPIOE_IDX) 932 /* @brief Number of external pin port on specified port. */ 933 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (10) 934 /* @brief Has external pin 19 connected to LLWU device. */ 935 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) 936 /* @brief Index of port of external pin. */ 937 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) 938 /* @brief Number of external pin port on specified port. */ 939 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) 940 /* @brief Has external pin 20 connected to LLWU device. */ 941 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) 942 /* @brief Index of port of external pin. */ 943 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) 944 /* @brief Number of external pin port on specified port. */ 945 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) 946 /* @brief Has external pin 21 connected to LLWU device. */ 947 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) 948 /* @brief Index of port of external pin. */ 949 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) 950 /* @brief Number of external pin port on specified port. */ 951 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) 952 /* @brief Has external pin 22 connected to LLWU device. */ 953 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 954 /* @brief Index of port of external pin. */ 955 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 956 /* @brief Number of external pin port on specified port. */ 957 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 958 /* @brief Has external pin 23 connected to LLWU device. */ 959 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 960 /* @brief Index of port of external pin. */ 961 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 962 /* @brief Number of external pin port on specified port. */ 963 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 964 /* @brief Has external pin 24 connected to LLWU device. */ 965 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 966 /* @brief Index of port of external pin. */ 967 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 968 /* @brief Number of external pin port on specified port. */ 969 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 970 /* @brief Has external pin 25 connected to LLWU device. */ 971 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 972 /* @brief Index of port of external pin. */ 973 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 974 /* @brief Number of external pin port on specified port. */ 975 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 976 /* @brief Has external pin 26 connected to LLWU device. */ 977 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 978 /* @brief Index of port of external pin. */ 979 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 980 /* @brief Number of external pin port on specified port. */ 981 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 982 /* @brief Has external pin 27 connected to LLWU device. */ 983 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 984 /* @brief Index of port of external pin. */ 985 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 986 /* @brief Number of external pin port on specified port. */ 987 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 988 /* @brief Has external pin 28 connected to LLWU device. */ 989 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 990 /* @brief Index of port of external pin. */ 991 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 992 /* @brief Number of external pin port on specified port. */ 993 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 994 /* @brief Has external pin 29 connected to LLWU device. */ 995 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 996 /* @brief Index of port of external pin. */ 997 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 998 /* @brief Number of external pin port on specified port. */ 999 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 1000 /* @brief Has external pin 30 connected to LLWU device. */ 1001 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 1002 /* @brief Index of port of external pin. */ 1003 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 1004 /* @brief Number of external pin port on specified port. */ 1005 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 1006 /* @brief Has external pin 31 connected to LLWU device. */ 1007 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 1008 /* @brief Index of port of external pin. */ 1009 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 1010 /* @brief Number of external pin port on specified port. */ 1011 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 1012 /* @brief Has internal module 0 connected to LLWU device. */ 1013 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 1014 /* @brief Has internal module 1 connected to LLWU device. */ 1015 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 1016 /* @brief Has internal module 2 connected to LLWU device. */ 1017 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 1018 /* @brief Has internal module 3 connected to LLWU device. */ 1019 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) 1020 /* @brief Has internal module 4 connected to LLWU device. */ 1021 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) 1022 /* @brief Has internal module 5 connected to LLWU device. */ 1023 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) 1024 /* @brief Has internal module 6 connected to LLWU device. */ 1025 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 1026 /* @brief Has internal module 7 connected to LLWU device. */ 1027 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) 1028 /* @brief Has Version ID Register (LLWU_VERID). */ 1029 #define FSL_FEATURE_LLWU_HAS_VERID (0) 1030 /* @brief Has Parameter Register (LLWU_PARAM). */ 1031 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 1032 /* @brief Width of registers of the LLWU. */ 1033 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 1034 /* @brief Has DMA Enable register (LLWU_DE). */ 1035 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 1036 #elif defined(CPU_MK80FN256VLQ15) 1037 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 1038 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (26) 1039 /* @brief Has pins 8-15 connected to LLWU device. */ 1040 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 1041 /* @brief Maximum number of internal modules connected to LLWU device. */ 1042 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) 1043 /* @brief Number of digital filters. */ 1044 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (4) 1045 /* @brief Has MF register. */ 1046 #define FSL_FEATURE_LLWU_HAS_MF (1) 1047 /* @brief Has PF register. */ 1048 #define FSL_FEATURE_LLWU_HAS_PF (1) 1049 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 1050 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 1051 /* @brief Has no internal module wakeup flag register. */ 1052 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 1053 /* @brief Has external pin 0 connected to LLWU device. */ 1054 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 1055 /* @brief Index of port of external pin. */ 1056 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) 1057 /* @brief Number of external pin port on specified port. */ 1058 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) 1059 /* @brief Has external pin 1 connected to LLWU device. */ 1060 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) 1061 /* @brief Index of port of external pin. */ 1062 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX) 1063 /* @brief Number of external pin port on specified port. */ 1064 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) 1065 /* @brief Has external pin 2 connected to LLWU device. */ 1066 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) 1067 /* @brief Index of port of external pin. */ 1068 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX) 1069 /* @brief Number of external pin port on specified port. */ 1070 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4) 1071 /* @brief Has external pin 3 connected to LLWU device. */ 1072 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 1073 /* @brief Index of port of external pin. */ 1074 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 1075 /* @brief Number of external pin port on specified port. */ 1076 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 1077 /* @brief Has external pin 4 connected to LLWU device. */ 1078 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) 1079 /* @brief Index of port of external pin. */ 1080 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) 1081 /* @brief Number of external pin port on specified port. */ 1082 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) 1083 /* @brief Has external pin 5 connected to LLWU device. */ 1084 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 1085 /* @brief Index of port of external pin. */ 1086 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 1087 /* @brief Number of external pin port on specified port. */ 1088 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 1089 /* @brief Has external pin 6 connected to LLWU device. */ 1090 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 1091 /* @brief Index of port of external pin. */ 1092 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 1093 /* @brief Number of external pin port on specified port. */ 1094 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 1095 /* @brief Has external pin 7 connected to LLWU device. */ 1096 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 1097 /* @brief Index of port of external pin. */ 1098 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 1099 /* @brief Number of external pin port on specified port. */ 1100 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 1101 /* @brief Has external pin 8 connected to LLWU device. */ 1102 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 1103 /* @brief Index of port of external pin. */ 1104 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 1105 /* @brief Number of external pin port on specified port. */ 1106 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 1107 /* @brief Has external pin 9 connected to LLWU device. */ 1108 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 1109 /* @brief Index of port of external pin. */ 1110 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 1111 /* @brief Number of external pin port on specified port. */ 1112 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 1113 /* @brief Has external pin 10 connected to LLWU device. */ 1114 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 1115 /* @brief Index of port of external pin. */ 1116 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 1117 /* @brief Number of external pin port on specified port. */ 1118 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 1119 /* @brief Has external pin 11 connected to LLWU device. */ 1120 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) 1121 /* @brief Index of port of external pin. */ 1122 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) 1123 /* @brief Number of external pin port on specified port. */ 1124 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) 1125 /* @brief Has external pin 12 connected to LLWU device. */ 1126 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 1127 /* @brief Index of port of external pin. */ 1128 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) 1129 /* @brief Number of external pin port on specified port. */ 1130 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 1131 /* @brief Has external pin 13 connected to LLWU device. */ 1132 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 1133 /* @brief Index of port of external pin. */ 1134 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) 1135 /* @brief Number of external pin port on specified port. */ 1136 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) 1137 /* @brief Has external pin 14 connected to LLWU device. */ 1138 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 1139 /* @brief Index of port of external pin. */ 1140 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 1141 /* @brief Number of external pin port on specified port. */ 1142 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 1143 /* @brief Has external pin 15 connected to LLWU device. */ 1144 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 1145 /* @brief Index of port of external pin. */ 1146 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 1147 /* @brief Number of external pin port on specified port. */ 1148 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 1149 /* @brief Has external pin 16 connected to LLWU device. */ 1150 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1) 1151 /* @brief Index of port of external pin. */ 1152 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOE_IDX) 1153 /* @brief Number of external pin port on specified port. */ 1154 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (6) 1155 /* @brief Has external pin 17 connected to LLWU device. */ 1156 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1) 1157 /* @brief Index of port of external pin. */ 1158 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOE_IDX) 1159 /* @brief Number of external pin port on specified port. */ 1160 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (9) 1161 /* @brief Has external pin 18 connected to LLWU device. */ 1162 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (1) 1163 /* @brief Index of port of external pin. */ 1164 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (GPIOE_IDX) 1165 /* @brief Number of external pin port on specified port. */ 1166 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (10) 1167 /* @brief Has external pin 19 connected to LLWU device. */ 1168 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1) 1169 /* @brief Index of port of external pin. */ 1170 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOE_IDX) 1171 /* @brief Number of external pin port on specified port. */ 1172 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (17) 1173 /* @brief Has external pin 20 connected to LLWU device. */ 1174 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1) 1175 /* @brief Index of port of external pin. */ 1176 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOE_IDX) 1177 /* @brief Number of external pin port on specified port. */ 1178 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (18) 1179 /* @brief Has external pin 21 connected to LLWU device. */ 1180 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1) 1181 /* @brief Index of port of external pin. */ 1182 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOA_IDX) 1183 /* @brief Number of external pin port on specified port. */ 1184 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (21) 1185 /* @brief Has external pin 22 connected to LLWU device. */ 1186 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (1) 1187 /* @brief Index of port of external pin. */ 1188 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (GPIOA_IDX) 1189 /* @brief Number of external pin port on specified port. */ 1190 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (10) 1191 /* @brief Has external pin 23 connected to LLWU device. */ 1192 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (1) 1193 /* @brief Index of port of external pin. */ 1194 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (GPIOA_IDX) 1195 /* @brief Number of external pin port on specified port. */ 1196 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (11) 1197 /* @brief Has external pin 24 connected to LLWU device. */ 1198 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (1) 1199 /* @brief Index of port of external pin. */ 1200 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (GPIOD_IDX) 1201 /* @brief Number of external pin port on specified port. */ 1202 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (8) 1203 /* @brief Has external pin 25 connected to LLWU device. */ 1204 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (1) 1205 /* @brief Index of port of external pin. */ 1206 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (GPIOD_IDX) 1207 /* @brief Number of external pin port on specified port. */ 1208 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (11) 1209 /* @brief Has external pin 26 connected to LLWU device. */ 1210 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 1211 /* @brief Index of port of external pin. */ 1212 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 1213 /* @brief Number of external pin port on specified port. */ 1214 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 1215 /* @brief Has external pin 27 connected to LLWU device. */ 1216 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 1217 /* @brief Index of port of external pin. */ 1218 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 1219 /* @brief Number of external pin port on specified port. */ 1220 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 1221 /* @brief Has external pin 28 connected to LLWU device. */ 1222 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 1223 /* @brief Index of port of external pin. */ 1224 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 1225 /* @brief Number of external pin port on specified port. */ 1226 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 1227 /* @brief Has external pin 29 connected to LLWU device. */ 1228 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 1229 /* @brief Index of port of external pin. */ 1230 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 1231 /* @brief Number of external pin port on specified port. */ 1232 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 1233 /* @brief Has external pin 30 connected to LLWU device. */ 1234 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 1235 /* @brief Index of port of external pin. */ 1236 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 1237 /* @brief Number of external pin port on specified port. */ 1238 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 1239 /* @brief Has external pin 31 connected to LLWU device. */ 1240 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 1241 /* @brief Index of port of external pin. */ 1242 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 1243 /* @brief Number of external pin port on specified port. */ 1244 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 1245 /* @brief Has internal module 0 connected to LLWU device. */ 1246 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 1247 /* @brief Has internal module 1 connected to LLWU device. */ 1248 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 1249 /* @brief Has internal module 2 connected to LLWU device. */ 1250 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 1251 /* @brief Has internal module 3 connected to LLWU device. */ 1252 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) 1253 /* @brief Has internal module 4 connected to LLWU device. */ 1254 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) 1255 /* @brief Has internal module 5 connected to LLWU device. */ 1256 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) 1257 /* @brief Has internal module 6 connected to LLWU device. */ 1258 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 1259 /* @brief Has internal module 7 connected to LLWU device. */ 1260 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) 1261 /* @brief Has Version ID Register (LLWU_VERID). */ 1262 #define FSL_FEATURE_LLWU_HAS_VERID (0) 1263 /* @brief Has Parameter Register (LLWU_PARAM). */ 1264 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 1265 /* @brief Width of registers of the LLWU. */ 1266 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 1267 /* @brief Has DMA Enable register (LLWU_DE). */ 1268 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 1269 #endif /* defined(CPU_MK80FN256CAx15) || defined(CPU_MK80FN256VDC15) */ 1270 1271 /* LMEM module features */ 1272 1273 /* @brief Has process identifier support. */ 1274 #define FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE (1) 1275 /* @brief Has L1 cache. */ 1276 #define FSL_FEATURE_HAS_L1CACHE (1) 1277 /* @brief L1 ICACHE line size in byte. */ 1278 #define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (16) 1279 /* @brief L1 DCACHE line size in byte. */ 1280 #define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (16) 1281 1282 /* LPTMR module features */ 1283 1284 /* @brief Has shared interrupt handler with another LPTMR module. */ 1285 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (1) 1286 /* @brief Whether LPTMR counter is 32 bits width. */ 1287 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) 1288 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ 1289 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) 1290 1291 /* LPUART module features */ 1292 1293 /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ 1294 #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) 1295 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 1296 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 1297 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 1298 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) 1299 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 1300 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 1301 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1302 #define FSL_FEATURE_LPUART_HAS_FIFO (1) 1303 /* @brief Has 32-bit register MODIR */ 1304 #define FSL_FEATURE_LPUART_HAS_MODIR (1) 1305 /* @brief Hardware flow control (RTS, CTS) is supported. */ 1306 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) 1307 /* @brief Infrared (modulation) is supported. */ 1308 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) 1309 /* @brief 2 bits long stop bit is available. */ 1310 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 1311 /* @brief If 10-bit mode is supported. */ 1312 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) 1313 /* @brief If 7-bit mode is supported. */ 1314 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0) 1315 /* @brief Baud rate fine adjustment is available. */ 1316 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 1317 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 1318 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) 1319 /* @brief Baud rate oversampling is available. */ 1320 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) 1321 /* @brief Baud rate oversampling is available. */ 1322 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 1323 /* @brief Peripheral type. */ 1324 #define FSL_FEATURE_LPUART_IS_SCI (1) 1325 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1326 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) \ 1327 (((x) == LPUART0) ? (8) : \ 1328 (((x) == LPUART1) ? (8) : \ 1329 (((x) == LPUART2) ? (1) : \ 1330 (((x) == LPUART3) ? (1) : \ 1331 (((x) == LPUART4) ? (1) : (-1)))))) 1332 /* @brief Maximal data width without parity bit. */ 1333 #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) 1334 /* @brief Maximal data width with parity bit. */ 1335 #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) 1336 /* @brief Supports two match addresses to filter incoming frames. */ 1337 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) 1338 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 1339 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) 1340 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 1341 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) 1342 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 1343 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) 1344 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 1345 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) 1346 /* @brief Has improved smart card (ISO7816 protocol) support. */ 1347 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 1348 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 1349 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 1350 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 1351 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) 1352 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ 1353 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) 1354 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 1355 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) 1356 /* @brief Has separate DMA RX and TX requests. */ 1357 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1358 /* @brief Has separate RX and TX interrupts. */ 1359 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) 1360 /* @brief Has LPAURT_PARAM. */ 1361 #define FSL_FEATURE_LPUART_HAS_PARAM (0) 1362 /* @brief Has LPUART_VERID. */ 1363 #define FSL_FEATURE_LPUART_HAS_VERID (0) 1364 /* @brief Has LPUART_GLOBAL. */ 1365 #define FSL_FEATURE_LPUART_HAS_GLOBAL (0) 1366 /* @brief Has LPUART_PINCFG. */ 1367 #define FSL_FEATURE_LPUART_HAS_PINCFG (0) 1368 1369 /* MCG module features */ 1370 1371 /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ 1372 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1) 1373 /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ 1374 #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (7) 1375 /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ 1376 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (16) 1377 /* @brief PLL reference clock low range. OSCCLK/PLL_R. */ 1378 #define FSL_FEATURE_MCG_PLL_REF_MIN (8000000) 1379 /* @brief PLL reference clock high range. OSCCLK/PLL_R. */ 1380 #define FSL_FEATURE_MCG_PLL_REF_MAX (16000000) 1381 /* @brief The PLL clock is divided by 2 before VCO divider. */ 1382 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (1) 1383 /* @brief FRDIV supports 1280. */ 1384 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) 1385 /* @brief FRDIV supports 1536. */ 1386 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) 1387 /* @brief MCGFFCLK divider. */ 1388 #define FSL_FEATURE_MCG_FFCLK_DIV (1) 1389 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ 1390 #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) 1391 /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ 1392 #define FSL_FEATURE_MCG_HAS_RTC_32K (1) 1393 /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ 1394 #define FSL_FEATURE_MCG_HAS_PLL1 (0) 1395 /* @brief Has 48MHz internal oscillator. */ 1396 #define FSL_FEATURE_MCG_HAS_IRC_48M (1) 1397 /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ 1398 #define FSL_FEATURE_MCG_HAS_OSC1 (0) 1399 /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ 1400 #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) 1401 /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ 1402 #define FSL_FEATURE_MCG_HAS_LOLRE (1) 1403 /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ 1404 #define FSL_FEATURE_MCG_USE_OSCSEL (1) 1405 /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ 1406 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) 1407 /* @brief TBD */ 1408 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) 1409 /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */ 1410 #define FSL_FEATURE_MCG_HAS_PLL (1) 1411 /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ 1412 #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1) 1413 /* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ 1414 #define FSL_FEATURE_MCG_HAS_PLL_VDIV (1) 1415 /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ 1416 #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) 1417 /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ 1418 #define FSL_FEATURE_MCG_HAS_FLL (1) 1419 /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ 1420 #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) 1421 /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ 1422 #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) 1423 /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ 1424 #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) 1425 /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ 1426 #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) 1427 /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ 1428 #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) 1429 /* @brief Has external clock monitor (register bit C6[CME]). */ 1430 #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) 1431 /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ 1432 #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) 1433 /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ 1434 #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) 1435 /* @brief Has PEI mode or PBI mode. */ 1436 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) 1437 /* @brief Reset clock mode is BLPI. */ 1438 #define FSL_FEATURE_MCG_RESET_IS_BLPI (0) 1439 1440 /* interrupt module features */ 1441 1442 /* @brief Lowest interrupt request number. */ 1443 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 1444 /* @brief Highest interrupt request number. */ 1445 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (100) 1446 1447 /* OSC module features */ 1448 1449 /* @brief Has OSC1 external oscillator. */ 1450 #define FSL_FEATURE_OSC_HAS_OSC1 (0) 1451 /* @brief Has OSC0 external oscillator. */ 1452 #define FSL_FEATURE_OSC_HAS_OSC0 (0) 1453 /* @brief Has OSC external oscillator (without index). */ 1454 #define FSL_FEATURE_OSC_HAS_OSC (1) 1455 /* @brief Number of OSC external oscillators. */ 1456 #define FSL_FEATURE_OSC_OSC_COUNT (1) 1457 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ 1458 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (1) 1459 1460 /* PDB module features */ 1461 1462 /* @brief Has DAC support. */ 1463 #define FSL_FEATURE_PDB_HAS_DAC (1) 1464 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 1465 #define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0) 1466 /* @brief PDB channel number). */ 1467 #define FSL_FEATURE_PDB_CHANNEL_COUNT (1) 1468 /* @brief Channel pre-trigger nunmber (related to number of registers CHmDLYn). */ 1469 #define FSL_FEATURE_PDB_CHANNEL_PRE_TRIGGER_COUNT (2) 1470 /* @brief DAC interval trigger number). */ 1471 #define FSL_FEATURE_PDB_DAC_INTERVAL_TRIGGER_COUNT (1) 1472 /* @brief Pulse out number). */ 1473 #define FSL_FEATURE_PDB_PULSE_OUT_COUNT (2) 1474 1475 /* PIT module features */ 1476 1477 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 1478 #define FSL_FEATURE_PIT_TIMER_COUNT (4) 1479 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 1480 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) 1481 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ 1482 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) 1483 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 1484 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0) 1485 /* @brief Has timer enable control. */ 1486 #define FSL_FEATURE_PIT_HAS_MDIS (1) 1487 1488 /* PMC module features */ 1489 1490 /* @brief Has Bandgap Enable In VLPx Operation support. */ 1491 #define FSL_FEATURE_PMC_HAS_BGEN (1) 1492 /* @brief Has Bandgap Buffer Enable. */ 1493 #define FSL_FEATURE_PMC_HAS_BGBE (1) 1494 /* @brief Has Bandgap Buffer Drive Select. */ 1495 #define FSL_FEATURE_PMC_HAS_BGBDS (0) 1496 /* @brief Has Low-Voltage Detect Voltage Select support. */ 1497 #define FSL_FEATURE_PMC_HAS_LVDV (1) 1498 /* @brief Has Low-Voltage Warning Voltage Select support. */ 1499 #define FSL_FEATURE_PMC_HAS_LVWV (1) 1500 /* @brief Has LPO. */ 1501 #define FSL_FEATURE_PMC_HAS_LPO (0) 1502 /* @brief Has VLPx option PMC_REGSC[VLPO]. */ 1503 #define FSL_FEATURE_PMC_HAS_VLPO (0) 1504 /* @brief Has acknowledge isolation support. */ 1505 #define FSL_FEATURE_PMC_HAS_ACKISO (1) 1506 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ 1507 #define FSL_FEATURE_PMC_HAS_REGFPM (0) 1508 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ 1509 #define FSL_FEATURE_PMC_HAS_REGONS (1) 1510 /* @brief Has PMC_HVDSC1. */ 1511 #define FSL_FEATURE_PMC_HAS_HVDSC1 (1) 1512 /* @brief Has PMC_PARAM. */ 1513 #define FSL_FEATURE_PMC_HAS_PARAM (0) 1514 /* @brief Has PMC_VERID. */ 1515 #define FSL_FEATURE_PMC_HAS_VERID (0) 1516 1517 /* PORT module features */ 1518 1519 /* @brief Has control lock (register bit PCR[LK]). */ 1520 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) 1521 /* @brief Has open drain control (register bit PCR[ODE]). */ 1522 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) 1523 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ 1524 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) 1525 /* @brief Has DMA request (register bit field PCR[IRQC] values). */ 1526 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) 1527 /* @brief Has pull resistor selection available. */ 1528 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) 1529 /* @brief Has pull resistor enable (register bit PCR[PE]). */ 1530 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) 1531 /* @brief Has slew rate control (register bit PCR[SRE]). */ 1532 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) 1533 /* @brief Has passive filter (register bit field PCR[PFE]). */ 1534 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) 1535 /* @brief Has drive strength control (register bit PCR[DSE]). */ 1536 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) 1537 /* @brief Has separate drive strength register (HDRVE). */ 1538 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) 1539 /* @brief Has glitch filter (register IOFLT). */ 1540 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) 1541 /* @brief Defines width of PCR[MUX] field. */ 1542 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) 1543 /* @brief Has dedicated interrupt vector. */ 1544 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) 1545 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ 1546 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) 1547 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ 1548 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) 1549 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ 1550 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) 1551 1552 /* QSPI module features */ 1553 1554 /* @brief QSPI lookup table depth. */ 1555 #define FSL_FEATURE_QSPI_LUT_DEPTH (64) 1556 /* @brief QSPI Tx FIFO depth. */ 1557 #define FSL_FEATURE_QSPI_TXFIFO_DEPTH (16) 1558 /* @brief QSPI Rx FIFO depth. */ 1559 #define FSL_FEATURE_QSPI_RXFIFO_DEPTH (16) 1560 /* @brief QSPI AHB buffer count. */ 1561 #define FSL_FEATURE_QSPI_AHB_BUFFER_COUNT (4) 1562 /* @brief QSPI AHB buffer size in byte. */ 1563 #define FSL_FEATURE_QSPI_AHB_BUFFER_SIZE (512U) 1564 /* @brief QSPI AMBA base address. */ 1565 #define FSL_FEATURE_QSPI_AMBA_BASE (0x68000000U) 1566 /* @brief QSPI AHB buffer ARDB base address. */ 1567 #define FSL_FEATURE_QSPI_ARDB_BASE (0x67000000U) 1568 /* @brief QSPI has command usage error flag. */ 1569 #define FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR (1) 1570 /* @brief QSPI support parallel mode. */ 1571 #define FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE (1) 1572 /* @brief QSPI support dual die. */ 1573 #define FSL_FEATURE_QSPI_SUPPORT_DUAL_DIE (1) 1574 1575 /* RCM module features */ 1576 1577 /* @brief Has Loss-of-Lock Reset support. */ 1578 #define FSL_FEATURE_RCM_HAS_LOL (1) 1579 /* @brief Has Loss-of-Clock Reset support. */ 1580 #define FSL_FEATURE_RCM_HAS_LOC (1) 1581 /* @brief Has JTAG generated Reset support. */ 1582 #define FSL_FEATURE_RCM_HAS_JTAG (1) 1583 /* @brief Has EzPort generated Reset support. */ 1584 #define FSL_FEATURE_RCM_HAS_EZPORT (0) 1585 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ 1586 #define FSL_FEATURE_RCM_HAS_EZPMS (0) 1587 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ 1588 #define FSL_FEATURE_RCM_HAS_BOOTROM (1) 1589 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ 1590 #define FSL_FEATURE_RCM_HAS_SSRS (1) 1591 /* @brief Has Version ID Register (RCM_VERID). */ 1592 #define FSL_FEATURE_RCM_HAS_VERID (0) 1593 /* @brief Has Parameter Register (RCM_PARAM). */ 1594 #define FSL_FEATURE_RCM_HAS_PARAM (0) 1595 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ 1596 #define FSL_FEATURE_RCM_HAS_SRIE (0) 1597 /* @brief Width of registers of the RCM. */ 1598 #define FSL_FEATURE_RCM_REG_WIDTH (8) 1599 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ 1600 #define FSL_FEATURE_RCM_HAS_CORE1 (0) 1601 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ 1602 #define FSL_FEATURE_RCM_HAS_MDM_AP (1) 1603 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ 1604 #define FSL_FEATURE_RCM_HAS_WAKEUP (1) 1605 1606 /* RTC module features */ 1607 1608 /* @brief Has wakeup pin. */ 1609 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) 1610 /* @brief Has wakeup pin selection (bit field CR[WPS]). */ 1611 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) 1612 /* @brief Has low power features (registers MER, MCLR and MCHR). */ 1613 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) 1614 /* @brief Has read/write access control (registers WAR and RAR). */ 1615 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) 1616 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ 1617 #define FSL_FEATURE_RTC_HAS_SECURITY (1) 1618 /* @brief Has RTC_CLKIN available. */ 1619 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) 1620 /* @brief Has prescaler adjust for LPO. */ 1621 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) 1622 /* @brief Has Clock Pin Enable field. */ 1623 #define FSL_FEATURE_RTC_HAS_CPE (0) 1624 /* @brief Has Timer Seconds Interrupt Configuration field. */ 1625 #define FSL_FEATURE_RTC_HAS_TSIC (0) 1626 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ 1627 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) 1628 /* @brief Has Tamper Interrupt Register (register TIR). */ 1629 #define FSL_FEATURE_RTC_HAS_TIR (0) 1630 /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ 1631 #define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) 1632 /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ 1633 #define FSL_FEATURE_RTC_HAS_TIR_SIE (0) 1634 /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ 1635 #define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) 1636 /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ 1637 #define FSL_FEATURE_RTC_HAS_SR_TIDF (0) 1638 /* @brief Has Tamper Detect Register (register TDR). */ 1639 #define FSL_FEATURE_RTC_HAS_TDR (0) 1640 /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ 1641 #define FSL_FEATURE_RTC_HAS_TDR_TPF (0) 1642 /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ 1643 #define FSL_FEATURE_RTC_HAS_TDR_STF (0) 1644 /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ 1645 #define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) 1646 /* @brief Has Tamper Time Seconds Register (register TTSR). */ 1647 #define FSL_FEATURE_RTC_HAS_TTSR (0) 1648 /* @brief Has Pin Configuration Register (register PCR). */ 1649 #define FSL_FEATURE_RTC_HAS_PCR (0) 1650 1651 /* SDHC module features */ 1652 1653 /* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */ 1654 #define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (0) 1655 /* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */ 1656 #define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (0) 1657 /* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */ 1658 #define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (0) 1659 1660 /* SIM module features */ 1661 1662 /* @brief Has USB FS divider. */ 1663 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) 1664 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ 1665 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) 1666 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ 1667 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) 1668 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ 1669 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) 1670 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ 1671 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) 1672 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ 1673 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) 1674 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ 1675 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) 1676 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ 1677 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) 1678 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ 1679 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) 1680 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ 1681 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) 1682 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ 1683 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) 1684 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ 1685 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) 1686 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ 1687 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) 1688 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ 1689 #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) 1690 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ 1691 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (5) 1692 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ 1693 #define FSL_FEATURE_SIM_OPT_UART_COUNT (0) 1694 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ 1695 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) 1696 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ 1697 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) 1698 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ 1699 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) 1700 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ 1701 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) 1702 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ 1703 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) 1704 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ 1705 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) 1706 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ 1707 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) 1708 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ 1709 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) 1710 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ 1711 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (1) 1712 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ 1713 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (1) 1714 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ 1715 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) 1716 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ 1717 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) 1718 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ 1719 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) 1720 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ 1721 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) 1722 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ 1723 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) 1724 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ 1725 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) 1726 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ 1727 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) 1728 /* @brief Has FTM module(s) configuration. */ 1729 #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) 1730 /* @brief Number of FTM modules. */ 1731 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) 1732 /* @brief Number of FTM triggers with selectable source. */ 1733 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) 1734 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ 1735 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) 1736 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ 1737 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) 1738 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ 1739 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) 1740 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ 1741 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) 1742 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ 1743 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) 1744 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ 1745 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) 1746 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ 1747 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) 1748 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ 1749 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) 1750 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ 1751 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) 1752 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ 1753 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) 1754 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ 1755 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) 1756 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ 1757 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) 1758 /* @brief Has TPM module(s) configuration. */ 1759 #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) 1760 /* @brief The highest TPM module index. */ 1761 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) 1762 /* @brief Has TPM module with index 0. */ 1763 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) 1764 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ 1765 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0) 1766 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ 1767 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) 1768 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1769 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) 1770 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ 1771 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0) 1772 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1773 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) 1774 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ 1775 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) 1776 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ 1777 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) 1778 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ 1779 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) 1780 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ 1781 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) 1782 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ 1783 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) 1784 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ 1785 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) 1786 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ 1787 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1) 1788 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ 1789 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) 1790 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ 1791 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) 1792 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ 1793 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) 1794 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ 1795 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) 1796 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ 1797 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) 1798 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ 1799 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) 1800 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ 1801 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1) 1802 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ 1803 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) 1804 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ 1805 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) 1806 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ 1807 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (1) 1808 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ 1809 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) 1810 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ 1811 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) 1812 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ 1813 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) 1814 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ 1815 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) 1816 /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ 1817 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) 1818 /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ 1819 #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0) 1820 /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ 1821 #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) 1822 /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ 1823 #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) 1824 /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ 1825 #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) 1826 /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ 1827 #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) 1828 /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ 1829 #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) 1830 /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ 1831 #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) 1832 /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ 1833 #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) 1834 /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ 1835 #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) 1836 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ 1837 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) 1838 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ 1839 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) 1840 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ 1841 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) 1842 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ 1843 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) 1844 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ 1845 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) 1846 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ 1847 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) 1848 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ 1849 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) 1850 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ 1851 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) 1852 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ 1853 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (1) 1854 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ 1855 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) 1856 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ 1857 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1) 1858 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ 1859 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) 1860 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ 1861 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) 1862 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ 1863 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) 1864 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ 1865 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) 1866 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ 1867 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) 1868 /* @brief Has device die ID (register bit field SDID[DIEID]). */ 1869 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) 1870 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ 1871 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) 1872 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ 1873 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) 1874 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ 1875 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) 1876 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ 1877 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) 1878 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ 1879 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) 1880 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ 1881 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) 1882 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ 1883 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) 1884 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ 1885 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) 1886 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ 1887 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) 1888 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ 1889 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) 1890 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ 1891 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) 1892 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ 1893 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) 1894 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ 1895 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) 1896 /* @brief Has miscellanious control register (register MCR). */ 1897 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) 1898 /* @brief Has COP watchdog (registers COPC and SRVCOP). */ 1899 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) 1900 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ 1901 #define FSL_FEATURE_SIM_HAS_COP_STOP (0) 1902 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ 1903 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) 1904 1905 /* SMC module features */ 1906 1907 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ 1908 #define FSL_FEATURE_SMC_HAS_PSTOPO (1) 1909 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ 1910 #define FSL_FEATURE_SMC_HAS_LPOPO (1) 1911 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ 1912 #define FSL_FEATURE_SMC_HAS_PORPO (1) 1913 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ 1914 #define FSL_FEATURE_SMC_HAS_LPWUI (0) 1915 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ 1916 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1) 1917 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ 1918 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) 1919 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ 1920 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) 1921 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ 1922 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1) 1923 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ 1924 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1) 1925 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ 1926 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) 1927 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ 1928 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) 1929 /* @brief Has stop submode. */ 1930 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) 1931 /* @brief Has stop submode 0(VLLS0). */ 1932 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) 1933 /* @brief Has stop submode 1(VLLS1). */ 1934 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1) 1935 /* @brief Has stop submode 2(VLLS2). */ 1936 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) 1937 /* @brief Has SMC_PARAM. */ 1938 #define FSL_FEATURE_SMC_HAS_PARAM (0) 1939 /* @brief Has SMC_VERID. */ 1940 #define FSL_FEATURE_SMC_HAS_VERID (0) 1941 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ 1942 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) 1943 /* @brief Has tamper reset (register bit SRS[TAMPER]). */ 1944 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) 1945 /* @brief Has security violation reset (register bit SRS[SECVIO]). */ 1946 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) 1947 /* @brief Width of SMC registers. */ 1948 #define FSL_FEATURE_SMC_REG_WIDTH (8) 1949 1950 /* DSPI module features */ 1951 1952 /* @brief Receive/transmit FIFO size in number of items. */ 1953 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ 1954 (((x) == SPI0) ? (4) : \ 1955 (((x) == SPI1) ? (1) : \ 1956 (((x) == SPI2) ? (1) : (-1)))) 1957 /* @brief Maximum transfer data width in bits. */ 1958 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) 1959 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ 1960 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) 1961 /* @brief Number of chip select pins. */ 1962 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6) 1963 /* @brief Number of CTAR registers. */ 1964 #define FSL_FEATURE_DSPI_CTAR_COUNT (2) 1965 /* @brief Has chip select strobe capability on the PCS5 pin. */ 1966 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) 1967 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 1968 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) 1969 /* @brief Has 16-bit data transfer support. */ 1970 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) 1971 /* @brief Has separate DMA RX and TX requests. */ 1972 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1973 1974 /* SYSMPU module features */ 1975 1976 /* @brief Specifies number of descriptors available. */ 1977 #define FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT (12) 1978 /* @brief Has process identifier support. */ 1979 #define FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER (1) 1980 /* @brief Total number of MPU slave. */ 1981 #define FSL_FEATURE_SYSMPU_SLAVE_COUNT (5) 1982 /* @brief Total number of MPU master. */ 1983 #define FSL_FEATURE_SYSMPU_MASTER_COUNT (6) 1984 1985 /* SysTick module features */ 1986 1987 /* @brief Systick has external reference clock. */ 1988 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) 1989 /* @brief Systick external reference clock is core clock divided by this value. */ 1990 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) 1991 1992 /* TPM module features */ 1993 1994 /* @brief Bus clock is the source clock for the module. */ 1995 #define FSL_FEATURE_TPM_BUS_CLOCK (0) 1996 /* @brief Number of channels. */ 1997 #define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) (2) 1998 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 1999 #define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) 2000 /* @brief Has TPM_PARAM. */ 2001 #define FSL_FEATURE_TPM_HAS_PARAM (0) 2002 /* @brief Has TPM_VERID. */ 2003 #define FSL_FEATURE_TPM_HAS_VERID (0) 2004 /* @brief Has TPM_GLOBAL. */ 2005 #define FSL_FEATURE_TPM_HAS_GLOBAL (0) 2006 /* @brief Has TPM_TRIG. */ 2007 #define FSL_FEATURE_TPM_HAS_TRIG (0) 2008 /* @brief Has counter pause on trigger. */ 2009 #define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) 2010 /* @brief Has external trigger selection. */ 2011 #define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) 2012 /* @brief Has TPM_COMBINE register. */ 2013 #define FSL_FEATURE_TPM_HAS_COMBINE (1) 2014 /* @brief Whether COMBINE register has effect. */ 2015 #define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (1) 2016 /* @brief Has TPM_POL. */ 2017 #define FSL_FEATURE_TPM_HAS_POL (1) 2018 /* @brief Has TPM_FILTER register. */ 2019 #define FSL_FEATURE_TPM_HAS_FILTER (1) 2020 /* @brief Whether FILTER register has effect. */ 2021 #define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (1) 2022 /* @brief Has TPM_QDCTRL register. */ 2023 #define FSL_FEATURE_TPM_HAS_QDCTRL (1) 2024 /* @brief Whether QDCTRL register has effect. */ 2025 #define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (1) 2026 /* @brief Is affected by errata with ID 050050 (Incorrect duty output when EPWM mode is set to PS=0 during write 1 to CnV register). */ 2027 #define FSL_FEATURE_TPM_HAS_ERRATA_050050 (0) 2028 2029 /* TSI module features */ 2030 2031 /* @brief TSI module version. */ 2032 #define FSL_FEATURE_TSI_VERSION (4) 2033 /* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */ 2034 #define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (1) 2035 /* @brief Number of TSI channels. */ 2036 #define FSL_FEATURE_TSI_CHANNEL_COUNT (16) 2037 2038 /* USB module features */ 2039 2040 /* @brief KHCI module instance count */ 2041 #define FSL_FEATURE_USB_KHCI_COUNT (1) 2042 /* @brief HOST mode enabled */ 2043 #define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) 2044 /* @brief OTG mode enabled */ 2045 #define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) 2046 /* @brief Size of the USB dedicated RAM */ 2047 #define FSL_FEATURE_USB_KHCI_USB_RAM (0) 2048 /* @brief Has KEEP_ALIVE_CTRL register */ 2049 #define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) 2050 /* @brief Has the Dynamic SOF threshold compare support */ 2051 #define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (1) 2052 /* @brief Has the VBUS detect support */ 2053 #define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (1) 2054 /* @brief Has the IRC48M module clock support */ 2055 #define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) 2056 /* @brief Number of endpoints supported */ 2057 #define FSL_FEATURE_USB_ENDPT_COUNT (16) 2058 /* @brief Has STALL_IL/OL_DIS registers */ 2059 #define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (0) 2060 /* @brief Has STALL_IH/OH_DIS registers */ 2061 #define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (0) 2062 2063 /* VREF module features */ 2064 2065 /* @brief Has chop oscillator (bit TRM[CHOPEN]) */ 2066 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) 2067 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ 2068 #define FSL_FEATURE_VREF_HAS_COMPENSATION (1) 2069 /* @brief If high/low buffer mode supported */ 2070 #define FSL_FEATURE_VREF_MODE_LV_TYPE (1) 2071 /* @brief Module has also low reference (registers VREFL/VREFH) */ 2072 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) 2073 /* @brief Has VREF_TRM4. */ 2074 #define FSL_FEATURE_VREF_HAS_TRM4 (0) 2075 2076 /* WDOG module features */ 2077 2078 /* @brief Watchdog is available. */ 2079 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) 2080 /* @brief Has Wait mode support. */ 2081 #define FSL_FEATURE_WDOG_HAS_WAITEN (1) 2082 2083 #endif /* _MK80F25615_FEATURES_H_ */ 2084 2085
