1 /* 2 ** ################################################################### 3 ** Processors: MIMXRT685SFAWBR_dsp 4 ** MIMXRT685SFFOB_dsp 5 ** MIMXRT685SFVKB_dsp 6 ** 7 ** Compiler: XCC Compiler 8 ** Reference manual: MIMXRT685 User manual Rev. 0.95 11 November 2019 9 ** Version: rev. 2.0, 2019-11-12 10 ** Build: b201016 11 ** 12 ** Abstract: 13 ** Provides a system configuration function and a global variable that 14 ** contains the system frequency. It configures the device and initializes 15 ** the oscillator (PLL) that is part of the microcontroller device. 16 ** 17 ** Copyright 2016 Freescale Semiconductor, Inc. 18 ** Copyright 2016-2020 NXP 19 ** All rights reserved. 20 ** 21 ** SPDX-License-Identifier: BSD-3-Clause 22 ** 23 ** http: www.nxp.com 24 ** mail: support@nxp.com 25 ** 26 ** Revisions: 27 ** - rev. 1.0 (2018-06-19) 28 ** Initial version. 29 ** - rev. 2.0 (2019-11-12) 30 ** Base on rev 0.95 RM (B0 Header) 31 ** 32 ** ################################################################### 33 */ 34 35 /*! 36 * @file MIMXRT685S 37 * @version 1.0 38 * @date 161020 39 * @brief Device specific configuration file for MIMXRT685S (implementation file) 40 * 41 * Provides a system configuration function and a global variable that contains 42 * the system frequency. It configures the device and initializes the oscillator 43 * (PLL) that is part of the microcontroller device. 44 */ 45 46 #include <stdint.h> 47 #include "fsl_device_registers.h" 48 49 /* Get OSC clock from SYSOSC_BYPASS */ getOscClk(void)50static uint32_t getOscClk(void) 51 { 52 return (CLKCTL0->SYSOSCBYPASS == 0U) ? CLK_XTAL_OSC_CLK : ((CLKCTL0->SYSOSCBYPASS == 1U) ? CLK_EXT_CLKIN : 0U); 53 } 54 55 /* Get FFRO clock from FFROCTL0 setting */ getFFroFreq(void)56static uint32_t getFFroFreq(void) 57 { 58 uint32_t freq = 0U; 59 60 switch (CLKCTL0->FFROCTL0 & CLKCTL0_FFROCTL0_TRIM_RANGE_MASK) 61 { 62 case CLKCTL0_FFROCTL0_TRIM_RANGE(0): 63 freq = CLK_FRO_48MHZ; 64 break; 65 case CLKCTL0_FFROCTL0_TRIM_RANGE(3): 66 freq = CLK_FRO_60MHZ; 67 break; 68 default: 69 freq = 0U; 70 break; 71 } 72 return freq; 73 } 74 getSpllFreq(void)75static uint32_t getSpllFreq(void) 76 { 77 uint32_t freq = 0U; 78 uint64_t freqTmp = 0U; 79 80 switch ((CLKCTL0->SYSPLL0CLKSEL) & CLKCTL0_SYSPLL0CLKSEL_SEL_MASK) 81 { 82 case CLKCTL0_SYSPLL0CLKSEL_SEL(0): /* SFRO clock */ 83 freq = CLK_FRO_16MHZ; 84 break; 85 case CLKCTL0_SYSPLL0CLKSEL_SEL(1): /* OSC clock (clk_in) */ 86 freq = getOscClk(); 87 break; 88 case CLKCTL0_SYSPLL0CLKSEL_SEL(2): /* FRO clock (48m_irc) divider by 2 */ 89 freq = getFFroFreq() / 2U; 90 break; 91 default: 92 freq = 0U; 93 break; 94 } 95 96 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) 97 { 98 /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ 99 freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL0->SYSPLL0NUM))) / ((uint64_t)(CLKCTL0->SYSPLL0DENOM)); 100 freq *= ((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_MULT_MASK) >> CLKCTL0_SYSPLL0CTL0_MULT_SHIFT; 101 freq += (uint32_t)freqTmp; 102 } 103 104 return freq; 105 } 106 107 /* ---------------------------------------------------------------------------- 108 -- Core clock 109 ---------------------------------------------------------------------------- */ 110 111 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; 112 113 /* ---------------------------------------------------------------------------- 114 -- SystemInit() 115 ---------------------------------------------------------------------------- */ 116 SystemInit(void)117__attribute__ ((weak)) void SystemInit (void) { 118 SystemInitHook(); 119 } 120 121 /* ---------------------------------------------------------------------------- 122 -- SystemCoreClockUpdate() 123 ---------------------------------------------------------------------------- */ 124 SystemCoreClockUpdate(void)125void SystemCoreClockUpdate (void) { 126 127 /* iMXRT6xx systemCoreClockUpdate */ 128 uint32_t freq = 0U; 129 130 switch ((CLKCTL1->DSPCPUCLKSELB) & CLKCTL1_DSPCPUCLKSELB_SEL_MASK) 131 { 132 case CLKCTL1_DSPCPUCLKSELB_SEL(0): /* DSPCPUCLKSELA clock */ 133 switch ((CLKCTL1->DSPCPUCLKSELA) & CLKCTL1_DSPCPUCLKSELA_SEL_MASK) 134 { 135 case CLKCTL1_DSPCPUCLKSELA_SEL(0): /* FRO clock (48m_irc) divider by 4 */ 136 freq = getFFroFreq() / 4U; 137 break; 138 case CLKCTL1_DSPCPUCLKSELA_SEL(1): /* OSC clock (clk_in) */ 139 freq = getOscClk(); 140 break; 141 case CLKCTL1_DSPCPUCLKSELA_SEL(2): /* Low Power Oscillator Clock (1m_lposc) */ 142 freq = CLK_LPOSC_1MHZ; 143 break; 144 case CLKCTL1_DSPCPUCLKSELA_SEL(3): /* SFRO clock */ 145 freq = CLK_FRO_16MHZ; 146 break; 147 default: 148 freq = 0U; 149 break; 150 } 151 break; 152 case CLKCTL1_DSPCPUCLKSELB_SEL(1): /* Main System PLL clock */ 153 freq = getSpllFreq(); 154 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) 155 { 156 freq = (uint32_t)((uint64_t)freq * 18U / ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD0_MASK) >> 157 CLKCTL0_SYSPLL0PFD_PFD0_SHIFT)); 158 } 159 freq = freq / ((CLKCTL0->MAINPLLCLKDIV & CLKCTL0_MAINPLLCLKDIV_DIV_MASK) + 1U); 160 break; 161 case CLKCTL1_DSPCPUCLKSELB_SEL(2): /* DSP PLL clock */ 162 freq = getSpllFreq(); 163 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U) 164 { 165 freq = (uint32_t)((uint64_t)freq * 18U / ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD1_MASK) >> 166 CLKCTL0_SYSPLL0PFD_PFD1_SHIFT)); 167 } 168 freq = freq / ((CLKCTL0->DSPPLLCLKDIV & CLKCTL0_DSPPLLCLKDIV_DIV_MASK) + 1U); 169 break; 170 case CLKCTL1_DSPCPUCLKSELB_SEL(3): /* RTC 32KHz clock */ 171 freq = CLK_RTC_32K_CLK; 172 break; 173 default: 174 freq = 0U; 175 break; 176 } 177 178 SystemCoreClock = freq / ((CLKCTL1->DSPCPUCLKDIV & 0xffU) + 1U); 179 } 180 181 /* ---------------------------------------------------------------------------- 182 -- SystemInitHook() 183 ---------------------------------------------------------------------------- */ 184 SystemInitHook(void)185__attribute__ ((weak)) void SystemInitHook (void) { 186 /* Void implementation of the weak function. */ 187 } 188
