1 /* 2 ** ################################################################### 3 ** Version: rev. 1.1, 2019-05-16 4 ** Build: b210318 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2021 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2018-08-22) 20 ** Initial version based on v0.2UM 21 ** - rev. 1.1 (2019-05-16) 22 ** Initial A1 version based on v1.3UM 23 ** 24 ** ################################################################### 25 */ 26 27 #ifndef _LPC55S69_cm33_core0_FEATURES_H_ 28 #define _LPC55S69_cm33_core0_FEATURES_H_ 29 30 /* SOC module features */ 31 32 /* @brief CASPER availability on the SoC. */ 33 #define FSL_FEATURE_SOC_CASPER_COUNT (1) 34 /* @brief CRC availability on the SoC. */ 35 #define FSL_FEATURE_SOC_CRC_COUNT (1) 36 /* @brief CTIMER availability on the SoC. */ 37 #define FSL_FEATURE_SOC_CTIMER_COUNT (5) 38 /* @brief DMA availability on the SoC. */ 39 #define FSL_FEATURE_SOC_DMA_COUNT (2) 40 /* @brief FLASH availability on the SoC. */ 41 #define FSL_FEATURE_SOC_FLASH_COUNT (1) 42 /* @brief FLEXCOMM availability on the SoC. */ 43 #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9) 44 /* @brief GINT availability on the SoC. */ 45 #define FSL_FEATURE_SOC_GINT_COUNT (2) 46 /* @brief GPIO availability on the SoC. */ 47 #define FSL_FEATURE_SOC_GPIO_COUNT (1) 48 /* @brief SECGPIO availability on the SoC. */ 49 #define FSL_FEATURE_SOC_SECGPIO_COUNT (1) 50 /* @brief HASHCRYPT availability on the SoC. */ 51 #define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1) 52 /* @brief I2C availability on the SoC. */ 53 #define FSL_FEATURE_SOC_I2C_COUNT (8) 54 /* @brief I2S availability on the SoC. */ 55 #define FSL_FEATURE_SOC_I2S_COUNT (8) 56 /* @brief INPUTMUX availability on the SoC. */ 57 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) 58 /* @brief IOCON availability on the SoC. */ 59 #define FSL_FEATURE_SOC_IOCON_COUNT (1) 60 /* @brief LPADC availability on the SoC. */ 61 #define FSL_FEATURE_SOC_LPADC_COUNT (1) 62 /* @brief MAILBOX availability on the SoC. */ 63 #define FSL_FEATURE_SOC_MAILBOX_COUNT (1) 64 /* @brief MRT availability on the SoC. */ 65 #define FSL_FEATURE_SOC_MRT_COUNT (1) 66 /* @brief OSTIMER availability on the SoC. */ 67 #define FSL_FEATURE_SOC_OSTIMER_COUNT (1) 68 /* @brief PINT availability on the SoC. */ 69 #define FSL_FEATURE_SOC_PINT_COUNT (1) 70 /* @brief SECPINT availability on the SoC. */ 71 #define FSL_FEATURE_SOC_SECPINT_COUNT (1) 72 /* @brief PMC availability on the SoC. */ 73 #define FSL_FEATURE_SOC_PMC_COUNT (1) 74 /* @brief POWERQUAD availability on the SoC. */ 75 #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) 76 /* @brief PUF availability on the SoC. */ 77 #define FSL_FEATURE_SOC_PUF_COUNT (1) 78 /* @brief LPC_RNG1 availability on the SoC. */ 79 #define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) 80 /* @brief RTC availability on the SoC. */ 81 #define FSL_FEATURE_SOC_RTC_COUNT (1) 82 /* @brief SCT availability on the SoC. */ 83 #define FSL_FEATURE_SOC_SCT_COUNT (1) 84 /* @brief SDIF availability on the SoC. */ 85 #define FSL_FEATURE_SOC_SDIF_COUNT (1) 86 /* @brief SPI availability on the SoC. */ 87 #define FSL_FEATURE_SOC_SPI_COUNT (9) 88 /* @brief SYSCON availability on the SoC. */ 89 #define FSL_FEATURE_SOC_SYSCON_COUNT (1) 90 /* @brief SYSCTL1 availability on the SoC. */ 91 #define FSL_FEATURE_SOC_SYSCTL1_COUNT (1) 92 /* @brief USART availability on the SoC. */ 93 #define FSL_FEATURE_SOC_USART_COUNT (8) 94 /* @brief USB availability on the SoC. */ 95 #define FSL_FEATURE_SOC_USB_COUNT (1) 96 /* @brief USBFSH availability on the SoC. */ 97 #define FSL_FEATURE_SOC_USBFSH_COUNT (1) 98 /* @brief USBHSD availability on the SoC. */ 99 #define FSL_FEATURE_SOC_USBHSD_COUNT (1) 100 /* @brief USBHSH availability on the SoC. */ 101 #define FSL_FEATURE_SOC_USBHSH_COUNT (1) 102 /* @brief USBPHY availability on the SoC. */ 103 #define FSL_FEATURE_SOC_USBPHY_COUNT (1) 104 /* @brief UTICK availability on the SoC. */ 105 #define FSL_FEATURE_SOC_UTICK_COUNT (1) 106 /* @brief WWDT availability on the SoC. */ 107 #define FSL_FEATURE_SOC_WWDT_COUNT (1) 108 109 /* LPADC module features */ 110 111 /* @brief FIFO availability on the SoC. */ 112 #define FSL_FEATURE_LPADC_FIFO_COUNT (2) 113 /* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ 114 #define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) 115 /* @brief Has differential mode (bitfield CMDLn[DIFF]). */ 116 #define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) 117 /* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ 118 #define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) 119 /* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ 120 #define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) 121 /* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ 122 #define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) 123 /* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ 124 #define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) 125 /* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ 126 #define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) 127 /* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ 128 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) 129 /* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ 130 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) 131 /* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ 132 #define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) 133 /* @brief Has internal clock (bitfield CFG[ADCKEN]). */ 134 #define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) 135 /* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ 136 #define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) 137 /* @brief Has calibration (bitfield CFG[CALOFS]). */ 138 #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) 139 /* @brief Has offset trim (register OFSTRIM). */ 140 #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) 141 /* @brief Has internal temperature sensor. */ 142 #define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) 143 /* @brief Temperature sensor parameter A (slope). */ 144 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (744.6f) 145 /* @brief Temperature sensor parameter B (offset). */ 146 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (313.7f) 147 /* @brief Temperature sensor parameter Alpha. */ 148 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (11.5f) 149 /* @brief the buffer size of temperature sensor. */ 150 #define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (4U) 151 152 /* CASPER module features */ 153 154 /* @brief Base address of the CASPER dedicated RAM */ 155 #define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000) 156 /* @brief SW interleaving of the CASPER dedicated RAM */ 157 #define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1) 158 /* @brief CASPER dedicated RAM offset */ 159 #define FSL_FEATURE_CASPER_RAM_OFFSET (0xE) 160 161 /* CTIMER module features */ 162 163 /* No feature definitions */ 164 165 /* DMA module features */ 166 167 /* @brief Number of channels */ 168 #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23) 169 /* @brief Align size of DMA descriptor */ 170 #define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) 171 /* @brief DMA head link descriptor table align size */ 172 #define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) 173 174 /* FLEXCOMM module features */ 175 176 /* @brief FLEXCOMM0 USART INDEX 0 */ 177 #define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) 178 /* @brief FLEXCOMM0 SPI INDEX 0 */ 179 #define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) 180 /* @brief FLEXCOMM0 I2C INDEX 0 */ 181 #define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) 182 /* @brief FLEXCOMM0 I2S INDEX 0 */ 183 #define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) 184 /* @brief FLEXCOMM1 USART INDEX 1 */ 185 #define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) 186 /* @brief FLEXCOMM1 SPI INDEX 1 */ 187 #define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) 188 /* @brief FLEXCOMM1 I2C INDEX 1 */ 189 #define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) 190 /* @brief FLEXCOMM1 I2S INDEX 1 */ 191 #define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) 192 /* @brief FLEXCOMM2 USART INDEX 2 */ 193 #define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) 194 /* @brief FLEXCOMM2 SPI INDEX 2 */ 195 #define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) 196 /* @brief FLEXCOMM2 I2C INDEX 2 */ 197 #define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) 198 /* @brief FLEXCOMM2 I2S INDEX 2 */ 199 #define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) 200 /* @brief FLEXCOMM3 USART INDEX 3 */ 201 #define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) 202 /* @brief FLEXCOMM3 SPI INDEX 3 */ 203 #define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) 204 /* @brief FLEXCOMM3 I2C INDEX 3 */ 205 #define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) 206 /* @brief FLEXCOMM3 I2S INDEX 3 */ 207 #define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) 208 /* @brief FLEXCOMM4 USART INDEX 4 */ 209 #define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) 210 /* @brief FLEXCOMM4 SPI INDEX 4 */ 211 #define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) 212 /* @brief FLEXCOMM4 I2C INDEX 4 */ 213 #define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) 214 /* @brief FLEXCOMM4 I2S INDEX 4 */ 215 #define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) 216 /* @brief FLEXCOMM5 USART INDEX 5 */ 217 #define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) 218 /* @brief FLEXCOMM5 SPI INDEX 5 */ 219 #define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) 220 /* @brief FLEXCOMM5 I2C INDEX 5 */ 221 #define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) 222 /* @brief FLEXCOMM5 I2S INDEX 5 */ 223 #define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) 224 /* @brief FLEXCOMM6 USART INDEX 6 */ 225 #define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) 226 /* @brief FLEXCOMM6 SPI INDEX 6 */ 227 #define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) 228 /* @brief FLEXCOMM6 I2C INDEX 6 */ 229 #define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) 230 /* @brief FLEXCOMM6 I2S INDEX 6 */ 231 #define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) 232 /* @brief FLEXCOMM7 USART INDEX 7 */ 233 #define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) 234 /* @brief FLEXCOMM7 SPI INDEX 7 */ 235 #define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) 236 /* @brief FLEXCOMM7 I2C INDEX 7 */ 237 #define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) 238 /* @brief FLEXCOMM7 I2S INDEX 7 */ 239 #define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) 240 /* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ 241 #define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) 242 /* @brief I2S has DMIC interconnection */ 243 #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) 244 245 /* HASHCRYPT module features */ 246 247 /* @brief the address of alias offset */ 248 #define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000) 249 250 /* I2S module features */ 251 252 /* @brief I2S support dual channel transfer. */ 253 #define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0) 254 /* @brief I2S has DMIC interconnection */ 255 #define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) 256 257 /* IOCON module features */ 258 259 /* @brief Func bit field width */ 260 #define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) 261 262 /* MAILBOX module features */ 263 264 /* @brief Mailbox side for current core */ 265 #define FSL_FEATURE_MAILBOX_SIDE_A (1) 266 267 /* MRT module features */ 268 269 /* @brief number of channels. */ 270 #define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) 271 272 /* PINT module features */ 273 274 /* @brief Number of connected outputs */ 275 #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) 276 277 /* PLU module features */ 278 279 /* @brief Has WAKEINT_CTRL register. */ 280 #define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1) 281 282 /* PMC module features */ 283 284 /* @brief UTICK does not support PD configure. */ 285 #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) 286 /* @brief WDT OSC does not support PD configure. */ 287 #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) 288 289 /* POWERLIB module features */ 290 291 /* @brief Powerlib API is different with other LPC series devices. */ 292 #define FSL_FEATURE_POWERLIB_EXTEND (1) 293 294 /* POWERQUAD module features */ 295 296 /* @brief Sine and Cossine fix errata */ 297 #define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1) 298 299 /* PUF module features */ 300 301 /* @brief Number of PUF key slots available on device. */ 302 #define FSL_FEATURE_PUF_HAS_KEYSLOTS (4) 303 /* @brief the shift status value */ 304 #define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1) 305 306 /* RTC module features */ 307 308 /* No feature definitions */ 309 310 /* SCT module features */ 311 312 /* @brief Number of events */ 313 #define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16) 314 /* @brief Number of states */ 315 #define FSL_FEATURE_SCT_NUMBER_OF_STATES (32) 316 /* @brief Number of match capture */ 317 #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16) 318 /* @brief Number of outputs */ 319 #define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) 320 321 /* SDIF module features */ 322 323 /* @brief FIFO depth, every location is a WORD */ 324 #define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) 325 /* @brief Max DMA buffer size */ 326 #define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) 327 /* @brief Max source clock in HZ */ 328 #define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) 329 /* @brief support 2 cards */ 330 #define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1) 331 332 /* SECPINT module features */ 333 334 /* @brief Number of connected outputs */ 335 #define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2) 336 337 /* SYSCON module features */ 338 339 /* @brief Flash page size in bytes */ 340 #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) 341 /* @brief Flash sector size in bytes */ 342 #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) 343 /* @brief Flash size in bytes */ 344 #define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (622592) 345 /* @brief Has Power Down mode */ 346 #define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1) 347 /* @brief CCM_ANALOG availability on the SoC. */ 348 #define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) 349 /* @brief Starter register discontinuous. */ 350 #define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) 351 352 /* SYSCTL1 module features */ 353 354 /* No feature definitions */ 355 356 /* USB module features */ 357 358 /* @brief Size of the USB dedicated RAM */ 359 #define FSL_FEATURE_USB_USB_RAM (0x00004000) 360 /* @brief Base address of the USB dedicated RAM */ 361 #define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000) 362 /* @brief USB version */ 363 #define FSL_FEATURE_USB_VERSION (200) 364 /* @brief Number of the endpoint in USB FS */ 365 #define FSL_FEATURE_USB_EP_NUM (5) 366 367 /* USBFSH module features */ 368 369 /* @brief Size of the USB dedicated RAM */ 370 #define FSL_FEATURE_USBFSH_USB_RAM (0x00004000) 371 /* @brief Base address of the USB dedicated RAM */ 372 #define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000) 373 /* @brief USBFSH version */ 374 #define FSL_FEATURE_USBFSH_VERSION (200) 375 376 /* USBHSD module features */ 377 378 /* @brief Size of the USB dedicated RAM */ 379 #define FSL_FEATURE_USBHSD_USB_RAM (0x00004000) 380 /* @brief Base address of the USB dedicated RAM */ 381 #define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000) 382 /* @brief USBHSD version */ 383 #define FSL_FEATURE_USBHSD_VERSION (300) 384 /* @brief Number of the endpoint in USB HS */ 385 #define FSL_FEATURE_USBHSD_EP_NUM (6) 386 387 /* USBHSH module features */ 388 389 /* @brief Size of the USB dedicated RAM */ 390 #define FSL_FEATURE_USBHSH_USB_RAM (0x00004000) 391 /* @brief Base address of the USB dedicated RAM */ 392 #define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) 393 /* @brief USBHSH version */ 394 #define FSL_FEATURE_USBHSH_VERSION (300) 395 396 /* USBPHY module features */ 397 398 /* @brief Size of the USB dedicated RAM */ 399 #define FSL_FEATURE_USBPHY_USB_RAM (0x00004000) 400 /* @brief Base address of the USB dedicated RAM */ 401 #define FSL_FEATURE_USBPHY_USB_RAM_BASE_ADDRESS (0x40100000) 402 /* @brief USBHSD version */ 403 #define FSL_FEATURE_USBPHY_VERSION (300) 404 /* @brief Number of the endpoint in USB HS */ 405 #define FSL_FEATURE_USBPHY_EP_NUM (6) 406 407 /* WWDT module features */ 408 409 /* @brief Has no RESET register. */ 410 #define FSL_FEATURE_WWDT_HAS_NO_RESET (1) 411 /* @brief WWDT does not support oscillator lock. */ 412 #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) 413 414 #endif /* _LPC55S69_cm33_core0_FEATURES_H_ */ 415 416
