1 /* 2 * Copyright (c) 2015, Freescale Semiconductor, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without modification, 6 * are permitted provided that the following conditions are met: 7 * 8 * o Redistributions of source code must retain the above copyright notice, this list 9 * of conditions and the following disclaimer. 10 * 11 * o Redistributions in binary form must reproduce the above copyright notice, this 12 * list of conditions and the following disclaimer in the documentation and/or 13 * other materials provided with the distribution. 14 * 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its 16 * contributors may be used to endorse or promote products derived from this 17 * software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __RDC_DEFS_IMX6SX__ 32 #define __RDC_DEFS_IMX6SX__ 33 34 /*! 35 * @addtogroup rdc_def_imx6sx 36 * @{ 37 */ 38 39 /******************************************************************************* 40 * Definitions 41 ******************************************************************************/ 42 43 /*! @brief RDC master assignment. */ 44 enum _rdc_mda 45 { 46 rdcMdaA9L2Cache = 0U, /*!< A9 L2 Cache RDC Master. */ 47 rdcMdaM4 = 1U, /*!< M4 RDC Master. */ 48 rdcMdaGpu = 2U, /*!< GPU RDC Master. */ 49 rdcMdaCsi1 = 3U, /*!< Csi1 RDC Master. */ 50 rdcMdaCsi2 = 4U, /*!< Csi2 RDC Master. */ 51 rdcMdaLcdif1 = 5U, /*!< Lcdif1 RDC Master. */ 52 rdcMdaLcdif2 = 6U, /*!< Lcdif2 RDC Master. */ 53 rdcMdaPxp = 7U, /*!< Pxp RDC Master. */ 54 rdcMdaPcieCtrl = 8U, /*!< Pcie Ctrl RDC Master. */ 55 rdcMdaDap = 9U, /*!< Dap RDC Master. */ 56 rdcMdaCaam = 10U, /*!< Caam RDC Master. */ 57 rdcMdaSdmaPeriph = 11U, /*!< Sdma Periph RDC Master. */ 58 rdcMdaSdmaBurst = 12U, /*!< Sdma Burst RDC Master. */ 59 rdcMdaApbhdma = 13U, /*!< Apbhdma RDC Master. */ 60 rdcMdaRawnand = 14U, /*!< Rawnand RDC Master. */ 61 rdcMdaUsdhc1 = 15U, /*!< Usdhc1 RDC Master. */ 62 rdcMdaUsdhc2 = 16U, /*!< Usdhc2 RDC Master. */ 63 rdcMdaUsdhc3 = 17U, /*!< Usdhc3 RDC Master. */ 64 rdcMdaUsdhc4 = 18U, /*!< Usdhc4 RDC Master. */ 65 rdcMdaUsb = 19U, /*!< USB RDC Master. */ 66 rdcMdaMlb = 20U, /*!< MLB RDC Master. */ 67 rdcMdaTestPort = 21U, /*!< Test Port RDC Master. */ 68 rdcMdaEnet1Tx = 22U, /*!< Enet1 Tx RDC Master. */ 69 rdcMdaEnet1Rx = 23U, /*!< Enet1 Rx Master. */ 70 rdcMdaEnet2Tx = 24U, /*!< Enet2 Tx RDC Master. */ 71 rdcMdaEnet2Rx = 25U, /*!< Enet2 Rx RDC Master. */ 72 rdcMdaSdmaPort = 26U, /*!< Sdma Port RDC Master. */ 73 }; 74 75 /*! @brief RDC peripheral assignment. */ 76 enum _rdc_pdap 77 { 78 rdcPdapPwm1 = 0U, /*!< Pwm1 RDC Peripheral. */ 79 rdcPdapPwm2 = 1U, /*!< Pwm2 RDC Peripheral. */ 80 rdcPdapPwm3 = 2U, /*!< Pwm3 RDC Peripheral. */ 81 rdcPdapPwm4 = 3U, /*!< Pwm4 RDC Peripheral. */ 82 rdcPdapCan1 = 4U, /*!< Can1 RDC Peripheral. */ 83 rdcPdapCan2 = 5U, /*!< Can2 RDC Peripheral. */ 84 rdcPdapGpt = 6U, /*!< Gpt RDC Peripheral. */ 85 rdcPdapGpio1 = 7U, /*!< Gpio1 RDC Peripheral. */ 86 rdcPdapGpio2 = 8U, /*!< Gpio2 RDC Peripheral. */ 87 rdcPdapGpio3 = 9U, /*!< Gpio3 RDC Peripheral. */ 88 rdcPdapGpio4 = 10U, /*!< Gpio4 RDC Peripheral. */ 89 rdcPdapGpio5 = 11U, /*!< Gpio5 RDC Peripheral. */ 90 rdcPdapGpio6 = 12U, /*!< Gpio6 RDC Peripheral. */ 91 rdcPdapGpio7 = 13U, /*!< Gpio7 RDC Peripheral. */ 92 rdcPdapKpp = 14U, /*!< Kpp RDC Peripheral. */ 93 rdcPdapWdog1 = 15U, /*!< Wdog1 RDC Peripheral. */ 94 rdcPdapWdog2 = 16U, /*!< Wdog2 RDC Peripheral. */ 95 rdcPdapCcm = 17U, /*!< Ccm RDC Peripheral. */ 96 rdcPdapAnatopDig = 18U, /*!< AnatopDig RDC Peripheral. */ 97 rdcPdapSnvsHp = 19U, /*!< SnvsHp RDC Peripheral. */ 98 rdcPdapEpit1 = 20U, /*!< Epit1 RDC Peripheral. */ 99 rdcPdapEpit2 = 21U, /*!< Epit2 RDC Peripheral. */ 100 rdcPdapSrc = 22U, /*!< Src RDC Peripheral. */ 101 rdcPdapGpc = 23U, /*!< Gpc RDC Peripheral. */ 102 rdcPdapIomuxc = 24U, /*!< Iomuxc RDC Peripheral. */ 103 rdcPdapIomuxcGpr = 25U, /*!< IomuxcGpr RDC Peripheral. */ 104 rdcPdapCanfdCan1 = 26U, /*!< Canfd Can1 RDC Peripheral. */ 105 rdcPdapSdma = 27U, /*!< Sdma RDC Peripheral. */ 106 rdcPdapCanfdCan2 = 28U, /*!< Canfd Can2 RDC Peripheral. */ 107 rdcPdapRdcSema421 = 29U, /*!< Rdc Sema421 RDC Peripheral. */ 108 rdcPdapRdcSema422 = 30U, /*!< Rdc Sema422 RDC Peripheral. */ 109 rdcPdapRdc = 31U, /*!< Rdc RDC Peripheral. */ 110 rdcPdapAipsTz1GlobalEnable1 = 32U, /*!< AipsTz1GlobalEnable1 RDC Peripheral. */ 111 rdcPdapAipsTz1GlobalEnable2 = 33U, /*!< AipsTz1GlobalEnable2 RDC Peripheral. */ 112 rdcPdapUsb02hPl301 = 34U, /*!< Usb02hPl301 RDC Peripheral. */ 113 rdcPdapUsb02hUsb = 35U, /*!< Usb02hUsb RDC Peripheral. */ 114 rdcPdapEnet1 = 36U, /*!< Enet1 RDC Peripheral. */ 115 rdcPdapMlb2550 = 37U, /*!< Mlb2550 RDC Peripheral. */ 116 rdcPdapUsdhc1 = 38U, /*!< Usdhc1 RDC Peripheral. */ 117 rdcPdapUsdhc2 = 39U, /*!< Usdhc2 RDC Peripheral. */ 118 rdcPdapUsdhc3 = 40U, /*!< Usdhc3 RDC Peripheral. */ 119 rdcPdapUsdhc4 = 41U, /*!< Usdhc4 RDC Peripheral. */ 120 rdcPdapI2c1 = 42U, /*!< I2c1 RDC Peripheral. */ 121 rdcPdapI2c2 = 43U, /*!< I2c2 RDC Peripheral. */ 122 rdcPdapI2c3 = 44U, /*!< I2c3 RDC Peripheral. */ 123 rdcPdapRomcp = 45U, /*!< Romcp RDC Peripheral. */ 124 rdcPdapMmdc = 46U, /*!< Mmdc RDC Peripheral. */ 125 rdcPdapEnet2 = 47U, /*!< Enet2 RDC Peripheral. */ 126 rdcPdapEim = 48U, /*!< Eim RDC Peripheral. */ 127 rdcPdapOcotpCtrlWrapper = 49U, /*!< OcotpCtrlWrapper RDC Peripheral. */ 128 rdcPdapCsu = 50U, /*!< Csu RDC Peripheral. */ 129 rdcPdapPerfmon1 = 51U, /*!< Perfmon1 RDC Peripheral. */ 130 rdcPdapPerfmon2 = 52U, /*!< Perfmon2 RDC Peripheral. */ 131 rdcPdapAxiMon = 53U, /*!< AxiMon RDC Peripheral. */ 132 rdcPdapTzasc1 = 54U, /*!< Tzasc1 RDC Peripheral. */ 133 rdcPdapSai1 = 55U, /*!< Sai1 RDC Peripheral. */ 134 rdcPdapAudmux = 56U, /*!< Audmux RDC Peripheral. */ 135 rdcPdapSai2 = 57U, /*!< Sai2 RDC Peripheral. */ 136 rdcPdapQspi1 = 58U, /*!< Qspi1 RDC Peripheral. */ 137 rdcPdapQspi2 = 59U, /*!< Qspi2 RDC Peripheral. */ 138 rdcPdapUart2 = 60U, /*!< Uart2 RDC Peripheral. */ 139 rdcPdapUart3 = 61U, /*!< Uart3 RDC Peripheral. */ 140 rdcPdapUart4 = 62U, /*!< Uart4 RDC Peripheral. */ 141 rdcPdapUart5 = 63U, /*!< Uart5 RDC Peripheral. */ 142 rdcPdapI2c4 = 64U, /*!< I2c4 RDC Peripheral. */ 143 rdcPdapQosc = 65U, /*!< Qosc RDC Peripheral. */ 144 rdcPdapCaam = 66U, /*!< Caam RDC Peripheral. */ 145 rdcPdapDap = 67U, /*!< Dap RDC Peripheral. */ 146 rdcPdapAdc1 = 68U, /*!< Adc1 RDC Peripheral. */ 147 rdcPdapAdc2 = 69U, /*!< Adc2 RDC Peripheral. */ 148 rdcPdapWdog3 = 70U, /*!< Wdog3 RDC Peripheral. */ 149 rdcPdapEcspi5 = 71U, /*!< Ecspi5 RDC Peripheral. */ 150 rdcPdapSema4 = 72U, /*!< Sema4 RDC Peripheral. */ 151 rdcPdapMuA = 73U, /*!< MuA RDC Peripheral. */ 152 rdcPdapCanfdCpu = 74U, /*!< Canfd Cpu RDC Peripheral. */ 153 rdcPdapMuB = 75U, /*!< MuB RDC Peripheral. */ 154 rdcPdapUart6 = 76U, /*!< Uart6 RDC Peripheral. */ 155 rdcPdapPwm5 = 77U, /*!< Pwm5 RDC Peripheral. */ 156 rdcPdapPwm6 = 78U, /*!< Pwm6 RDC Peripheral. */ 157 rdcPdapPwm7 = 79U, /*!< Pwm7 RDC Peripheral. */ 158 rdcPdapPwm8 = 80U, /*!< Pwm8 RDC Peripheral. */ 159 rdcPdapAipsTz3GlobalEnable0 = 81U, /*!< AipsTz3GlobalEnable0 RDC Peripheral. */ 160 rdcPdapAipsTz3GlobalEnable1 = 82U, /*!< AipsTz3GlobalEnable1 RDC Peripheral. */ 161 rdcPdapSpdif = 84U, /*!< Spdif RDC Peripheral. */ 162 rdcPdapEcspi1 = 85U, /*!< Ecspi1 RDC Peripheral. */ 163 rdcPdapEcspi2 = 86U, /*!< Ecspi2 RDC Peripheral. */ 164 rdcPdapEcspi3 = 87U, /*!< Ecspi3 RDC Peripheral. */ 165 rdcPdapEcspi4 = 88U, /*!< Ecspi4 RDC Peripheral. */ 166 rdcPdapUart1 = 91U, /*!< Uart1 RDC Peripheral. */ 167 rdcPdapEsai = 92U, /*!< Esai RDC Peripheral. */ 168 rdcPdapSsi1 = 93U, /*!< Ssi1 RDC Peripheral. */ 169 rdcPdapSsi2 = 94U, /*!< Ssi2 RDC Peripheral. */ 170 rdcPdapSsi3 = 95U, /*!< Ssi3 RDC Peripheral. */ 171 rdcPdapAsrc = 96U, /*!< Asrc RDC Peripheral. */ 172 rdcPdapSpbaMaMegamix = 98U, /*!< SpbaMaMegamix RDC Peripheral. */ 173 rdcPdapGis = 99U, /*!< Gis RDC Peripheral. */ 174 rdcPdapDcic1 = 100U, /*!< Dcic1 RDC Peripheral. */ 175 rdcPdapDcic2 = 101U, /*!< Dcic2 RDC Peripheral. */ 176 rdcPdapCsi1 = 102U, /*!< Csi1 RDC Peripheral. */ 177 rdcPdapPxp = 103U, /*!< Pxp RDC Peripheral. */ 178 rdcPdapCsi2 = 104U, /*!< Csi2 RDC Peripheral. */ 179 rdcPdapLcdif1 = 105U, /*!< Lcdif1 RDC Peripheral. */ 180 rdcPdapLcdif2 = 106U, /*!< Lcdif2 RDC Peripheral. */ 181 rdcPdapVadc = 107U, /*!< Vadc RDC Peripheral. */ 182 rdcPdapVdec = 108U, /*!< Vdec RDC Peripheral. */ 183 rdcPdapSpDisplaymix = 109U, /*!< SpDisplaymix RDC Peripheral. */ 184 }; 185 186 /*! @brief RDC memory region */ 187 enum _rdc_mr 188 { 189 rdcMrMmdc = 0U, /*!< alignment 4096 */ 190 rdcMrMmdcLast = 7U, /*!< alignment 4096 */ 191 rdcMrQspi1 = 8U, /*!< alignment 4096 */ 192 rdcMrQspi1Last = 15U, /*!< alignment 4096 */ 193 rdcMrQspi2 = 16U, /*!< alignment 4096 */ 194 rdcMrQspi2Last = 23U, /*!< alignment 4096 */ 195 rdcMrWeim = 24U, /*!< alignment 4096 */ 196 rdcMrWeimLast = 31U, /*!< alignment 4096 */ 197 rdcMrPcie = 32U, /*!< alignment 4096 */ 198 rdcMrPcieLast = 39U, /*!< alignment 4096 */ 199 rdcMrOcram = 40U, /*!< alignment 128 */ 200 rdcMrOcramLast = 44U, /*!< alignment 128 */ 201 rdcMrOcramS = 45U, /*!< alignment 128 */ 202 rdcMrOcramSLast = 49U, /*!< alignment 128 */ 203 rdcMrOcramL2 = 50U, /*!< alignment 128 */ 204 rdcMrOcramL2Last = 54U, /*!< alignment 128 */ 205 }; 206 207 #endif /* __RDC_DEFS_IMX6SX__ */ 208 /******************************************************************************* 209 * EOF 210 ******************************************************************************/ 211
