1/*
2 * NOTE: Autogenerated file by kinetis_signal2dts.py
3 *       for MKW41Z512VHT4/signal_configuration.xml
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8/*
9 * Pin nodes are of the form:
10 *
11 *	<SIGNAL[0..n]>: <signal[0]> {
12 *		nxp,kinetis-port-pins = < PIN PCR[MUX] >;
13 *	};
14 */
15
16&porta {
17	TSI0_CH8_PTA0: tsi0_ch8_pta0 {
18		nxp,kinetis-port-pins = < 0 0 >;
19	};
20	PTA0: GPIOA_PTA0: gpioa_pta0 {
21		nxp,kinetis-port-pins = < 0 1 >;
22	};
23	SPI0_PCS1_PTA0: spi0_pcs1_pta0 {
24		nxp,kinetis-port-pins = < 0 2 >;
25	};
26	TPM1_CH0_PTA0: tpm1_ch0_pta0 {
27		nxp,kinetis-port-pins = < 0 5 >;
28	};
29	SWD_DIO_PTA0: swd_dio_pta0 {
30		nxp,kinetis-port-pins = < 0 7 >;
31	};
32	TSI0_CH9_PTA1: tsi0_ch9_pta1 {
33		nxp,kinetis-port-pins = < 1 0 >;
34	};
35	PTA1: GPIOA_PTA1: gpioa_pta1 {
36		nxp,kinetis-port-pins = < 1 1 >;
37	};
38	SPI1_PCS0_PTA1: spi1_pcs0_pta1 {
39		nxp,kinetis-port-pins = < 1 2 >;
40	};
41	TPM1_CH1_PTA1: tpm1_ch1_pta1 {
42		nxp,kinetis-port-pins = < 1 5 >;
43	};
44	SWD_CLK_PTA1: swd_clk_pta1 {
45		nxp,kinetis-port-pins = < 1 7 >;
46	};
47	PTA2: GPIOA_PTA2: gpioa_pta2 {
48		nxp,kinetis-port-pins = < 2 1 >;
49	};
50	TPM0_CH3_PTA2: tpm0_ch3_pta2 {
51		nxp,kinetis-port-pins = < 2 5 >;
52	};
53	RESET_b_PTA2: reset_b_pta2 {
54		nxp,kinetis-port-pins = < 2 7 >;
55	};
56	TSI0_CH10_PTA16: tsi0_ch10_pta16 {
57		nxp,kinetis-port-pins = < 16 0 >;
58	};
59	PTA16: GPIOA_PTA16: LLWU_P4_PTA16: gpioa_pta16 {
60		nxp,kinetis-port-pins = < 16 1 >;
61	};
62	SPI1_SOUT_PTA16: spi1_sout_pta16 {
63		nxp,kinetis-port-pins = < 16 2 >;
64	};
65	TPM0_CH0_PTA16: tpm0_ch0_pta16 {
66		nxp,kinetis-port-pins = < 16 5 >;
67	};
68	TSI0_CH11_PTA17: tsi0_ch11_pta17 {
69		nxp,kinetis-port-pins = < 17 0 >;
70	};
71	PTA17: GPIOA_PTA17: LLWU_P5_PTA17: RF_RESET_PTA17: gpioa_pta17 {
72		nxp,kinetis-port-pins = < 17 1 >;
73	};
74	SPI1_SIN_PTA17: spi1_sin_pta17 {
75		nxp,kinetis-port-pins = < 17 2 >;
76	};
77	TPM_CLKIN1_PTA17: tpm_clkin1_pta17 {
78		nxp,kinetis-port-pins = < 17 5 >;
79	};
80	TSI0_CH12_PTA18: tsi0_ch12_pta18 {
81		nxp,kinetis-port-pins = < 18 0 >;
82	};
83	PTA18: GPIOA_PTA18: LLWU_P6_PTA18: gpioa_pta18 {
84		nxp,kinetis-port-pins = < 18 1 >;
85	};
86	SPI1_SCK_PTA18: spi1_sck_pta18 {
87		nxp,kinetis-port-pins = < 18 2 >;
88	};
89	TPM2_CH0_PTA18: tpm2_ch0_pta18 {
90		nxp,kinetis-port-pins = < 18 5 >;
91	};
92	TSI0_CH13_PTA19: ADC0_SE5_PTA19: tsi0_ch13_pta19 {
93		nxp,kinetis-port-pins = < 19 0 >;
94	};
95	PTA19: GPIOA_PTA19: LLWU_P7_PTA19: gpioa_pta19 {
96		nxp,kinetis-port-pins = < 19 1 >;
97	};
98	SPI1_PCS0_PTA19: spi1_pcs0_pta19 {
99		nxp,kinetis-port-pins = < 19 2 >;
100	};
101	TPM2_CH1_PTA19: tpm2_ch1_pta19 {
102		nxp,kinetis-port-pins = < 19 5 >;
103	};
104};
105
106&portb {
107	PTB0: GPIOB_PTB0: LLWU_P8_PTB0: XTAL_OUT_EN_PTB0: gpiob_ptb0 {
108		nxp,kinetis-port-pins = < 0 1 >;
109	};
110	I2C0_SCL_PTB0: i2c0_scl_ptb0 {
111		nxp,kinetis-port-pins = < 0 3 >;
112	};
113	CMP0_OUT_PTB0: cmp0_out_ptb0 {
114		nxp,kinetis-port-pins = < 0 4 >;
115	};
116	TPM0_CH1_PTB0: tpm0_ch1_ptb0 {
117		nxp,kinetis-port-pins = < 0 5 >;
118	};
119	CLKOUT_PTB0: clkout_ptb0 {
120		nxp,kinetis-port-pins = < 0 7 >;
121	};
122	ADC0_SE1_PTB1: CMP0_IN5_PTB1: adc0_se1_ptb1 {
123		nxp,kinetis-port-pins = < 1 0 >;
124	};
125	PTB1: GPIOB_PTB1: gpiob_ptb1 {
126		nxp,kinetis-port-pins = < 1 1 >;
127	};
128	DTM_RX_PTB1: dtm_rx_ptb1 {
129		nxp,kinetis-port-pins = < 1 2 >;
130	};
131	I2C0_SDA_PTB1: i2c0_sda_ptb1 {
132		nxp,kinetis-port-pins = < 1 3 >;
133	};
134	LPTMR0_ALT1_PTB1: lptmr0_alt1_ptb1 {
135		nxp,kinetis-port-pins = < 1 4 >;
136	};
137	TPM0_CH2_PTB1: tpm0_ch2_ptb1 {
138		nxp,kinetis-port-pins = < 1 5 >;
139	};
140	CMT_IRO_PTB1: cmt_iro_ptb1 {
141		nxp,kinetis-port-pins = < 1 7 >;
142	};
143	ADC0_SE3_PTB2: CMP0_IN3_PTB2: adc0_se3_ptb2 {
144		nxp,kinetis-port-pins = < 2 0 >;
145	};
146	PTB2: GPIOB_PTB2: gpiob_ptb2 {
147		nxp,kinetis-port-pins = < 2 1 >;
148	};
149	RF_NOT_ALLOWED_PTB2: rf_not_allowed_ptb2 {
150		nxp,kinetis-port-pins = < 2 2 >;
151	};
152	DTM_TX_PTB2: dtm_tx_ptb2 {
153		nxp,kinetis-port-pins = < 2 3 >;
154	};
155	TPM1_CH0_PTB2: tpm1_ch0_ptb2 {
156		nxp,kinetis-port-pins = < 2 5 >;
157	};
158	ADC0_SE2_PTB3: CMP0_IN4_PTB3: adc0_se2_ptb3 {
159		nxp,kinetis-port-pins = < 3 0 >;
160	};
161	PTB3: GPIOB_PTB3: gpiob_ptb3 {
162		nxp,kinetis-port-pins = < 3 1 >;
163	};
164	CLKOUT_PTB3: clkout_ptb3 {
165		nxp,kinetis-port-pins = < 3 4 >;
166	};
167	TPM1_CH1_PTB3: tpm1_ch1_ptb3 {
168		nxp,kinetis-port-pins = < 3 5 >;
169	};
170	RTC_CLKOUT_PTB3: rtc_clkout_ptb3 {
171		nxp,kinetis-port-pins = < 3 7 >;
172	};
173	EXTAL32K_PTB16: extal32k_ptb16 {
174		nxp,kinetis-port-pins = < 16 0 >;
175	};
176	PTB16: GPIOB_PTB16: gpiob_ptb16 {
177		nxp,kinetis-port-pins = < 16 1 >;
178	};
179	I2C1_SCL_PTB16: i2c1_scl_ptb16 {
180		nxp,kinetis-port-pins = < 16 3 >;
181	};
182	TPM2_CH0_PTB16: tpm2_ch0_ptb16 {
183		nxp,kinetis-port-pins = < 16 5 >;
184	};
185	XTAL32K_PTB17: xtal32k_ptb17 {
186		nxp,kinetis-port-pins = < 17 0 >;
187	};
188	PTB17: GPIOB_PTB17: gpiob_ptb17 {
189		nxp,kinetis-port-pins = < 17 1 >;
190	};
191	I2C1_SDA_PTB17: i2c1_sda_ptb17 {
192		nxp,kinetis-port-pins = < 17 3 >;
193	};
194	TPM2_CH1_PTB17: tpm2_ch1_ptb17 {
195		nxp,kinetis-port-pins = < 17 5 >;
196	};
197	BSM_CLK_PTB17: bsm_clk_ptb17 {
198		nxp,kinetis-port-pins = < 17 7 >;
199	};
200	DAC0_OUT_PTB18: ADC0_SE4_PTB18: CMP0_IN2_PTB18: dac0_out_ptb18 {
201		nxp,kinetis-port-pins = < 18 0 >;
202	};
203	PTB18: GPIOB_PTB18: gpiob_ptb18 {
204		nxp,kinetis-port-pins = < 18 1 >;
205	};
206	I2C1_SCL_PTB18: i2c1_scl_ptb18 {
207		nxp,kinetis-port-pins = < 18 3 >;
208	};
209	TPM_CLKIN0_PTB18: tpm_clkin0_ptb18 {
210		nxp,kinetis-port-pins = < 18 4 >;
211	};
212	TPM0_CH0_PTB18: tpm0_ch0_ptb18 {
213		nxp,kinetis-port-pins = < 18 5 >;
214	};
215	NMI_b_PTB18: nmi_b_ptb18 {
216		nxp,kinetis-port-pins = < 18 7 >;
217	};
218};
219
220&portc {
221	PTC1: GPIOC_PTC1: gpioc_ptc1 {
222		nxp,kinetis-port-pins = < 1 1 >;
223	};
224	ANT_B_PTC1: ant_b_ptc1 {
225		nxp,kinetis-port-pins = < 1 2 >;
226	};
227	I2C0_SDA_PTC1: i2c0_sda_ptc1 {
228		nxp,kinetis-port-pins = < 1 3 >;
229	};
230	UART0_RTS_b_PTC1: uart0_rts_b_ptc1 {
231		nxp,kinetis-port-pins = < 1 4 >;
232	};
233	TPM0_CH2_PTC1: tpm0_ch2_ptc1 {
234		nxp,kinetis-port-pins = < 1 5 >;
235	};
236	BLE_RF_ACTIVE_PTC1: ble_rf_active_ptc1 {
237		nxp,kinetis-port-pins = < 1 7 >;
238	};
239	TSI0_CH14_PTC2: tsi0_ch14_ptc2 {
240		nxp,kinetis-port-pins = < 2 0 >;
241	};
242	PTC2: GPIOC_PTC2: LLWU_P10_PTC2: gpioc_ptc2 {
243		nxp,kinetis-port-pins = < 2 1 >;
244	};
245	TX_SWITCH_PTC2: tx_switch_ptc2 {
246		nxp,kinetis-port-pins = < 2 2 >;
247	};
248	I2C1_SCL_PTC2: i2c1_scl_ptc2 {
249		nxp,kinetis-port-pins = < 2 3 >;
250	};
251	UART0_RX_PTC2: uart0_rx_ptc2 {
252		nxp,kinetis-port-pins = < 2 4 >;
253	};
254	CMT_IRO_PTC2: cmt_iro_ptc2 {
255		nxp,kinetis-port-pins = < 2 5 >;
256	};
257	DTM_RX_PTC2: dtm_rx_ptc2 {
258		nxp,kinetis-port-pins = < 2 7 >;
259	};
260	TSI0_CH15_PTC3: tsi0_ch15_ptc3 {
261		nxp,kinetis-port-pins = < 3 0 >;
262	};
263	PTC3: GPIOC_PTC3: LLWU_P11_PTC3: gpioc_ptc3 {
264		nxp,kinetis-port-pins = < 3 1 >;
265	};
266	RX_SWITCH_PTC3: rx_switch_ptc3 {
267		nxp,kinetis-port-pins = < 3 2 >;
268	};
269	I2C1_SDA_PTC3: i2c1_sda_ptc3 {
270		nxp,kinetis-port-pins = < 3 3 >;
271	};
272	UART0_TX_PTC3: uart0_tx_ptc3 {
273		nxp,kinetis-port-pins = < 3 4 >;
274	};
275	TPM0_CH1_PTC3: tpm0_ch1_ptc3 {
276		nxp,kinetis-port-pins = < 3 5 >;
277	};
278	DTM_TX_PTC3: dtm_tx_ptc3 {
279		nxp,kinetis-port-pins = < 3 7 >;
280	};
281	TSI0_CH0_PTC4: tsi0_ch0_ptc4 {
282		nxp,kinetis-port-pins = < 4 0 >;
283	};
284	PTC4: GPIOC_PTC4: LLWU_P12_PTC4: gpioc_ptc4 {
285		nxp,kinetis-port-pins = < 4 1 >;
286	};
287	ANT_A_PTC4: ant_a_ptc4 {
288		nxp,kinetis-port-pins = < 4 2 >;
289	};
290	EXTRG_IN_PTC4: extrg_in_ptc4 {
291		nxp,kinetis-port-pins = < 4 3 >;
292	};
293	UART0_CTS_b_PTC4: uart0_cts_b_ptc4 {
294		nxp,kinetis-port-pins = < 4 4 >;
295	};
296	TPM1_CH0_PTC4: tpm1_ch0_ptc4 {
297		nxp,kinetis-port-pins = < 4 5 >;
298	};
299	BSM_DATA_PTC4: bsm_data_ptc4 {
300		nxp,kinetis-port-pins = < 4 7 >;
301	};
302	TSI0_CH1_PTC5: tsi0_ch1_ptc5 {
303		nxp,kinetis-port-pins = < 5 0 >;
304	};
305	PTC5: GPIOC_PTC5: LLWU_P13_PTC5: gpioc_ptc5 {
306		nxp,kinetis-port-pins = < 5 1 >;
307	};
308	RF_NOT_ALLOWED_PTC5: rf_not_allowed_ptc5 {
309		nxp,kinetis-port-pins = < 5 2 >;
310	};
311	LPTMR0_ALT2_PTC5: lptmr0_alt2_ptc5 {
312		nxp,kinetis-port-pins = < 5 3 >;
313	};
314	UART0_RTS_b_PTC5: uart0_rts_b_ptc5 {
315		nxp,kinetis-port-pins = < 5 4 >;
316	};
317	TPM1_CH1_PTC5: tpm1_ch1_ptc5 {
318		nxp,kinetis-port-pins = < 5 5 >;
319	};
320	BSM_CLK_PTC5: bsm_clk_ptc5 {
321		nxp,kinetis-port-pins = < 5 7 >;
322	};
323	TSI0_CH2_PTC6: tsi0_ch2_ptc6 {
324		nxp,kinetis-port-pins = < 6 0 >;
325	};
326	PTC6: GPIOC_PTC6: LLWU_P14_PTC6: XTAL_OUT_EN_PTC6: gpioc_ptc6 {
327		nxp,kinetis-port-pins = < 6 1 >;
328	};
329	I2C1_SCL_PTC6: i2c1_scl_ptc6 {
330		nxp,kinetis-port-pins = < 6 3 >;
331	};
332	UART0_RX_PTC6: uart0_rx_ptc6 {
333		nxp,kinetis-port-pins = < 6 4 >;
334	};
335	TPM2_CH0_PTC6: tpm2_ch0_ptc6 {
336		nxp,kinetis-port-pins = < 6 5 >;
337	};
338	BSM_FRAME_PTC6: bsm_frame_ptc6 {
339		nxp,kinetis-port-pins = < 6 7 >;
340	};
341	TSI0_CH3_PTC7: tsi0_ch3_ptc7 {
342		nxp,kinetis-port-pins = < 7 0 >;
343	};
344	PTC7: GPIOC_PTC7: LLWU_P15_PTC7: gpioc_ptc7 {
345		nxp,kinetis-port-pins = < 7 1 >;
346	};
347	SPI0_PCS2_PTC7: spi0_pcs2_ptc7 {
348		nxp,kinetis-port-pins = < 7 2 >;
349	};
350	I2C1_SDA_PTC7: i2c1_sda_ptc7 {
351		nxp,kinetis-port-pins = < 7 3 >;
352	};
353	UART0_TX_PTC7: uart0_tx_ptc7 {
354		nxp,kinetis-port-pins = < 7 4 >;
355	};
356	TPM2_CH1_PTC7: tpm2_ch1_ptc7 {
357		nxp,kinetis-port-pins = < 7 5 >;
358	};
359	BSM_DATA_PTC7: bsm_data_ptc7 {
360		nxp,kinetis-port-pins = < 7 7 >;
361	};
362	TSI0_CH4_PTC16: tsi0_ch4_ptc16 {
363		nxp,kinetis-port-pins = < 16 0 >;
364	};
365	PTC16: GPIOC_PTC16: LLWU_P0_PTC16: gpioc_ptc16 {
366		nxp,kinetis-port-pins = < 16 1 >;
367	};
368	SPI0_SCK_PTC16: spi0_sck_ptc16 {
369		nxp,kinetis-port-pins = < 16 2 >;
370	};
371	I2C0_SDA_PTC16: i2c0_sda_ptc16 {
372		nxp,kinetis-port-pins = < 16 3 >;
373	};
374	UART0_RTS_b_PTC16: uart0_rts_b_ptc16 {
375		nxp,kinetis-port-pins = < 16 4 >;
376	};
377	TPM0_CH3_PTC16: tpm0_ch3_ptc16 {
378		nxp,kinetis-port-pins = < 16 5 >;
379	};
380	TSI0_CH5_PTC17: tsi0_ch5_ptc17 {
381		nxp,kinetis-port-pins = < 17 0 >;
382	};
383	PTC17: GPIOC_PTC17: LLWU_P1_PTC17: gpioc_ptc17 {
384		nxp,kinetis-port-pins = < 17 1 >;
385	};
386	SPI0_SOUT_PTC17: spi0_sout_ptc17 {
387		nxp,kinetis-port-pins = < 17 2 >;
388	};
389	I2C1_SCL_PTC17: i2c1_scl_ptc17 {
390		nxp,kinetis-port-pins = < 17 3 >;
391	};
392	UART0_RX_PTC17: uart0_rx_ptc17 {
393		nxp,kinetis-port-pins = < 17 4 >;
394	};
395	BSM_FRAME_PTC17: bsm_frame_ptc17 {
396		nxp,kinetis-port-pins = < 17 5 >;
397	};
398	DTM_RX_PTC17: dtm_rx_ptc17 {
399		nxp,kinetis-port-pins = < 17 7 >;
400	};
401	TSI0_CH6_PTC18: tsi0_ch6_ptc18 {
402		nxp,kinetis-port-pins = < 18 0 >;
403	};
404	PTC18: GPIOC_PTC18: LLWU_P2_PTC18: gpioc_ptc18 {
405		nxp,kinetis-port-pins = < 18 1 >;
406	};
407	SPI0_SIN_PTC18: spi0_sin_ptc18 {
408		nxp,kinetis-port-pins = < 18 2 >;
409	};
410	I2C1_SDA_PTC18: i2c1_sda_ptc18 {
411		nxp,kinetis-port-pins = < 18 3 >;
412	};
413	UART0_TX_PTC18: uart0_tx_ptc18 {
414		nxp,kinetis-port-pins = < 18 4 >;
415	};
416	BSM_DATA_PTC18: bsm_data_ptc18 {
417		nxp,kinetis-port-pins = < 18 5 >;
418	};
419	DTM_TX_PTC18: dtm_tx_ptc18 {
420		nxp,kinetis-port-pins = < 18 7 >;
421	};
422	TSI0_CH7_PTC19: tsi0_ch7_ptc19 {
423		nxp,kinetis-port-pins = < 19 0 >;
424	};
425	PTC19: GPIOC_PTC19: LLWU_P3_PTC19: gpioc_ptc19 {
426		nxp,kinetis-port-pins = < 19 1 >;
427	};
428	SPI0_PCS0_PTC19: spi0_pcs0_ptc19 {
429		nxp,kinetis-port-pins = < 19 2 >;
430	};
431	I2C0_SCL_PTC19: i2c0_scl_ptc19 {
432		nxp,kinetis-port-pins = < 19 3 >;
433	};
434	UART0_CTS_b_PTC19: uart0_cts_b_ptc19 {
435		nxp,kinetis-port-pins = < 19 4 >;
436	};
437	BSM_CLK_PTC19: bsm_clk_ptc19 {
438		nxp,kinetis-port-pins = < 19 5 >;
439	};
440	BLE_RF_ACTIVE_PTC19: ble_rf_active_ptc19 {
441		nxp,kinetis-port-pins = < 19 7 >;
442	};
443};
444
445