1/*
2 * NOTE: Autogenerated file by kinetis_signal2dts.py
3 *       for MKE16F256VLH16/signal_configuration.xml
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8/*
9 * Pin nodes are of the form:
10 *
11 *	<SIGNAL[0..n]>: <signal[0]> {
12 *		nxp,kinetis-port-pins = < PIN PCR[MUX] >;
13 *	};
14 */
15
16&porta {
17	ADC0_SE0_PTA0: ACMP0_IN0_PTA0: adc0_se0_pta0 {
18		nxp,kinetis-port-pins = < 0 0 >;
19	};
20	PTA0: GPIOA_PTA0: gpioa_pta0 {
21		nxp,kinetis-port-pins = < 0 1 >;
22	};
23	FTM2_CH1_PTA0: ftm2_ch1_pta0 {
24		nxp,kinetis-port-pins = < 0 2 >;
25	};
26	LPI2C0_SCLS_PTA0: lpi2c0_scls_pta0 {
27		nxp,kinetis-port-pins = < 0 3 >;
28	};
29	FXIO_D2_PTA0: fxio_d2_pta0 {
30		nxp,kinetis-port-pins = < 0 4 >;
31	};
32	FTM2_QD_PHA_PTA0: ftm2_qd_pha_pta0 {
33		nxp,kinetis-port-pins = < 0 5 >;
34	};
35	LPUART0_CTS_PTA0: lpuart0_cts_pta0 {
36		nxp,kinetis-port-pins = < 0 6 >;
37	};
38	TRGMUX_OUT3_PTA0: trgmux_out3_pta0 {
39		nxp,kinetis-port-pins = < 0 7 >;
40	};
41	ADC0_SE1_PTA1: ACMP0_IN1_PTA1: adc0_se1_pta1 {
42		nxp,kinetis-port-pins = < 1 0 >;
43	};
44	PTA1: GPIOA_PTA1: gpioa_pta1 {
45		nxp,kinetis-port-pins = < 1 1 >;
46	};
47	FTM1_CH1_PTA1: ftm1_ch1_pta1 {
48		nxp,kinetis-port-pins = < 1 2 >;
49	};
50	LPI2C0_SDAS_PTA1: lpi2c0_sdas_pta1 {
51		nxp,kinetis-port-pins = < 1 3 >;
52	};
53	FXIO_D3_PTA1: fxio_d3_pta1 {
54		nxp,kinetis-port-pins = < 1 4 >;
55	};
56	FTM1_QD_PHA_PTA1: ftm1_qd_pha_pta1 {
57		nxp,kinetis-port-pins = < 1 5 >;
58	};
59	LPUART0_RTS_PTA1: lpuart0_rts_pta1 {
60		nxp,kinetis-port-pins = < 1 6 >;
61	};
62	TRGMUX_OUT0_PTA1: trgmux_out0_pta1 {
63		nxp,kinetis-port-pins = < 1 7 >;
64	};
65	ADC1_SE0_PTA2: adc1_se0_pta2 {
66		nxp,kinetis-port-pins = < 2 0 >;
67	};
68	PTA2: GPIOA_PTA2: gpioa_pta2 {
69		nxp,kinetis-port-pins = < 2 1 >;
70	};
71	FTM3_CH0_PTA2: ftm3_ch0_pta2 {
72		nxp,kinetis-port-pins = < 2 2 >;
73	};
74	LPI2C0_SDA_PTA2: lpi2c0_sda_pta2 {
75		nxp,kinetis-port-pins = < 2 3 >;
76	};
77	EWM_OUT_b_PTA2: ewm_out_b_pta2 {
78		nxp,kinetis-port-pins = < 2 4 >;
79	};
80	LPUART0_RX_PTA2: lpuart0_rx_pta2 {
81		nxp,kinetis-port-pins = < 2 6 >;
82	};
83	ADC1_SE1_PTA3: adc1_se1_pta3 {
84		nxp,kinetis-port-pins = < 3 0 >;
85	};
86	PTA3: GPIOA_PTA3: gpioa_pta3 {
87		nxp,kinetis-port-pins = < 3 1 >;
88	};
89	FTM3_CH1_PTA3: ftm3_ch1_pta3 {
90		nxp,kinetis-port-pins = < 3 2 >;
91	};
92	LPI2C0_SCL_PTA3: lpi2c0_scl_pta3 {
93		nxp,kinetis-port-pins = < 3 3 >;
94	};
95	EWM_IN_PTA3: ewm_in_pta3 {
96		nxp,kinetis-port-pins = < 3 4 >;
97	};
98	LPUART0_TX_PTA3: lpuart0_tx_pta3 {
99		nxp,kinetis-port-pins = < 3 6 >;
100	};
101	PTA4: GPIOA_PTA4: gpioa_pta4 {
102		nxp,kinetis-port-pins = < 4 1 >;
103	};
104	ACMP0_OUT_PTA4: acmp0_out_pta4 {
105		nxp,kinetis-port-pins = < 4 4 >;
106	};
107	EWM_OUT_b_PTA4: ewm_out_b_pta4 {
108		nxp,kinetis-port-pins = < 4 5 >;
109	};
110	JTAG_TMS_PTA4: SWD_DIO_PTA4: jtag_tms_pta4 {
111		nxp,kinetis-port-pins = < 4 7 >;
112	};
113	PTA5: GPIOA_PTA5: gpioa_pta5 {
114		nxp,kinetis-port-pins = < 5 1 >;
115	};
116	TCLK1_PTA5: tclk1_pta5 {
117		nxp,kinetis-port-pins = < 5 3 >;
118	};
119	JTAG_TRST_b_PTA5: jtag_trst_b_pta5 {
120		nxp,kinetis-port-pins = < 5 6 >;
121	};
122	RESET_b_PTA5: reset_b_pta5 {
123		nxp,kinetis-port-pins = < 5 7 >;
124	};
125	ADC0_SE2_PTA6: ACMP1_IN0_PTA6: adc0_se2_pta6 {
126		nxp,kinetis-port-pins = < 6 0 >;
127	};
128	PTA6: GPIOA_PTA6: gpioa_pta6 {
129		nxp,kinetis-port-pins = < 6 1 >;
130	};
131	FTM0_FLT1_PTA6: ftm0_flt1_pta6 {
132		nxp,kinetis-port-pins = < 6 2 >;
133	};
134	LPSPI1_PCS1_PTA6: lpspi1_pcs1_pta6 {
135		nxp,kinetis-port-pins = < 6 3 >;
136	};
137	LPUART1_CTS_PTA6: lpuart1_cts_pta6 {
138		nxp,kinetis-port-pins = < 6 6 >;
139	};
140	ADC0_SE3_PTA7: ACMP1_IN1_PTA7: adc0_se3_pta7 {
141		nxp,kinetis-port-pins = < 7 0 >;
142	};
143	PTA7: GPIOA_PTA7: gpioa_pta7 {
144		nxp,kinetis-port-pins = < 7 1 >;
145	};
146	FTM0_FLT2_PTA7: ftm0_flt2_pta7 {
147		nxp,kinetis-port-pins = < 7 2 >;
148	};
149	RTC_CLKIN_PTA7: rtc_clkin_pta7 {
150		nxp,kinetis-port-pins = < 7 4 >;
151	};
152	LPUART1_RTS_PTA7: lpuart1_rts_pta7 {
153		nxp,kinetis-port-pins = < 7 6 >;
154	};
155	PTA10: GPIOA_PTA10: gpioa_pta10 {
156		nxp,kinetis-port-pins = < 10 1 >;
157	};
158	FTM1_CH4_PTA10: ftm1_ch4_pta10 {
159		nxp,kinetis-port-pins = < 10 2 >;
160	};
161	LPUART0_TX_PTA10: lpuart0_tx_pta10 {
162		nxp,kinetis-port-pins = < 10 3 >;
163	};
164	FXIO_D0_PTA10: fxio_d0_pta10 {
165		nxp,kinetis-port-pins = < 10 4 >;
166	};
167	JTAG_TDO_PTA10: noetm_Trace_SWO_PTA10: jtag_tdo_pta10 {
168		nxp,kinetis-port-pins = < 10 7 >;
169	};
170	PTA11: GPIOA_PTA11: gpioa_pta11 {
171		nxp,kinetis-port-pins = < 11 1 >;
172	};
173	FTM1_CH5_PTA11: ftm1_ch5_pta11 {
174		nxp,kinetis-port-pins = < 11 2 >;
175	};
176	LPUART0_RX_PTA11: lpuart0_rx_pta11 {
177		nxp,kinetis-port-pins = < 11 3 >;
178	};
179	FXIO_D1_PTA11: fxio_d1_pta11 {
180		nxp,kinetis-port-pins = < 11 4 >;
181	};
182	ADC2_SE5_PTA12: adc2_se5_pta12 {
183		nxp,kinetis-port-pins = < 12 0 >;
184	};
185	PTA12: GPIOA_PTA12: gpioa_pta12 {
186		nxp,kinetis-port-pins = < 12 1 >;
187	};
188	FTM1_CH6_PTA12: ftm1_ch6_pta12 {
189		nxp,kinetis-port-pins = < 12 2 >;
190	};
191	LPI2C1_SDAS_PTA12: lpi2c1_sdas_pta12 {
192		nxp,kinetis-port-pins = < 12 4 >;
193	};
194	ADC2_SE4_PTA13: adc2_se4_pta13 {
195		nxp,kinetis-port-pins = < 13 0 >;
196	};
197	PTA13: GPIOA_PTA13: gpioa_pta13 {
198		nxp,kinetis-port-pins = < 13 1 >;
199	};
200	FTM1_CH7_PTA13: ftm1_ch7_pta13 {
201		nxp,kinetis-port-pins = < 13 2 >;
202	};
203	LPI2C1_SCLS_PTA13: lpi2c1_scls_pta13 {
204		nxp,kinetis-port-pins = < 13 4 >;
205	};
206};
207
208&portb {
209	ADC0_SE4_PTB0: ADC1_SE14_PTB0: adc0_se4_ptb0 {
210		nxp,kinetis-port-pins = < 0 0 >;
211	};
212	PTB0: GPIOB_PTB0: gpiob_ptb0 {
213		nxp,kinetis-port-pins = < 0 1 >;
214	};
215	LPUART0_RX_PTB0: lpuart0_rx_ptb0 {
216		nxp,kinetis-port-pins = < 0 2 >;
217	};
218	LPSPI0_PCS0_PTB0: lpspi0_pcs0_ptb0 {
219		nxp,kinetis-port-pins = < 0 3 >;
220	};
221	LPTMR0_ALT3_PTB0: lptmr0_alt3_ptb0 {
222		nxp,kinetis-port-pins = < 0 4 >;
223	};
224	PWT_IN3_PTB0: pwt_in3_ptb0 {
225		nxp,kinetis-port-pins = < 0 5 >;
226	};
227	ADC0_SE5_PTB1: ADC1_SE15_PTB1: adc0_se5_ptb1 {
228		nxp,kinetis-port-pins = < 1 0 >;
229	};
230	PTB1: GPIOB_PTB1: gpiob_ptb1 {
231		nxp,kinetis-port-pins = < 1 1 >;
232	};
233	LPUART0_TX_PTB1: lpuart0_tx_ptb1 {
234		nxp,kinetis-port-pins = < 1 2 >;
235	};
236	LPSPI0_SOUT_PTB1: lpspi0_sout_ptb1 {
237		nxp,kinetis-port-pins = < 1 3 >;
238	};
239	TCLK0_PTB1: tclk0_ptb1 {
240		nxp,kinetis-port-pins = < 1 4 >;
241	};
242	ADC0_SE6_PTB2: adc0_se6_ptb2 {
243		nxp,kinetis-port-pins = < 2 0 >;
244	};
245	PTB2: GPIOB_PTB2: gpiob_ptb2 {
246		nxp,kinetis-port-pins = < 2 1 >;
247	};
248	FTM1_CH0_PTB2: ftm1_ch0_ptb2 {
249		nxp,kinetis-port-pins = < 2 2 >;
250	};
251	LPSPI0_SCK_PTB2: lpspi0_sck_ptb2 {
252		nxp,kinetis-port-pins = < 2 3 >;
253	};
254	FTM1_QD_PHB_PTB2: ftm1_qd_phb_ptb2 {
255		nxp,kinetis-port-pins = < 2 4 >;
256	};
257	TRGMUX_IN3_PTB2: trgmux_in3_ptb2 {
258		nxp,kinetis-port-pins = < 2 6 >;
259	};
260	ADC0_SE7_PTB3: adc0_se7_ptb3 {
261		nxp,kinetis-port-pins = < 3 0 >;
262	};
263	PTB3: GPIOB_PTB3: gpiob_ptb3 {
264		nxp,kinetis-port-pins = < 3 1 >;
265	};
266	FTM1_CH1_PTB3: ftm1_ch1_ptb3 {
267		nxp,kinetis-port-pins = < 3 2 >;
268	};
269	LPSPI0_SIN_PTB3: lpspi0_sin_ptb3 {
270		nxp,kinetis-port-pins = < 3 3 >;
271	};
272	FTM1_QD_PHA_PTB3: ftm1_qd_pha_ptb3 {
273		nxp,kinetis-port-pins = < 3 4 >;
274	};
275	TRGMUX_IN2_PTB3: trgmux_in2_ptb3 {
276		nxp,kinetis-port-pins = < 3 6 >;
277	};
278	ACMP1_IN2_PTB4: acmp1_in2_ptb4 {
279		nxp,kinetis-port-pins = < 4 0 >;
280	};
281	PTB4: GPIOB_PTB4: gpiob_ptb4 {
282		nxp,kinetis-port-pins = < 4 1 >;
283	};
284	FTM0_CH4_PTB4: ftm0_ch4_ptb4 {
285		nxp,kinetis-port-pins = < 4 2 >;
286	};
287	LPSPI0_SOUT_PTB4: lpspi0_sout_ptb4 {
288		nxp,kinetis-port-pins = < 4 3 >;
289	};
290	TRGMUX_IN1_PTB4: trgmux_in1_ptb4 {
291		nxp,kinetis-port-pins = < 4 6 >;
292	};
293	PTB5: GPIOB_PTB5: gpiob_ptb5 {
294		nxp,kinetis-port-pins = < 5 1 >;
295	};
296	FTM0_CH5_PTB5: ftm0_ch5_ptb5 {
297		nxp,kinetis-port-pins = < 5 2 >;
298	};
299	LPSPI0_PCS1_PTB5: lpspi0_pcs1_ptb5 {
300		nxp,kinetis-port-pins = < 5 3 >;
301	};
302	TRGMUX_IN0_PTB5: trgmux_in0_ptb5 {
303		nxp,kinetis-port-pins = < 5 6 >;
304	};
305	ACMP1_OUT_PTB5: acmp1_out_ptb5 {
306		nxp,kinetis-port-pins = < 5 7 >;
307	};
308	XTAL_PTB6: xtal_ptb6 {
309		nxp,kinetis-port-pins = < 6 0 >;
310	};
311	PTB6: GPIOB_PTB6: gpiob_ptb6 {
312		nxp,kinetis-port-pins = < 6 1 >;
313	};
314	LPI2C0_SDA_PTB6: lpi2c0_sda_ptb6 {
315		nxp,kinetis-port-pins = < 6 2 >;
316	};
317	EXTAL_PTB7: extal_ptb7 {
318		nxp,kinetis-port-pins = < 7 0 >;
319	};
320	PTB7: GPIOB_PTB7: gpiob_ptb7 {
321		nxp,kinetis-port-pins = < 7 1 >;
322	};
323	LPI2C0_SCL_PTB7: lpi2c0_scl_ptb7 {
324		nxp,kinetis-port-pins = < 7 2 >;
325	};
326	ADC1_SE7_PTB12: adc1_se7_ptb12 {
327		nxp,kinetis-port-pins = < 12 0 >;
328	};
329	PTB12: GPIOB_PTB12: gpiob_ptb12 {
330		nxp,kinetis-port-pins = < 12 1 >;
331	};
332	FTM0_CH0_PTB12: ftm0_ch0_ptb12 {
333		nxp,kinetis-port-pins = < 12 2 >;
334	};
335	FTM3_FLT2_PTB12: ftm3_flt2_ptb12 {
336		nxp,kinetis-port-pins = < 12 3 >;
337	};
338	ADC1_SE8_PTB13: ADC2_SE8_PTB13: adc1_se8_ptb13 {
339		nxp,kinetis-port-pins = < 13 0 >;
340	};
341	PTB13: GPIOB_PTB13: gpiob_ptb13 {
342		nxp,kinetis-port-pins = < 13 1 >;
343	};
344	FTM0_CH1_PTB13: ftm0_ch1_ptb13 {
345		nxp,kinetis-port-pins = < 13 2 >;
346	};
347	FTM3_FLT1_PTB13: ftm3_flt1_ptb13 {
348		nxp,kinetis-port-pins = < 13 3 >;
349	};
350};
351
352&portc {
353	ADC0_SE8_PTC0: ACMP1_IN4_PTC0: adc0_se8_ptc0 {
354		nxp,kinetis-port-pins = < 0 0 >;
355	};
356	PTC0: GPIOC_PTC0: gpioc_ptc0 {
357		nxp,kinetis-port-pins = < 0 1 >;
358	};
359	FTM0_CH0_PTC0: ftm0_ch0_ptc0 {
360		nxp,kinetis-port-pins = < 0 2 >;
361	};
362	FTM1_CH6_PTC0: ftm1_ch6_ptc0 {
363		nxp,kinetis-port-pins = < 0 6 >;
364	};
365	ADC0_SE9_PTC1: ACMP1_IN3_PTC1: adc0_se9_ptc1 {
366		nxp,kinetis-port-pins = < 1 0 >;
367	};
368	PTC1: GPIOC_PTC1: gpioc_ptc1 {
369		nxp,kinetis-port-pins = < 1 1 >;
370	};
371	FTM0_CH1_PTC1: ftm0_ch1_ptc1 {
372		nxp,kinetis-port-pins = < 1 2 >;
373	};
374	FTM1_CH7_PTC1: ftm1_ch7_ptc1 {
375		nxp,kinetis-port-pins = < 1 6 >;
376	};
377	ADC0_SE10_PTC2: ACMP0_IN5_PTC2: XTAL32_PTC2: adc0_se10_ptc2 {
378		nxp,kinetis-port-pins = < 2 0 >;
379	};
380	PTC2: GPIOC_PTC2: gpioc_ptc2 {
381		nxp,kinetis-port-pins = < 2 1 >;
382	};
383	FTM0_CH2_PTC2: ftm0_ch2_ptc2 {
384		nxp,kinetis-port-pins = < 2 2 >;
385	};
386	CAN0_RX_PTC2: can0_rx_ptc2 {
387		nxp,kinetis-port-pins = < 2 3 >;
388	};
389	ADC0_SE11_PTC3: ACMP0_IN4_PTC3: EXTAL32_PTC3: adc0_se11_ptc3 {
390		nxp,kinetis-port-pins = < 3 0 >;
391	};
392	PTC3: GPIOC_PTC3: gpioc_ptc3 {
393		nxp,kinetis-port-pins = < 3 1 >;
394	};
395	FTM0_CH3_PTC3: ftm0_ch3_ptc3 {
396		nxp,kinetis-port-pins = < 3 2 >;
397	};
398	CAN0_TX_PTC3: can0_tx_ptc3 {
399		nxp,kinetis-port-pins = < 3 3 >;
400	};
401	ACMP0_IN2_PTC4: acmp0_in2_ptc4 {
402		nxp,kinetis-port-pins = < 4 0 >;
403	};
404	PTC4: GPIOC_PTC4: gpioc_ptc4 {
405		nxp,kinetis-port-pins = < 4 1 >;
406	};
407	FTM1_CH0_PTC4: ftm1_ch0_ptc4 {
408		nxp,kinetis-port-pins = < 4 2 >;
409	};
410	RTC_CLKOUT_PTC4: rtc_clkout_ptc4 {
411		nxp,kinetis-port-pins = < 4 3 >;
412	};
413	EWM_IN_PTC4: ewm_in_ptc4 {
414		nxp,kinetis-port-pins = < 4 5 >;
415	};
416	FTM1_QD_PHB_PTC4: ftm1_qd_phb_ptc4 {
417		nxp,kinetis-port-pins = < 4 6 >;
418	};
419	JTAG_TCLK_PTC4: SWD_CLK_PTC4: jtag_tclk_ptc4 {
420		nxp,kinetis-port-pins = < 4 7 >;
421	};
422	PTC5: GPIOC_PTC5: gpioc_ptc5 {
423		nxp,kinetis-port-pins = < 5 1 >;
424	};
425	FTM2_CH0_PTC5: ftm2_ch0_ptc5 {
426		nxp,kinetis-port-pins = < 5 2 >;
427	};
428	RTC_CLKOUT_PTC5: rtc_clkout_ptc5 {
429		nxp,kinetis-port-pins = < 5 3 >;
430	};
431	LPI2C1_HREQ_PTC5: lpi2c1_hreq_ptc5 {
432		nxp,kinetis-port-pins = < 5 4 >;
433	};
434	FTM2_QD_PHB_PTC5: ftm2_qd_phb_ptc5 {
435		nxp,kinetis-port-pins = < 5 6 >;
436	};
437	JTAG_TDI_PTC5: jtag_tdi_ptc5 {
438		nxp,kinetis-port-pins = < 5 7 >;
439	};
440	ADC1_SE4_PTC6: adc1_se4_ptc6 {
441		nxp,kinetis-port-pins = < 6 0 >;
442	};
443	PTC6: GPIOC_PTC6: gpioc_ptc6 {
444		nxp,kinetis-port-pins = < 6 1 >;
445	};
446	LPUART1_RX_PTC6: lpuart1_rx_ptc6 {
447		nxp,kinetis-port-pins = < 6 2 >;
448	};
449	FTM3_CH2_PTC6: ftm3_ch2_ptc6 {
450		nxp,kinetis-port-pins = < 6 4 >;
451	};
452	ADC1_SE5_PTC7: adc1_se5_ptc7 {
453		nxp,kinetis-port-pins = < 7 0 >;
454	};
455	PTC7: GPIOC_PTC7: gpioc_ptc7 {
456		nxp,kinetis-port-pins = < 7 1 >;
457	};
458	LPUART1_TX_PTC7: lpuart1_tx_ptc7 {
459		nxp,kinetis-port-pins = < 7 2 >;
460	};
461	FTM3_CH3_PTC7: ftm3_ch3_ptc7 {
462		nxp,kinetis-port-pins = < 7 4 >;
463	};
464	ADC2_SE14_PTC8: adc2_se14_ptc8 {
465		nxp,kinetis-port-pins = < 8 0 >;
466	};
467	PTC8: GPIOC_PTC8: gpioc_ptc8 {
468		nxp,kinetis-port-pins = < 8 1 >;
469	};
470	LPUART1_RX_PTC8: lpuart1_rx_ptc8 {
471		nxp,kinetis-port-pins = < 8 2 >;
472	};
473	FTM1_FLT0_PTC8: ftm1_flt0_ptc8 {
474		nxp,kinetis-port-pins = < 8 3 >;
475	};
476	LPUART0_CTS_PTC8: lpuart0_cts_ptc8 {
477		nxp,kinetis-port-pins = < 8 6 >;
478	};
479	ADC2_SE15_PTC9: adc2_se15_ptc9 {
480		nxp,kinetis-port-pins = < 9 0 >;
481	};
482	PTC9: GPIOC_PTC9: gpioc_ptc9 {
483		nxp,kinetis-port-pins = < 9 1 >;
484	};
485	LPUART1_TX_PTC9: lpuart1_tx_ptc9 {
486		nxp,kinetis-port-pins = < 9 2 >;
487	};
488	FTM1_FLT1_PTC9: ftm1_flt1_ptc9 {
489		nxp,kinetis-port-pins = < 9 3 >;
490	};
491	LPUART0_RTS_PTC9: lpuart0_rts_ptc9 {
492		nxp,kinetis-port-pins = < 9 6 >;
493	};
494	ADC0_SE12_PTC14: ACMP2_IN5_PTC14: adc0_se12_ptc14 {
495		nxp,kinetis-port-pins = < 14 0 >;
496	};
497	PTC14: GPIOC_PTC14: gpioc_ptc14 {
498		nxp,kinetis-port-pins = < 14 1 >;
499	};
500	FTM1_CH2_PTC14: ftm1_ch2_ptc14 {
501		nxp,kinetis-port-pins = < 14 2 >;
502	};
503	ADC0_SE13_PTC15: ACMP2_IN4_PTC15: adc0_se13_ptc15 {
504		nxp,kinetis-port-pins = < 15 0 >;
505	};
506	PTC15: GPIOC_PTC15: gpioc_ptc15 {
507		nxp,kinetis-port-pins = < 15 1 >;
508	};
509	FTM1_CH3_PTC15: ftm1_ch3_ptc15 {
510		nxp,kinetis-port-pins = < 15 2 >;
511	};
512	ADC0_SE14_PTC16: adc0_se14_ptc16 {
513		nxp,kinetis-port-pins = < 16 0 >;
514	};
515	PTC16: GPIOC_PTC16: gpioc_ptc16 {
516		nxp,kinetis-port-pins = < 16 1 >;
517	};
518	FTM1_FLT2_PTC16: ftm1_flt2_ptc16 {
519		nxp,kinetis-port-pins = < 16 2 >;
520	};
521	LPI2C1_SDAS_PTC16: lpi2c1_sdas_ptc16 {
522		nxp,kinetis-port-pins = < 16 4 >;
523	};
524	ADC0_SE15_PTC17: adc0_se15_ptc17 {
525		nxp,kinetis-port-pins = < 17 0 >;
526	};
527	PTC17: GPIOC_PTC17: gpioc_ptc17 {
528		nxp,kinetis-port-pins = < 17 1 >;
529	};
530	FTM1_FLT3_PTC17: ftm1_flt3_ptc17 {
531		nxp,kinetis-port-pins = < 17 2 >;
532	};
533	LPI2C1_SCLS_PTC17: lpi2c1_scls_ptc17 {
534		nxp,kinetis-port-pins = < 17 4 >;
535	};
536};
537
538&portd {
539	ADC2_SE0_PTD0: adc2_se0_ptd0 {
540		nxp,kinetis-port-pins = < 0 0 >;
541	};
542	PTD0: GPIOD_PTD0: gpiod_ptd0 {
543		nxp,kinetis-port-pins = < 0 1 >;
544	};
545	FTM0_CH2_PTD0: ftm0_ch2_ptd0 {
546		nxp,kinetis-port-pins = < 0 2 >;
547	};
548	LPSPI1_SCK_PTD0: lpspi1_sck_ptd0 {
549		nxp,kinetis-port-pins = < 0 3 >;
550	};
551	FTM2_CH0_PTD0: ftm2_ch0_ptd0 {
552		nxp,kinetis-port-pins = < 0 4 >;
553	};
554	FXIO_D0_PTD0: fxio_d0_ptd0 {
555		nxp,kinetis-port-pins = < 0 6 >;
556	};
557	TRGMUX_OUT1_PTD0: trgmux_out1_ptd0 {
558		nxp,kinetis-port-pins = < 0 7 >;
559	};
560	ADC2_SE1_PTD1: adc2_se1_ptd1 {
561		nxp,kinetis-port-pins = < 1 0 >;
562	};
563	PTD1: GPIOD_PTD1: gpiod_ptd1 {
564		nxp,kinetis-port-pins = < 1 1 >;
565	};
566	FTM0_CH3_PTD1: ftm0_ch3_ptd1 {
567		nxp,kinetis-port-pins = < 1 2 >;
568	};
569	LPSPI1_SIN_PTD1: lpspi1_sin_ptd1 {
570		nxp,kinetis-port-pins = < 1 3 >;
571	};
572	FTM2_CH1_PTD1: ftm2_ch1_ptd1 {
573		nxp,kinetis-port-pins = < 1 4 >;
574	};
575	FXIO_D1_PTD1: fxio_d1_ptd1 {
576		nxp,kinetis-port-pins = < 1 6 >;
577	};
578	TRGMUX_OUT2_PTD1: trgmux_out2_ptd1 {
579		nxp,kinetis-port-pins = < 1 7 >;
580	};
581	ADC1_SE2_PTD2: adc1_se2_ptd2 {
582		nxp,kinetis-port-pins = < 2 0 >;
583	};
584	PTD2: GPIOD_PTD2: gpiod_ptd2 {
585		nxp,kinetis-port-pins = < 2 1 >;
586	};
587	FTM3_CH4_PTD2: ftm3_ch4_ptd2 {
588		nxp,kinetis-port-pins = < 2 2 >;
589	};
590	LPSPI1_SOUT_PTD2: lpspi1_sout_ptd2 {
591		nxp,kinetis-port-pins = < 2 3 >;
592	};
593	FXIO_D4_PTD2: fxio_d4_ptd2 {
594		nxp,kinetis-port-pins = < 2 4 >;
595	};
596	TRGMUX_IN5_PTD2: trgmux_in5_ptd2 {
597		nxp,kinetis-port-pins = < 2 6 >;
598	};
599	ADC1_SE3_PTD3: adc1_se3_ptd3 {
600		nxp,kinetis-port-pins = < 3 0 >;
601	};
602	PTD3: GPIOD_PTD3: gpiod_ptd3 {
603		nxp,kinetis-port-pins = < 3 1 >;
604	};
605	FTM3_CH5_PTD3: ftm3_ch5_ptd3 {
606		nxp,kinetis-port-pins = < 3 2 >;
607	};
608	LPSPI1_PCS0_PTD3: lpspi1_pcs0_ptd3 {
609		nxp,kinetis-port-pins = < 3 3 >;
610	};
611	FXIO_D5_PTD3: fxio_d5_ptd3 {
612		nxp,kinetis-port-pins = < 3 4 >;
613	};
614	TRGMUX_IN4_PTD3: trgmux_in4_ptd3 {
615		nxp,kinetis-port-pins = < 3 6 >;
616	};
617	NMI_b_PTD3: nmi_b_ptd3 {
618		nxp,kinetis-port-pins = < 3 7 >;
619	};
620	ADC1_SE6_PTD4: ACMP1_IN6_PTD4: adc1_se6_ptd4 {
621		nxp,kinetis-port-pins = < 4 0 >;
622	};
623	PTD4: GPIOD_PTD4: gpiod_ptd4 {
624		nxp,kinetis-port-pins = < 4 1 >;
625	};
626	FTM0_FLT3_PTD4: ftm0_flt3_ptd4 {
627		nxp,kinetis-port-pins = < 4 2 >;
628	};
629	FTM3_FLT3_PTD4: ftm3_flt3_ptd4 {
630		nxp,kinetis-port-pins = < 4 3 >;
631	};
632	PTD5: GPIOD_PTD5: gpiod_ptd5 {
633		nxp,kinetis-port-pins = < 5 1 >;
634	};
635	FTM2_CH3_PTD5: ftm2_ch3_ptd5 {
636		nxp,kinetis-port-pins = < 5 2 >;
637	};
638	LPTMR0_ALT2_PTD5: lptmr0_alt2_ptd5 {
639		nxp,kinetis-port-pins = < 5 3 >;
640	};
641	FTM2_FLT1_PTD5: ftm2_flt1_ptd5 {
642		nxp,kinetis-port-pins = < 5 4 >;
643	};
644	PWT_IN2_PTD5: pwt_in2_ptd5 {
645		nxp,kinetis-port-pins = < 5 5 >;
646	};
647	TRGMUX_IN7_PTD5: trgmux_in7_ptd5 {
648		nxp,kinetis-port-pins = < 5 6 >;
649	};
650	PTD6: GPIOD_PTD6: gpiod_ptd6 {
651		nxp,kinetis-port-pins = < 6 1 >;
652	};
653	LPUART2_RX_PTD6: lpuart2_rx_ptd6 {
654		nxp,kinetis-port-pins = < 6 2 >;
655	};
656	FTM2_FLT2_PTD6: ftm2_flt2_ptd6 {
657		nxp,kinetis-port-pins = < 6 4 >;
658	};
659	PTD7: GPIOD_PTD7: gpiod_ptd7 {
660		nxp,kinetis-port-pins = < 7 1 >;
661	};
662	LPUART2_TX_PTD7: lpuart2_tx_ptd7 {
663		nxp,kinetis-port-pins = < 7 2 >;
664	};
665	FTM2_FLT3_PTD7: ftm2_flt3_ptd7 {
666		nxp,kinetis-port-pins = < 7 4 >;
667	};
668	ACMP2_IN1_PTD15: acmp2_in1_ptd15 {
669		nxp,kinetis-port-pins = < 15 0 >;
670	};
671	PTD15: GPIOD_PTD15: gpiod_ptd15 {
672		nxp,kinetis-port-pins = < 15 1 >;
673	};
674	FTM0_CH0_PTD15: ftm0_ch0_ptd15 {
675		nxp,kinetis-port-pins = < 15 2 >;
676	};
677	ACMP2_IN0_PTD16: acmp2_in0_ptd16 {
678		nxp,kinetis-port-pins = < 16 0 >;
679	};
680	PTD16: GPIOD_PTD16: gpiod_ptd16 {
681		nxp,kinetis-port-pins = < 16 1 >;
682	};
683	FTM0_CH1_PTD16: ftm0_ch1_ptd16 {
684		nxp,kinetis-port-pins = < 16 2 >;
685	};
686};
687
688&porte {
689	ADC2_SE7_PTE0: adc2_se7_pte0 {
690		nxp,kinetis-port-pins = < 0 0 >;
691	};
692	PTE0: GPIOE_PTE0: gpioe_pte0 {
693		nxp,kinetis-port-pins = < 0 1 >;
694	};
695	LPSPI0_SCK_PTE0: lpspi0_sck_pte0 {
696		nxp,kinetis-port-pins = < 0 2 >;
697	};
698	TCLK1_PTE0: tclk1_pte0 {
699		nxp,kinetis-port-pins = < 0 3 >;
700	};
701	LPI2C1_SDA_PTE0: lpi2c1_sda_pte0 {
702		nxp,kinetis-port-pins = < 0 4 >;
703	};
704	FTM1_FLT2_PTE0: ftm1_flt2_pte0 {
705		nxp,kinetis-port-pins = < 0 6 >;
706	};
707	ADC2_SE6_PTE1: adc2_se6_pte1 {
708		nxp,kinetis-port-pins = < 1 0 >;
709	};
710	PTE1: GPIOE_PTE1: gpioe_pte1 {
711		nxp,kinetis-port-pins = < 1 1 >;
712	};
713	LPSPI0_SIN_PTE1: lpspi0_sin_pte1 {
714		nxp,kinetis-port-pins = < 1 2 >;
715	};
716	LPI2C0_HREQ_PTE1: lpi2c0_hreq_pte1 {
717		nxp,kinetis-port-pins = < 1 3 >;
718	};
719	LPI2C1_SCL_PTE1: lpi2c1_scl_pte1 {
720		nxp,kinetis-port-pins = < 1 4 >;
721	};
722	FTM1_FLT1_PTE1: ftm1_flt1_pte1 {
723		nxp,kinetis-port-pins = < 1 6 >;
724	};
725	ADC1_SE10_PTE2: adc1_se10_pte2 {
726		nxp,kinetis-port-pins = < 2 0 >;
727	};
728	PTE2: GPIOE_PTE2: gpioe_pte2 {
729		nxp,kinetis-port-pins = < 2 1 >;
730	};
731	LPSPI0_SOUT_PTE2: lpspi0_sout_pte2 {
732		nxp,kinetis-port-pins = < 2 2 >;
733	};
734	LPTMR0_ALT3_PTE2: lptmr0_alt3_pte2 {
735		nxp,kinetis-port-pins = < 2 3 >;
736	};
737	FTM3_CH6_PTE2: ftm3_ch6_pte2 {
738		nxp,kinetis-port-pins = < 2 4 >;
739	};
740	PWT_IN3_PTE2: pwt_in3_pte2 {
741		nxp,kinetis-port-pins = < 2 5 >;
742	};
743	LPUART1_CTS_PTE2: lpuart1_cts_pte2 {
744		nxp,kinetis-port-pins = < 2 6 >;
745	};
746	PTE3: GPIOE_PTE3: gpioe_pte3 {
747		nxp,kinetis-port-pins = < 3 1 >;
748	};
749	FTM0_FLT0_PTE3: ftm0_flt0_pte3 {
750		nxp,kinetis-port-pins = < 3 2 >;
751	};
752	LPUART2_RTS_PTE3: lpuart2_rts_pte3 {
753		nxp,kinetis-port-pins = < 3 3 >;
754	};
755	FTM2_FLT0_PTE3: ftm2_flt0_pte3 {
756		nxp,kinetis-port-pins = < 3 4 >;
757	};
758	TRGMUX_IN6_PTE3: trgmux_in6_pte3 {
759		nxp,kinetis-port-pins = < 3 6 >;
760	};
761	ACMP2_OUT_PTE3: acmp2_out_pte3 {
762		nxp,kinetis-port-pins = < 3 7 >;
763	};
764	PTE4: GPIOE_PTE4: gpioe_pte4 {
765		nxp,kinetis-port-pins = < 4 1 >;
766	};
767	BUSOUT_PTE4: busout_pte4 {
768		nxp,kinetis-port-pins = < 4 2 >;
769	};
770	FTM2_QD_PHB_PTE4: ftm2_qd_phb_pte4 {
771		nxp,kinetis-port-pins = < 4 3 >;
772	};
773	FTM2_CH2_PTE4: ftm2_ch2_pte4 {
774		nxp,kinetis-port-pins = < 4 4 >;
775	};
776	CAN0_RX_PTE4: can0_rx_pte4 {
777		nxp,kinetis-port-pins = < 4 5 >;
778	};
779	FXIO_D6_PTE4: fxio_d6_pte4 {
780		nxp,kinetis-port-pins = < 4 6 >;
781	};
782	EWM_OUT_b_PTE4: ewm_out_b_pte4 {
783		nxp,kinetis-port-pins = < 4 7 >;
784	};
785	PTE5: GPIOE_PTE5: gpioe_pte5 {
786		nxp,kinetis-port-pins = < 5 1 >;
787	};
788	TCLK2_PTE5: tclk2_pte5 {
789		nxp,kinetis-port-pins = < 5 2 >;
790	};
791	FTM2_QD_PHA_PTE5: ftm2_qd_pha_pte5 {
792		nxp,kinetis-port-pins = < 5 3 >;
793	};
794	FTM2_CH3_PTE5: ftm2_ch3_pte5 {
795		nxp,kinetis-port-pins = < 5 4 >;
796	};
797	CAN0_TX_PTE5: can0_tx_pte5 {
798		nxp,kinetis-port-pins = < 5 5 >;
799	};
800	FXIO_D7_PTE5: fxio_d7_pte5 {
801		nxp,kinetis-port-pins = < 5 6 >;
802	};
803	EWM_IN_PTE5: ewm_in_pte5 {
804		nxp,kinetis-port-pins = < 5 7 >;
805	};
806	ADC1_SE11_PTE6: ACMP0_IN6_PTE6: adc1_se11_pte6 {
807		nxp,kinetis-port-pins = < 6 0 >;
808	};
809	PTE6: GPIOE_PTE6: gpioe_pte6 {
810		nxp,kinetis-port-pins = < 6 1 >;
811	};
812	LPSPI0_PCS2_PTE6: lpspi0_pcs2_pte6 {
813		nxp,kinetis-port-pins = < 6 2 >;
814	};
815	FTM3_CH7_PTE6: ftm3_ch7_pte6 {
816		nxp,kinetis-port-pins = < 6 4 >;
817	};
818	LPUART1_RTS_PTE6: lpuart1_rts_pte6 {
819		nxp,kinetis-port-pins = < 6 6 >;
820	};
821	ADC2_SE2_PTE7: ACMP2_IN6_PTE7: adc2_se2_pte7 {
822		nxp,kinetis-port-pins = < 7 0 >;
823	};
824	PTE7: GPIOE_PTE7: gpioe_pte7 {
825		nxp,kinetis-port-pins = < 7 1 >;
826	};
827	FTM0_CH7_PTE7: ftm0_ch7_pte7 {
828		nxp,kinetis-port-pins = < 7 2 >;
829	};
830	FTM3_FLT0_PTE7: ftm3_flt0_pte7 {
831		nxp,kinetis-port-pins = < 7 3 >;
832	};
833	ACMP0_IN3_PTE8: acmp0_in3_pte8 {
834		nxp,kinetis-port-pins = < 8 0 >;
835	};
836	PTE8: GPIOE_PTE8: gpioe_pte8 {
837		nxp,kinetis-port-pins = < 8 1 >;
838	};
839	FTM0_CH6_PTE8: ftm0_ch6_pte8 {
840		nxp,kinetis-port-pins = < 8 2 >;
841	};
842	ACMP2_IN2_PTE9: DAC0_OUT_PTE9: acmp2_in2_pte9 {
843		nxp,kinetis-port-pins = < 9 0 >;
844	};
845	PTE9: GPIOE_PTE9: gpioe_pte9 {
846		nxp,kinetis-port-pins = < 9 1 >;
847	};
848	FTM0_CH7_PTE9: ftm0_ch7_pte9 {
849		nxp,kinetis-port-pins = < 9 2 >;
850	};
851	LPUART2_CTS_PTE9: lpuart2_cts_pte9 {
852		nxp,kinetis-port-pins = < 9 3 >;
853	};
854	ADC2_SE12_PTE10: adc2_se12_pte10 {
855		nxp,kinetis-port-pins = < 10 0 >;
856	};
857	PTE10: GPIOE_PTE10: gpioe_pte10 {
858		nxp,kinetis-port-pins = < 10 1 >;
859	};
860	CLKOUT_PTE10: clkout_pte10 {
861		nxp,kinetis-port-pins = < 10 2 >;
862	};
863	FTM2_CH4_PTE10: ftm2_ch4_pte10 {
864		nxp,kinetis-port-pins = < 10 4 >;
865	};
866	FXIO_D4_PTE10: fxio_d4_pte10 {
867		nxp,kinetis-port-pins = < 10 6 >;
868	};
869	TRGMUX_OUT4_PTE10: trgmux_out4_pte10 {
870		nxp,kinetis-port-pins = < 10 7 >;
871	};
872	ADC2_SE13_PTE11: adc2_se13_pte11 {
873		nxp,kinetis-port-pins = < 11 0 >;
874	};
875	PTE11: GPIOE_PTE11: gpioe_pte11 {
876		nxp,kinetis-port-pins = < 11 1 >;
877	};
878	PWT_IN1_PTE11: pwt_in1_pte11 {
879		nxp,kinetis-port-pins = < 11 2 >;
880	};
881	LPTMR0_ALT1_PTE11: lptmr0_alt1_pte11 {
882		nxp,kinetis-port-pins = < 11 3 >;
883	};
884	FTM2_CH5_PTE11: ftm2_ch5_pte11 {
885		nxp,kinetis-port-pins = < 11 4 >;
886	};
887	FXIO_D5_PTE11: fxio_d5_pte11 {
888		nxp,kinetis-port-pins = < 11 6 >;
889	};
890	TRGMUX_OUT5_PTE11: trgmux_out5_pte11 {
891		nxp,kinetis-port-pins = < 11 7 >;
892	};
893};
894
895