1/*
2 * NOTE: Autogenerated file by kinetis_signal2dts.py
3 *       for MK82FN256VLL15/signal_configuration.xml
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8/*
9 * Pin nodes are of the form:
10 *
11 *	<SIGNAL[0..n]>: <signal[0]> {
12 *		nxp,kinetis-port-pins = < PIN PCR[MUX] >;
13 *	};
14 */
15
16&porta {
17	TSI0_CH1_PTA0: tsi0_ch1_pta0 {
18		nxp,kinetis-port-pins = < 0 0 >;
19	};
20	PTA0: GPIOA_PTA0: gpioa_pta0 {
21		nxp,kinetis-port-pins = < 0 1 >;
22	};
23	LPUART0_CTS_b_PTA0: lpuart0_cts_b_pta0 {
24		nxp,kinetis-port-pins = < 0 2 >;
25	};
26	FTM0_CH5_PTA0: ftm0_ch5_pta0 {
27		nxp,kinetis-port-pins = < 0 3 >;
28	};
29	FXIO0_D10_PTA0: fxio0_d10_pta0 {
30		nxp,kinetis-port-pins = < 0 5 >;
31	};
32	EMVSIM0_CLK_PTA0: emvsim0_clk_pta0 {
33		nxp,kinetis-port-pins = < 0 6 >;
34	};
35	JTAG_TCLK_PTA0: jtag_tclk_pta0 {
36		nxp,kinetis-port-pins = < 0 7 >;
37	};
38	TSI0_CH2_PTA1: tsi0_ch2_pta1 {
39		nxp,kinetis-port-pins = < 1 0 >;
40	};
41	PTA1: GPIOA_PTA1: gpioa_pta1 {
42		nxp,kinetis-port-pins = < 1 1 >;
43	};
44	LPUART0_RX_PTA1: lpuart0_rx_pta1 {
45		nxp,kinetis-port-pins = < 1 2 >;
46	};
47	FTM0_CH6_PTA1: ftm0_ch6_pta1 {
48		nxp,kinetis-port-pins = < 1 3 >;
49	};
50	I2C3_SDA_PTA1: i2c3_sda_pta1 {
51		nxp,kinetis-port-pins = < 1 4 >;
52	};
53	FXIO0_D11_PTA1: fxio0_d11_pta1 {
54		nxp,kinetis-port-pins = < 1 5 >;
55	};
56	EMVSIM0_IO_PTA1: emvsim0_io_pta1 {
57		nxp,kinetis-port-pins = < 1 6 >;
58	};
59	JTAG_TDI_PTA1: jtag_tdi_pta1 {
60		nxp,kinetis-port-pins = < 1 7 >;
61	};
62	TSI0_CH3_PTA2: tsi0_ch3_pta2 {
63		nxp,kinetis-port-pins = < 2 0 >;
64	};
65	PTA2: GPIOA_PTA2: gpioa_pta2 {
66		nxp,kinetis-port-pins = < 2 1 >;
67	};
68	LPUART0_TX_PTA2: lpuart0_tx_pta2 {
69		nxp,kinetis-port-pins = < 2 2 >;
70	};
71	FTM0_CH7_PTA2: ftm0_ch7_pta2 {
72		nxp,kinetis-port-pins = < 2 3 >;
73	};
74	I2C3_SCL_PTA2: i2c3_scl_pta2 {
75		nxp,kinetis-port-pins = < 2 4 >;
76	};
77	FXIO0_D12_PTA2: fxio0_d12_pta2 {
78		nxp,kinetis-port-pins = < 2 5 >;
79	};
80	EMVSIM0_PD_PTA2: emvsim0_pd_pta2 {
81		nxp,kinetis-port-pins = < 2 6 >;
82	};
83	JTAG_TDO_PTA2: TRACE_SWO_PTA2: jtag_tdo_pta2 {
84		nxp,kinetis-port-pins = < 2 7 >;
85	};
86	TSI0_CH4_PTA3: tsi0_ch4_pta3 {
87		nxp,kinetis-port-pins = < 3 0 >;
88	};
89	PTA3: GPIOA_PTA3: gpioa_pta3 {
90		nxp,kinetis-port-pins = < 3 1 >;
91	};
92	LPUART0_RTS_b_PTA3: lpuart0_rts_b_pta3 {
93		nxp,kinetis-port-pins = < 3 2 >;
94	};
95	FTM0_CH0_PTA3: ftm0_ch0_pta3 {
96		nxp,kinetis-port-pins = < 3 3 >;
97	};
98	FXIO0_D13_PTA3: fxio0_d13_pta3 {
99		nxp,kinetis-port-pins = < 3 5 >;
100	};
101	EMVSIM0_RST_PTA3: emvsim0_rst_pta3 {
102		nxp,kinetis-port-pins = < 3 6 >;
103	};
104	JTAG_TMS_PTA3: jtag_tms_pta3 {
105		nxp,kinetis-port-pins = < 3 7 >;
106	};
107	TSI0_CH5_PTA4: tsi0_ch5_pta4 {
108		nxp,kinetis-port-pins = < 4 0 >;
109	};
110	PTA4: GPIOA_PTA4: LLWU_P3_PTA4: gpioa_pta4 {
111		nxp,kinetis-port-pins = < 4 1 >;
112	};
113	FTM0_CH1_PTA4: ftm0_ch1_pta4 {
114		nxp,kinetis-port-pins = < 4 3 >;
115	};
116	FXIO0_D14_PTA4: fxio0_d14_pta4 {
117		nxp,kinetis-port-pins = < 4 5 >;
118	};
119	EMVSIM0_VCCEN_PTA4: emvsim0_vccen_pta4 {
120		nxp,kinetis-port-pins = < 4 6 >;
121	};
122	NMI_b_PTA4: nmi_b_pta4 {
123		nxp,kinetis-port-pins = < 4 7 >;
124	};
125	PTA5: GPIOA_PTA5: gpioa_pta5 {
126		nxp,kinetis-port-pins = < 5 1 >;
127	};
128	USB0_CLKIN_PTA5: usb0_clkin_pta5 {
129		nxp,kinetis-port-pins = < 5 2 >;
130	};
131	FTM0_CH2_PTA5: ftm0_ch2_pta5 {
132		nxp,kinetis-port-pins = < 5 3 >;
133	};
134	FXIO0_D15_PTA5: fxio0_d15_pta5 {
135		nxp,kinetis-port-pins = < 5 5 >;
136	};
137	I2S0_TX_BCLK_PTA5: i2s0_tx_bclk_pta5 {
138		nxp,kinetis-port-pins = < 5 6 >;
139	};
140	JTAG_TRST_b_PTA5: jtag_trst_b_pta5 {
141		nxp,kinetis-port-pins = < 5 7 >;
142	};
143	PTA12: GPIOA_PTA12: gpioa_pta12 {
144		nxp,kinetis-port-pins = < 12 1 >;
145	};
146	FTM1_CH0_PTA12: ftm1_ch0_pta12 {
147		nxp,kinetis-port-pins = < 12 3 >;
148	};
149	TRACE_CLKOUT_PTA12: trace_clkout_pta12 {
150		nxp,kinetis-port-pins = < 12 4 >;
151	};
152	FXIO0_D18_PTA12: fxio0_d18_pta12 {
153		nxp,kinetis-port-pins = < 12 5 >;
154	};
155	I2S0_TXD0_PTA12: i2s0_txd0_pta12 {
156		nxp,kinetis-port-pins = < 12 6 >;
157	};
158	FTM1_QD_PHA_PTA12: TPM1_CH0_PTA12: ftm1_qd_pha_pta12 {
159		nxp,kinetis-port-pins = < 12 7 >;
160	};
161	PTA13: GPIOA_PTA13: LLWU_P4_PTA13: gpioa_pta13 {
162		nxp,kinetis-port-pins = < 13 1 >;
163	};
164	FTM1_CH1_PTA13: ftm1_ch1_pta13 {
165		nxp,kinetis-port-pins = < 13 3 >;
166	};
167	TRACE_D3_PTA13: trace_d3_pta13 {
168		nxp,kinetis-port-pins = < 13 4 >;
169	};
170	FXIO0_D19_PTA13: fxio0_d19_pta13 {
171		nxp,kinetis-port-pins = < 13 5 >;
172	};
173	I2S0_TX_FS_PTA13: i2s0_tx_fs_pta13 {
174		nxp,kinetis-port-pins = < 13 6 >;
175	};
176	FTM1_QD_PHB_PTA13: TPM1_CH1_PTA13: ftm1_qd_phb_pta13 {
177		nxp,kinetis-port-pins = < 13 7 >;
178	};
179	PTA14: GPIOA_PTA14: gpioa_pta14 {
180		nxp,kinetis-port-pins = < 14 1 >;
181	};
182	SPI0_PCS0_PTA14: spi0_pcs0_pta14 {
183		nxp,kinetis-port-pins = < 14 2 >;
184	};
185	LPUART0_TX_PTA14: lpuart0_tx_pta14 {
186		nxp,kinetis-port-pins = < 14 3 >;
187	};
188	TRACE_D2_PTA14: trace_d2_pta14 {
189		nxp,kinetis-port-pins = < 14 4 >;
190	};
191	FXIO0_D20_PTA14: fxio0_d20_pta14 {
192		nxp,kinetis-port-pins = < 14 5 >;
193	};
194	I2S0_RX_BCLK_PTA14: i2s0_rx_bclk_pta14 {
195		nxp,kinetis-port-pins = < 14 6 >;
196	};
197	I2S0_TXD1_PTA14: i2s0_txd1_pta14 {
198		nxp,kinetis-port-pins = < 14 7 >;
199	};
200	PTA15: GPIOA_PTA15: gpioa_pta15 {
201		nxp,kinetis-port-pins = < 15 1 >;
202	};
203	SPI0_SCK_PTA15: spi0_sck_pta15 {
204		nxp,kinetis-port-pins = < 15 2 >;
205	};
206	LPUART0_RX_PTA15: lpuart0_rx_pta15 {
207		nxp,kinetis-port-pins = < 15 3 >;
208	};
209	TRACE_D1_PTA15: trace_d1_pta15 {
210		nxp,kinetis-port-pins = < 15 4 >;
211	};
212	FXIO0_D21_PTA15: fxio0_d21_pta15 {
213		nxp,kinetis-port-pins = < 15 5 >;
214	};
215	I2S0_RXD0_PTA15: i2s0_rxd0_pta15 {
216		nxp,kinetis-port-pins = < 15 6 >;
217	};
218	PTA16: GPIOA_PTA16: gpioa_pta16 {
219		nxp,kinetis-port-pins = < 16 1 >;
220	};
221	SPI0_SOUT_PTA16: spi0_sout_pta16 {
222		nxp,kinetis-port-pins = < 16 2 >;
223	};
224	LPUART0_CTS_b_PTA16: lpuart0_cts_b_pta16 {
225		nxp,kinetis-port-pins = < 16 3 >;
226	};
227	TRACE_D0_PTA16: trace_d0_pta16 {
228		nxp,kinetis-port-pins = < 16 4 >;
229	};
230	FXIO0_D22_PTA16: fxio0_d22_pta16 {
231		nxp,kinetis-port-pins = < 16 5 >;
232	};
233	I2S0_RX_FS_PTA16: i2s0_rx_fs_pta16 {
234		nxp,kinetis-port-pins = < 16 6 >;
235	};
236	I2S0_RXD1_PTA16: i2s0_rxd1_pta16 {
237		nxp,kinetis-port-pins = < 16 7 >;
238	};
239	PTA17: GPIOA_PTA17: gpioa_pta17 {
240		nxp,kinetis-port-pins = < 17 1 >;
241	};
242	SPI0_SIN_PTA17: spi0_sin_pta17 {
243		nxp,kinetis-port-pins = < 17 2 >;
244	};
245	LPUART0_RTS_b_PTA17: lpuart0_rts_b_pta17 {
246		nxp,kinetis-port-pins = < 17 3 >;
247	};
248	FXIO0_D23_PTA17: fxio0_d23_pta17 {
249		nxp,kinetis-port-pins = < 17 5 >;
250	};
251	I2S0_MCLK_PTA17: i2s0_mclk_pta17 {
252		nxp,kinetis-port-pins = < 17 6 >;
253	};
254	EXTAL0_PTA18: extal0_pta18 {
255		nxp,kinetis-port-pins = < 18 0 >;
256	};
257	PTA18: GPIOA_PTA18: gpioa_pta18 {
258		nxp,kinetis-port-pins = < 18 1 >;
259	};
260	FTM0_FLT2_PTA18: ftm0_flt2_pta18 {
261		nxp,kinetis-port-pins = < 18 3 >;
262	};
263	FTM_CLKIN0_PTA18: ftm_clkin0_pta18 {
264		nxp,kinetis-port-pins = < 18 4 >;
265	};
266	TPM_CLKIN0_PTA18: tpm_clkin0_pta18 {
267		nxp,kinetis-port-pins = < 18 7 >;
268	};
269	XTAL0_PTA19: xtal0_pta19 {
270		nxp,kinetis-port-pins = < 19 0 >;
271	};
272	PTA19: GPIOA_PTA19: gpioa_pta19 {
273		nxp,kinetis-port-pins = < 19 1 >;
274	};
275	FTM1_FLT0_PTA19: ftm1_flt0_pta19 {
276		nxp,kinetis-port-pins = < 19 3 >;
277	};
278	FTM_CLKIN1_PTA19: ftm_clkin1_pta19 {
279		nxp,kinetis-port-pins = < 19 4 >;
280	};
281	LPTMR0_ALT1_PTA19: LPTMR1_ALT1_PTA19: lptmr0_alt1_pta19 {
282		nxp,kinetis-port-pins = < 19 6 >;
283	};
284	TPM_CLKIN1_PTA19: tpm_clkin1_pta19 {
285		nxp,kinetis-port-pins = < 19 7 >;
286	};
287};
288
289&portb {
290	ADC0_SE8_PTB0: TSI0_CH0_PTB0: adc0_se8_ptb0 {
291		nxp,kinetis-port-pins = < 0 0 >;
292	};
293	PTB0: GPIOB_PTB0: LLWU_P5_PTB0: gpiob_ptb0 {
294		nxp,kinetis-port-pins = < 0 1 >;
295	};
296	I2C0_SCL_PTB0: i2c0_scl_ptb0 {
297		nxp,kinetis-port-pins = < 0 2 >;
298	};
299	FTM1_CH0_PTB0: ftm1_ch0_ptb0 {
300		nxp,kinetis-port-pins = < 0 3 >;
301	};
302	SDRAM_CAS_b_PTB0: sdram_cas_b_ptb0 {
303		nxp,kinetis-port-pins = < 0 5 >;
304	};
305	FTM1_QD_PHA_PTB0: TPM1_CH0_PTB0: ftm1_qd_pha_ptb0 {
306		nxp,kinetis-port-pins = < 0 6 >;
307	};
308	FXIO0_D0_PTB0: fxio0_d0_ptb0 {
309		nxp,kinetis-port-pins = < 0 7 >;
310	};
311	ADC0_SE9_PTB1: TSI0_CH6_PTB1: adc0_se9_ptb1 {
312		nxp,kinetis-port-pins = < 1 0 >;
313	};
314	PTB1: GPIOB_PTB1: gpiob_ptb1 {
315		nxp,kinetis-port-pins = < 1 1 >;
316	};
317	I2C0_SDA_PTB1: i2c0_sda_ptb1 {
318		nxp,kinetis-port-pins = < 1 2 >;
319	};
320	FTM1_CH1_PTB1: ftm1_ch1_ptb1 {
321		nxp,kinetis-port-pins = < 1 3 >;
322	};
323	SDRAM_RAS_b_PTB1: sdram_ras_b_ptb1 {
324		nxp,kinetis-port-pins = < 1 5 >;
325	};
326	FTM1_QD_PHB_PTB1: TPM1_CH1_PTB1: ftm1_qd_phb_ptb1 {
327		nxp,kinetis-port-pins = < 1 6 >;
328	};
329	FXIO0_D1_PTB1: fxio0_d1_ptb1 {
330		nxp,kinetis-port-pins = < 1 7 >;
331	};
332	ADC0_SE12_PTB2: TSI0_CH7_PTB2: adc0_se12_ptb2 {
333		nxp,kinetis-port-pins = < 2 0 >;
334	};
335	PTB2: GPIOB_PTB2: gpiob_ptb2 {
336		nxp,kinetis-port-pins = < 2 1 >;
337	};
338	I2C0_SCL_PTB2: i2c0_scl_ptb2 {
339		nxp,kinetis-port-pins = < 2 2 >;
340	};
341	LPUART0_RTS_b_PTB2: lpuart0_rts_b_ptb2 {
342		nxp,kinetis-port-pins = < 2 3 >;
343	};
344	SDRAM_WE_PTB2: sdram_we_ptb2 {
345		nxp,kinetis-port-pins = < 2 5 >;
346	};
347	FTM0_FLT3_PTB2: ftm0_flt3_ptb2 {
348		nxp,kinetis-port-pins = < 2 6 >;
349	};
350	FXIO0_D2_PTB2: fxio0_d2_ptb2 {
351		nxp,kinetis-port-pins = < 2 7 >;
352	};
353	ADC0_SE13_PTB3: TSI0_CH8_PTB3: adc0_se13_ptb3 {
354		nxp,kinetis-port-pins = < 3 0 >;
355	};
356	PTB3: GPIOB_PTB3: gpiob_ptb3 {
357		nxp,kinetis-port-pins = < 3 1 >;
358	};
359	I2C0_SDA_PTB3: i2c0_sda_ptb3 {
360		nxp,kinetis-port-pins = < 3 2 >;
361	};
362	LPUART0_CTS_b_PTB3: lpuart0_cts_b_ptb3 {
363		nxp,kinetis-port-pins = < 3 3 >;
364	};
365	SDRAM_CS0_b_PTB3: sdram_cs0_b_ptb3 {
366		nxp,kinetis-port-pins = < 3 5 >;
367	};
368	FTM0_FLT0_PTB3: ftm0_flt0_ptb3 {
369		nxp,kinetis-port-pins = < 3 6 >;
370	};
371	FXIO0_D3_PTB3: fxio0_d3_ptb3 {
372		nxp,kinetis-port-pins = < 3 7 >;
373	};
374	PTB9: GPIOB_PTB9: gpiob_ptb9 {
375		nxp,kinetis-port-pins = < 9 1 >;
376	};
377	SPI1_PCS1_PTB9: spi1_pcs1_ptb9 {
378		nxp,kinetis-port-pins = < 9 2 >;
379	};
380	LPUART3_CTS_b_PTB9: lpuart3_cts_b_ptb9 {
381		nxp,kinetis-port-pins = < 9 3 >;
382	};
383	SDRAM_D20_PTB9: sdram_d20_ptb9 {
384		nxp,kinetis-port-pins = < 9 5 >;
385	};
386	PTB10: GPIOB_PTB10: gpiob_ptb10 {
387		nxp,kinetis-port-pins = < 10 1 >;
388	};
389	SPI1_PCS0_PTB10: spi1_pcs0_ptb10 {
390		nxp,kinetis-port-pins = < 10 2 >;
391	};
392	LPUART3_RX_PTB10: lpuart3_rx_ptb10 {
393		nxp,kinetis-port-pins = < 10 3 >;
394	};
395	I2C2_SCL_PTB10: i2c2_scl_ptb10 {
396		nxp,kinetis-port-pins = < 10 4 >;
397	};
398	SDRAM_D19_PTB10: sdram_d19_ptb10 {
399		nxp,kinetis-port-pins = < 10 5 >;
400	};
401	FTM0_FLT1_PTB10: ftm0_flt1_ptb10 {
402		nxp,kinetis-port-pins = < 10 6 >;
403	};
404	FXIO0_D4_PTB10: fxio0_d4_ptb10 {
405		nxp,kinetis-port-pins = < 10 7 >;
406	};
407	PTB11: GPIOB_PTB11: gpiob_ptb11 {
408		nxp,kinetis-port-pins = < 11 1 >;
409	};
410	SPI1_SCK_PTB11: spi1_sck_ptb11 {
411		nxp,kinetis-port-pins = < 11 2 >;
412	};
413	LPUART3_TX_PTB11: lpuart3_tx_ptb11 {
414		nxp,kinetis-port-pins = < 11 3 >;
415	};
416	I2C2_SDA_PTB11: i2c2_sda_ptb11 {
417		nxp,kinetis-port-pins = < 11 4 >;
418	};
419	SDRAM_D18_PTB11: sdram_d18_ptb11 {
420		nxp,kinetis-port-pins = < 11 5 >;
421	};
422	FTM0_FLT2_PTB11: ftm0_flt2_ptb11 {
423		nxp,kinetis-port-pins = < 11 6 >;
424	};
425	FXIO0_D5_PTB11: fxio0_d5_ptb11 {
426		nxp,kinetis-port-pins = < 11 7 >;
427	};
428	TSI0_CH9_PTB16: tsi0_ch9_ptb16 {
429		nxp,kinetis-port-pins = < 16 0 >;
430	};
431	PTB16: GPIOB_PTB16: gpiob_ptb16 {
432		nxp,kinetis-port-pins = < 16 1 >;
433	};
434	SPI1_SOUT_PTB16: spi1_sout_ptb16 {
435		nxp,kinetis-port-pins = < 16 2 >;
436	};
437	LPUART0_RX_PTB16: lpuart0_rx_ptb16 {
438		nxp,kinetis-port-pins = < 16 3 >;
439	};
440	FTM_CLKIN0_PTB16: ftm_clkin0_ptb16 {
441		nxp,kinetis-port-pins = < 16 4 >;
442	};
443	SDRAM_D17_PTB16: sdram_d17_ptb16 {
444		nxp,kinetis-port-pins = < 16 5 >;
445	};
446	EWM_IN_PTB16: ewm_in_ptb16 {
447		nxp,kinetis-port-pins = < 16 6 >;
448	};
449	TPM_CLKIN0_PTB16: tpm_clkin0_ptb16 {
450		nxp,kinetis-port-pins = < 16 7 >;
451	};
452	TSI0_CH10_PTB17: tsi0_ch10_ptb17 {
453		nxp,kinetis-port-pins = < 17 0 >;
454	};
455	PTB17: GPIOB_PTB17: gpiob_ptb17 {
456		nxp,kinetis-port-pins = < 17 1 >;
457	};
458	SPI1_SIN_PTB17: spi1_sin_ptb17 {
459		nxp,kinetis-port-pins = < 17 2 >;
460	};
461	LPUART0_TX_PTB17: lpuart0_tx_ptb17 {
462		nxp,kinetis-port-pins = < 17 3 >;
463	};
464	FTM_CLKIN1_PTB17: ftm_clkin1_ptb17 {
465		nxp,kinetis-port-pins = < 17 4 >;
466	};
467	SDRAM_D16_PTB17: sdram_d16_ptb17 {
468		nxp,kinetis-port-pins = < 17 5 >;
469	};
470	EWM_OUT_b_PTB17: ewm_out_b_ptb17 {
471		nxp,kinetis-port-pins = < 17 6 >;
472	};
473	TPM_CLKIN1_PTB17: tpm_clkin1_ptb17 {
474		nxp,kinetis-port-pins = < 17 7 >;
475	};
476	TSI0_CH11_PTB18: tsi0_ch11_ptb18 {
477		nxp,kinetis-port-pins = < 18 0 >;
478	};
479	PTB18: GPIOB_PTB18: gpiob_ptb18 {
480		nxp,kinetis-port-pins = < 18 1 >;
481	};
482	FTM2_CH0_PTB18: ftm2_ch0_ptb18 {
483		nxp,kinetis-port-pins = < 18 3 >;
484	};
485	I2S0_TX_BCLK_PTB18: i2s0_tx_bclk_ptb18 {
486		nxp,kinetis-port-pins = < 18 4 >;
487	};
488	SDRAM_A23_PTB18: sdram_a23_ptb18 {
489		nxp,kinetis-port-pins = < 18 5 >;
490	};
491	FTM2_QD_PHA_PTB18: TPM2_CH0_PTB18: ftm2_qd_pha_ptb18 {
492		nxp,kinetis-port-pins = < 18 6 >;
493	};
494	FXIO0_D6_PTB18: fxio0_d6_ptb18 {
495		nxp,kinetis-port-pins = < 18 7 >;
496	};
497	TSI0_CH12_PTB19: tsi0_ch12_ptb19 {
498		nxp,kinetis-port-pins = < 19 0 >;
499	};
500	PTB19: GPIOB_PTB19: gpiob_ptb19 {
501		nxp,kinetis-port-pins = < 19 1 >;
502	};
503	FTM2_CH1_PTB19: ftm2_ch1_ptb19 {
504		nxp,kinetis-port-pins = < 19 3 >;
505	};
506	I2S0_TX_FS_PTB19: i2s0_tx_fs_ptb19 {
507		nxp,kinetis-port-pins = < 19 4 >;
508	};
509	FTM2_QD_PHB_PTB19: TPM2_CH1_PTB19: ftm2_qd_phb_ptb19 {
510		nxp,kinetis-port-pins = < 19 6 >;
511	};
512	FXIO0_D7_PTB19: fxio0_d7_ptb19 {
513		nxp,kinetis-port-pins = < 19 7 >;
514	};
515	PTB20: GPIOB_PTB20: gpiob_ptb20 {
516		nxp,kinetis-port-pins = < 20 1 >;
517	};
518	SPI2_PCS0_PTB20: spi2_pcs0_ptb20 {
519		nxp,kinetis-port-pins = < 20 2 >;
520	};
521	SDRAM_D31_PTB20: sdram_d31_ptb20 {
522		nxp,kinetis-port-pins = < 20 5 >;
523	};
524	CMP0_OUT_PTB20: cmp0_out_ptb20 {
525		nxp,kinetis-port-pins = < 20 6 >;
526	};
527	FXIO0_D8_PTB20: fxio0_d8_ptb20 {
528		nxp,kinetis-port-pins = < 20 7 >;
529	};
530	PTB21: GPIOB_PTB21: gpiob_ptb21 {
531		nxp,kinetis-port-pins = < 21 1 >;
532	};
533	SPI2_SCK_PTB21: spi2_sck_ptb21 {
534		nxp,kinetis-port-pins = < 21 2 >;
535	};
536	SDRAM_D30_PTB21: sdram_d30_ptb21 {
537		nxp,kinetis-port-pins = < 21 5 >;
538	};
539	CMP1_OUT_PTB21: cmp1_out_ptb21 {
540		nxp,kinetis-port-pins = < 21 6 >;
541	};
542	FXIO0_D9_PTB21: fxio0_d9_ptb21 {
543		nxp,kinetis-port-pins = < 21 7 >;
544	};
545	PTB22: GPIOB_PTB22: gpiob_ptb22 {
546		nxp,kinetis-port-pins = < 22 1 >;
547	};
548	SPI2_SOUT_PTB22: spi2_sout_ptb22 {
549		nxp,kinetis-port-pins = < 22 2 >;
550	};
551	SDRAM_D29_PTB22: sdram_d29_ptb22 {
552		nxp,kinetis-port-pins = < 22 5 >;
553	};
554	FXIO0_D10_PTB22: fxio0_d10_ptb22 {
555		nxp,kinetis-port-pins = < 22 7 >;
556	};
557	PTB23: GPIOB_PTB23: gpiob_ptb23 {
558		nxp,kinetis-port-pins = < 23 1 >;
559	};
560	SPI2_SIN_PTB23: spi2_sin_ptb23 {
561		nxp,kinetis-port-pins = < 23 2 >;
562	};
563	SPI0_PCS5_PTB23: spi0_pcs5_ptb23 {
564		nxp,kinetis-port-pins = < 23 3 >;
565	};
566	SDRAM_D28_PTB23: sdram_d28_ptb23 {
567		nxp,kinetis-port-pins = < 23 5 >;
568	};
569	FXIO0_D11_PTB23: fxio0_d11_ptb23 {
570		nxp,kinetis-port-pins = < 23 7 >;
571	};
572};
573
574&portc {
575	ADC0_SE14_PTC0: TSI0_CH13_PTC0: adc0_se14_ptc0 {
576		nxp,kinetis-port-pins = < 0 0 >;
577	};
578	PTC0: GPIOC_PTC0: gpioc_ptc0 {
579		nxp,kinetis-port-pins = < 0 1 >;
580	};
581	SPI0_PCS4_PTC0: spi0_pcs4_ptc0 {
582		nxp,kinetis-port-pins = < 0 2 >;
583	};
584	PDB0_EXTRG_PTC0: pdb0_extrg_ptc0 {
585		nxp,kinetis-port-pins = < 0 3 >;
586	};
587	USB0_SOF_OUT_PTC0: usb0_sof_out_ptc0 {
588		nxp,kinetis-port-pins = < 0 4 >;
589	};
590	SDRAM_A22_PTC0: sdram_a22_ptc0 {
591		nxp,kinetis-port-pins = < 0 5 >;
592	};
593	I2S0_TXD1_PTC0: i2s0_txd1_ptc0 {
594		nxp,kinetis-port-pins = < 0 6 >;
595	};
596	FXIO0_D12_PTC0: fxio0_d12_ptc0 {
597		nxp,kinetis-port-pins = < 0 7 >;
598	};
599	ADC0_SE15_PTC1: TSI0_CH14_PTC1: adc0_se15_ptc1 {
600		nxp,kinetis-port-pins = < 1 0 >;
601	};
602	PTC1: GPIOC_PTC1: LLWU_P6_PTC1: gpioc_ptc1 {
603		nxp,kinetis-port-pins = < 1 1 >;
604	};
605	SPI0_PCS3_PTC1: spi0_pcs3_ptc1 {
606		nxp,kinetis-port-pins = < 1 2 >;
607	};
608	LPUART1_RTS_b_PTC1: lpuart1_rts_b_ptc1 {
609		nxp,kinetis-port-pins = < 1 3 >;
610	};
611	FTM0_CH0_PTC1: ftm0_ch0_ptc1 {
612		nxp,kinetis-port-pins = < 1 4 >;
613	};
614	SDRAM_A21_PTC1: sdram_a21_ptc1 {
615		nxp,kinetis-port-pins = < 1 5 >;
616	};
617	I2S0_TXD0_PTC1: i2s0_txd0_ptc1 {
618		nxp,kinetis-port-pins = < 1 6 >;
619	};
620	FXIO0_D13_PTC1: fxio0_d13_ptc1 {
621		nxp,kinetis-port-pins = < 1 7 >;
622	};
623	ADC0_SE4b_PTC2: CMP1_IN0_PTC2: TSI0_CH15_PTC2: adc0_se4b_ptc2 {
624		nxp,kinetis-port-pins = < 2 0 >;
625	};
626	PTC2: GPIOC_PTC2: gpioc_ptc2 {
627		nxp,kinetis-port-pins = < 2 1 >;
628	};
629	SPI0_PCS2_PTC2: spi0_pcs2_ptc2 {
630		nxp,kinetis-port-pins = < 2 2 >;
631	};
632	LPUART1_CTS_b_PTC2: lpuart1_cts_b_ptc2 {
633		nxp,kinetis-port-pins = < 2 3 >;
634	};
635	FTM0_CH1_PTC2: ftm0_ch1_ptc2 {
636		nxp,kinetis-port-pins = < 2 4 >;
637	};
638	SDRAM_A20_PTC2: sdram_a20_ptc2 {
639		nxp,kinetis-port-pins = < 2 5 >;
640	};
641	I2S0_TX_FS_PTC2: i2s0_tx_fs_ptc2 {
642		nxp,kinetis-port-pins = < 2 6 >;
643	};
644	CMP1_IN1_PTC3: cmp1_in1_ptc3 {
645		nxp,kinetis-port-pins = < 3 0 >;
646	};
647	PTC3: GPIOC_PTC3: LLWU_P7_PTC3: gpioc_ptc3 {
648		nxp,kinetis-port-pins = < 3 1 >;
649	};
650	SPI0_PCS1_PTC3: spi0_pcs1_ptc3 {
651		nxp,kinetis-port-pins = < 3 2 >;
652	};
653	LPUART1_RX_PTC3: lpuart1_rx_ptc3 {
654		nxp,kinetis-port-pins = < 3 3 >;
655	};
656	FTM0_CH2_PTC3: ftm0_ch2_ptc3 {
657		nxp,kinetis-port-pins = < 3 4 >;
658	};
659	CLKOUT_PTC3: clkout_ptc3 {
660		nxp,kinetis-port-pins = < 3 5 >;
661	};
662	I2S0_TX_BCLK_PTC3: i2s0_tx_bclk_ptc3 {
663		nxp,kinetis-port-pins = < 3 6 >;
664	};
665	PTC4: GPIOC_PTC4: LLWU_P8_PTC4: gpioc_ptc4 {
666		nxp,kinetis-port-pins = < 4 1 >;
667	};
668	SPI0_PCS0_PTC4: spi0_pcs0_ptc4 {
669		nxp,kinetis-port-pins = < 4 2 >;
670	};
671	LPUART1_TX_PTC4: lpuart1_tx_ptc4 {
672		nxp,kinetis-port-pins = < 4 3 >;
673	};
674	FTM0_CH3_PTC4: ftm0_ch3_ptc4 {
675		nxp,kinetis-port-pins = < 4 4 >;
676	};
677	SDRAM_A19_PTC4: sdram_a19_ptc4 {
678		nxp,kinetis-port-pins = < 4 5 >;
679	};
680	CMP1_OUT_PTC4: cmp1_out_ptc4 {
681		nxp,kinetis-port-pins = < 4 6 >;
682	};
683	PTC5: GPIOC_PTC5: LLWU_P9_PTC5: gpioc_ptc5 {
684		nxp,kinetis-port-pins = < 5 1 >;
685	};
686	SPI0_SCK_PTC5: spi0_sck_ptc5 {
687		nxp,kinetis-port-pins = < 5 2 >;
688	};
689	LPTMR0_ALT2_PTC5: LPTMR1_ALT2_PTC5: lptmr0_alt2_ptc5 {
690		nxp,kinetis-port-pins = < 5 3 >;
691	};
692	I2S0_RXD0_PTC5: i2s0_rxd0_ptc5 {
693		nxp,kinetis-port-pins = < 5 4 >;
694	};
695	SDRAM_A18_PTC5: sdram_a18_ptc5 {
696		nxp,kinetis-port-pins = < 5 5 >;
697	};
698	CMP0_OUT_PTC5: cmp0_out_ptc5 {
699		nxp,kinetis-port-pins = < 5 6 >;
700	};
701	FTM0_CH2_PTC5: ftm0_ch2_ptc5 {
702		nxp,kinetis-port-pins = < 5 7 >;
703	};
704	CMP0_IN0_PTC6: cmp0_in0_ptc6 {
705		nxp,kinetis-port-pins = < 6 0 >;
706	};
707	PTC6: GPIOC_PTC6: LLWU_P10_PTC6: gpioc_ptc6 {
708		nxp,kinetis-port-pins = < 6 1 >;
709	};
710	SPI0_SOUT_PTC6: spi0_sout_ptc6 {
711		nxp,kinetis-port-pins = < 6 2 >;
712	};
713	PDB0_EXTRG_PTC6: pdb0_extrg_ptc6 {
714		nxp,kinetis-port-pins = < 6 3 >;
715	};
716	I2S0_RX_BCLK_PTC6: i2s0_rx_bclk_ptc6 {
717		nxp,kinetis-port-pins = < 6 4 >;
718	};
719	SDRAM_A17_PTC6: sdram_a17_ptc6 {
720		nxp,kinetis-port-pins = < 6 5 >;
721	};
722	I2S0_MCLK_PTC6: i2s0_mclk_ptc6 {
723		nxp,kinetis-port-pins = < 6 6 >;
724	};
725	FXIO0_D14_PTC6: fxio0_d14_ptc6 {
726		nxp,kinetis-port-pins = < 6 7 >;
727	};
728	CMP0_IN1_PTC7: cmp0_in1_ptc7 {
729		nxp,kinetis-port-pins = < 7 0 >;
730	};
731	PTC7: GPIOC_PTC7: gpioc_ptc7 {
732		nxp,kinetis-port-pins = < 7 1 >;
733	};
734	SPI0_SIN_PTC7: spi0_sin_ptc7 {
735		nxp,kinetis-port-pins = < 7 2 >;
736	};
737	USB0_SOF_OUT_PTC7: usb0_sof_out_ptc7 {
738		nxp,kinetis-port-pins = < 7 3 >;
739	};
740	I2S0_RX_FS_PTC7: i2s0_rx_fs_ptc7 {
741		nxp,kinetis-port-pins = < 7 4 >;
742	};
743	SDRAM_A16_PTC7: sdram_a16_ptc7 {
744		nxp,kinetis-port-pins = < 7 5 >;
745	};
746	FXIO0_D15_PTC7: fxio0_d15_ptc7 {
747		nxp,kinetis-port-pins = < 7 7 >;
748	};
749	CMP0_IN2_PTC8: cmp0_in2_ptc8 {
750		nxp,kinetis-port-pins = < 8 0 >;
751	};
752	PTC8: GPIOC_PTC8: gpioc_ptc8 {
753		nxp,kinetis-port-pins = < 8 1 >;
754	};
755	FTM3_CH4_PTC8: ftm3_ch4_ptc8 {
756		nxp,kinetis-port-pins = < 8 3 >;
757	};
758	I2S0_MCLK_PTC8: i2s0_mclk_ptc8 {
759		nxp,kinetis-port-pins = < 8 4 >;
760	};
761	SDRAM_A15_PTC8: sdram_a15_ptc8 {
762		nxp,kinetis-port-pins = < 8 5 >;
763	};
764	FXIO0_D16_PTC8: fxio0_d16_ptc8 {
765		nxp,kinetis-port-pins = < 8 7 >;
766	};
767	CMP0_IN3_PTC9: cmp0_in3_ptc9 {
768		nxp,kinetis-port-pins = < 9 0 >;
769	};
770	PTC9: GPIOC_PTC9: gpioc_ptc9 {
771		nxp,kinetis-port-pins = < 9 1 >;
772	};
773	FTM3_CH5_PTC9: ftm3_ch5_ptc9 {
774		nxp,kinetis-port-pins = < 9 3 >;
775	};
776	I2S0_RX_BCLK_PTC9: i2s0_rx_bclk_ptc9 {
777		nxp,kinetis-port-pins = < 9 4 >;
778	};
779	SDRAM_A14_PTC9: sdram_a14_ptc9 {
780		nxp,kinetis-port-pins = < 9 5 >;
781	};
782	FTM2_FLT0_PTC9: ftm2_flt0_ptc9 {
783		nxp,kinetis-port-pins = < 9 6 >;
784	};
785	FXIO0_D17_PTC9: fxio0_d17_ptc9 {
786		nxp,kinetis-port-pins = < 9 7 >;
787	};
788	PTC10: GPIOC_PTC10: gpioc_ptc10 {
789		nxp,kinetis-port-pins = < 10 1 >;
790	};
791	I2C1_SCL_PTC10: i2c1_scl_ptc10 {
792		nxp,kinetis-port-pins = < 10 2 >;
793	};
794	FTM3_CH6_PTC10: ftm3_ch6_ptc10 {
795		nxp,kinetis-port-pins = < 10 3 >;
796	};
797	I2S0_RX_FS_PTC10: i2s0_rx_fs_ptc10 {
798		nxp,kinetis-port-pins = < 10 4 >;
799	};
800	SDRAM_A13_PTC10: sdram_a13_ptc10 {
801		nxp,kinetis-port-pins = < 10 5 >;
802	};
803	FXIO0_D18_PTC10: fxio0_d18_ptc10 {
804		nxp,kinetis-port-pins = < 10 7 >;
805	};
806	PTC11: GPIOC_PTC11: LLWU_P11_PTC11: gpioc_ptc11 {
807		nxp,kinetis-port-pins = < 11 1 >;
808	};
809	I2C1_SDA_PTC11: i2c1_sda_ptc11 {
810		nxp,kinetis-port-pins = < 11 2 >;
811	};
812	FTM3_CH7_PTC11: ftm3_ch7_ptc11 {
813		nxp,kinetis-port-pins = < 11 3 >;
814	};
815	I2S0_RXD1_PTC11: i2s0_rxd1_ptc11 {
816		nxp,kinetis-port-pins = < 11 4 >;
817	};
818	FXIO0_D19_PTC11: fxio0_d19_ptc11 {
819		nxp,kinetis-port-pins = < 11 7 >;
820	};
821	PTC12: GPIOC_PTC12: gpioc_ptc12 {
822		nxp,kinetis-port-pins = < 12 1 >;
823	};
824	LPUART4_RTS_b_PTC12: lpuart4_rts_b_ptc12 {
825		nxp,kinetis-port-pins = < 12 3 >;
826	};
827	FTM_CLKIN0_PTC12: ftm_clkin0_ptc12 {
828		nxp,kinetis-port-pins = < 12 4 >;
829	};
830	SDRAM_D27_PTC12: sdram_d27_ptc12 {
831		nxp,kinetis-port-pins = < 12 5 >;
832	};
833	FTM3_FLT0_PTC12: ftm3_flt0_ptc12 {
834		nxp,kinetis-port-pins = < 12 6 >;
835	};
836	TPM_CLKIN0_PTC12: tpm_clkin0_ptc12 {
837		nxp,kinetis-port-pins = < 12 7 >;
838	};
839	PTC13: GPIOC_PTC13: gpioc_ptc13 {
840		nxp,kinetis-port-pins = < 13 1 >;
841	};
842	LPUART4_CTS_b_PTC13: lpuart4_cts_b_ptc13 {
843		nxp,kinetis-port-pins = < 13 3 >;
844	};
845	FTM_CLKIN1_PTC13: ftm_clkin1_ptc13 {
846		nxp,kinetis-port-pins = < 13 4 >;
847	};
848	SDRAM_D26_PTC13: sdram_d26_ptc13 {
849		nxp,kinetis-port-pins = < 13 5 >;
850	};
851	TPM_CLKIN1_PTC13: tpm_clkin1_ptc13 {
852		nxp,kinetis-port-pins = < 13 7 >;
853	};
854	PTC14: GPIOC_PTC14: gpioc_ptc14 {
855		nxp,kinetis-port-pins = < 14 1 >;
856	};
857	LPUART4_RX_PTC14: lpuart4_rx_ptc14 {
858		nxp,kinetis-port-pins = < 14 3 >;
859	};
860	SDRAM_D25_PTC14: sdram_d25_ptc14 {
861		nxp,kinetis-port-pins = < 14 5 >;
862	};
863	FXIO0_D20_PTC14: fxio0_d20_ptc14 {
864		nxp,kinetis-port-pins = < 14 7 >;
865	};
866	PTC15: GPIOC_PTC15: gpioc_ptc15 {
867		nxp,kinetis-port-pins = < 15 1 >;
868	};
869	LPUART4_TX_PTC15: lpuart4_tx_ptc15 {
870		nxp,kinetis-port-pins = < 15 3 >;
871	};
872	SDRAM_D24_PTC15: sdram_d24_ptc15 {
873		nxp,kinetis-port-pins = < 15 5 >;
874	};
875	FXIO0_D21_PTC15: fxio0_d21_ptc15 {
876		nxp,kinetis-port-pins = < 15 7 >;
877	};
878	PTC17: GPIOC_PTC17: gpioc_ptc17 {
879		nxp,kinetis-port-pins = < 17 1 >;
880	};
881	LPUART3_TX_PTC17: lpuart3_tx_ptc17 {
882		nxp,kinetis-port-pins = < 17 3 >;
883	};
884	SDRAM_DQM3_PTC17: sdram_dqm3_ptc17 {
885		nxp,kinetis-port-pins = < 17 5 >;
886	};
887};
888
889&portd {
890	PTD0: GPIOD_PTD0: LLWU_P12_PTD0: gpiod_ptd0 {
891		nxp,kinetis-port-pins = < 0 1 >;
892	};
893	SPI0_PCS0_PTD0: spi0_pcs0_ptd0 {
894		nxp,kinetis-port-pins = < 0 2 >;
895	};
896	LPUART2_RTS_b_PTD0: lpuart2_rts_b_ptd0 {
897		nxp,kinetis-port-pins = < 0 3 >;
898	};
899	FTM3_CH0_PTD0: ftm3_ch0_ptd0 {
900		nxp,kinetis-port-pins = < 0 4 >;
901	};
902	FXIO0_D22_PTD0: fxio0_d22_ptd0 {
903		nxp,kinetis-port-pins = < 0 7 >;
904	};
905	ADC0_SE5b_PTD1: adc0_se5b_ptd1 {
906		nxp,kinetis-port-pins = < 1 0 >;
907	};
908	PTD1: GPIOD_PTD1: gpiod_ptd1 {
909		nxp,kinetis-port-pins = < 1 1 >;
910	};
911	SPI0_SCK_PTD1: spi0_sck_ptd1 {
912		nxp,kinetis-port-pins = < 1 2 >;
913	};
914	LPUART2_CTS_b_PTD1: lpuart2_cts_b_ptd1 {
915		nxp,kinetis-port-pins = < 1 3 >;
916	};
917	FTM3_CH1_PTD1: ftm3_ch1_ptd1 {
918		nxp,kinetis-port-pins = < 1 4 >;
919	};
920	FXIO0_D23_PTD1: fxio0_d23_ptd1 {
921		nxp,kinetis-port-pins = < 1 7 >;
922	};
923	PTD2: GPIOD_PTD2: LLWU_P13_PTD2: gpiod_ptd2 {
924		nxp,kinetis-port-pins = < 2 1 >;
925	};
926	SPI0_SOUT_PTD2: spi0_sout_ptd2 {
927		nxp,kinetis-port-pins = < 2 2 >;
928	};
929	LPUART2_RX_PTD2: lpuart2_rx_ptd2 {
930		nxp,kinetis-port-pins = < 2 3 >;
931	};
932	FTM3_CH2_PTD2: ftm3_ch2_ptd2 {
933		nxp,kinetis-port-pins = < 2 4 >;
934	};
935	SDRAM_A12_PTD2: sdram_a12_ptd2 {
936		nxp,kinetis-port-pins = < 2 5 >;
937	};
938	I2C0_SCL_PTD2: i2c0_scl_ptd2 {
939		nxp,kinetis-port-pins = < 2 7 >;
940	};
941	PTD3: GPIOD_PTD3: gpiod_ptd3 {
942		nxp,kinetis-port-pins = < 3 1 >;
943	};
944	SPI0_SIN_PTD3: spi0_sin_ptd3 {
945		nxp,kinetis-port-pins = < 3 2 >;
946	};
947	LPUART2_TX_PTD3: lpuart2_tx_ptd3 {
948		nxp,kinetis-port-pins = < 3 3 >;
949	};
950	FTM3_CH3_PTD3: ftm3_ch3_ptd3 {
951		nxp,kinetis-port-pins = < 3 4 >;
952	};
953	SDRAM_A11_PTD3: sdram_a11_ptd3 {
954		nxp,kinetis-port-pins = < 3 5 >;
955	};
956	I2C0_SDA_PTD3: i2c0_sda_ptd3 {
957		nxp,kinetis-port-pins = < 3 7 >;
958	};
959	PTD4: GPIOD_PTD4: LLWU_P14_PTD4: gpiod_ptd4 {
960		nxp,kinetis-port-pins = < 4 1 >;
961	};
962	SPI0_PCS1_PTD4: spi0_pcs1_ptd4 {
963		nxp,kinetis-port-pins = < 4 2 >;
964	};
965	LPUART0_RTS_b_PTD4: lpuart0_rts_b_ptd4 {
966		nxp,kinetis-port-pins = < 4 3 >;
967	};
968	FTM0_CH4_PTD4: ftm0_ch4_ptd4 {
969		nxp,kinetis-port-pins = < 4 4 >;
970	};
971	SDRAM_A10_PTD4: sdram_a10_ptd4 {
972		nxp,kinetis-port-pins = < 4 5 >;
973	};
974	EWM_IN_PTD4: ewm_in_ptd4 {
975		nxp,kinetis-port-pins = < 4 6 >;
976	};
977	SPI1_PCS0_PTD4: spi1_pcs0_ptd4 {
978		nxp,kinetis-port-pins = < 4 7 >;
979	};
980	ADC0_SE6b_PTD5: adc0_se6b_ptd5 {
981		nxp,kinetis-port-pins = < 5 0 >;
982	};
983	PTD5: GPIOD_PTD5: gpiod_ptd5 {
984		nxp,kinetis-port-pins = < 5 1 >;
985	};
986	SPI0_PCS2_PTD5: spi0_pcs2_ptd5 {
987		nxp,kinetis-port-pins = < 5 2 >;
988	};
989	LPUART0_CTS_b_PTD5: lpuart0_cts_b_ptd5 {
990		nxp,kinetis-port-pins = < 5 3 >;
991	};
992	FTM0_CH5_PTD5: ftm0_ch5_ptd5 {
993		nxp,kinetis-port-pins = < 5 4 >;
994	};
995	SDRAM_A9_PTD5: sdram_a9_ptd5 {
996		nxp,kinetis-port-pins = < 5 5 >;
997	};
998	EWM_OUT_b_PTD5: ewm_out_b_ptd5 {
999		nxp,kinetis-port-pins = < 5 6 >;
1000	};
1001	SPI1_SCK_PTD5: spi1_sck_ptd5 {
1002		nxp,kinetis-port-pins = < 5 7 >;
1003	};
1004	ADC0_SE7b_PTD6: adc0_se7b_ptd6 {
1005		nxp,kinetis-port-pins = < 6 0 >;
1006	};
1007	PTD6: GPIOD_PTD6: LLWU_P15_PTD6: gpiod_ptd6 {
1008		nxp,kinetis-port-pins = < 6 1 >;
1009	};
1010	SPI0_PCS3_PTD6: spi0_pcs3_ptd6 {
1011		nxp,kinetis-port-pins = < 6 2 >;
1012	};
1013	LPUART0_RX_PTD6: lpuart0_rx_ptd6 {
1014		nxp,kinetis-port-pins = < 6 3 >;
1015	};
1016	FTM0_CH6_PTD6: ftm0_ch6_ptd6 {
1017		nxp,kinetis-port-pins = < 6 4 >;
1018	};
1019	FTM0_FLT0_PTD6: ftm0_flt0_ptd6 {
1020		nxp,kinetis-port-pins = < 6 6 >;
1021	};
1022	SPI1_SOUT_PTD6: spi1_sout_ptd6 {
1023		nxp,kinetis-port-pins = < 6 7 >;
1024	};
1025	PTD7: GPIOD_PTD7: gpiod_ptd7 {
1026		nxp,kinetis-port-pins = < 7 1 >;
1027	};
1028	CMT_IRO_PTD7: cmt_iro_ptd7 {
1029		nxp,kinetis-port-pins = < 7 2 >;
1030	};
1031	LPUART0_TX_PTD7: lpuart0_tx_ptd7 {
1032		nxp,kinetis-port-pins = < 7 3 >;
1033	};
1034	FTM0_CH7_PTD7: ftm0_ch7_ptd7 {
1035		nxp,kinetis-port-pins = < 7 4 >;
1036	};
1037	SDRAM_CKE_PTD7: sdram_cke_ptd7 {
1038		nxp,kinetis-port-pins = < 7 5 >;
1039	};
1040	FTM0_FLT1_PTD7: ftm0_flt1_ptd7 {
1041		nxp,kinetis-port-pins = < 7 6 >;
1042	};
1043	SPI1_SIN_PTD7: spi1_sin_ptd7 {
1044		nxp,kinetis-port-pins = < 7 7 >;
1045	};
1046};
1047
1048&porte {
1049	PTE0: GPIOE_PTE0: gpioe_pte0 {
1050		nxp,kinetis-port-pins = < 0 1 >;
1051	};
1052	SPI1_PCS1_PTE0: spi1_pcs1_pte0 {
1053		nxp,kinetis-port-pins = < 0 2 >;
1054	};
1055	LPUART1_TX_PTE0: lpuart1_tx_pte0 {
1056		nxp,kinetis-port-pins = < 0 3 >;
1057	};
1058	SDHC0_D1_PTE0: sdhc0_d1_pte0 {
1059		nxp,kinetis-port-pins = < 0 4 >;
1060	};
1061	QSPI0A_DATA3_PTE0: qspi0a_data3_pte0 {
1062		nxp,kinetis-port-pins = < 0 5 >;
1063	};
1064	I2C1_SDA_PTE0: i2c1_sda_pte0 {
1065		nxp,kinetis-port-pins = < 0 6 >;
1066	};
1067	RTC_CLKOUT_PTE0: rtc_clkout_pte0 {
1068		nxp,kinetis-port-pins = < 0 7 >;
1069	};
1070	PTE1: GPIOE_PTE1: LLWU_P0_PTE1: gpioe_pte1 {
1071		nxp,kinetis-port-pins = < 1 1 >;
1072	};
1073	SPI1_SCK_PTE1: spi1_sck_pte1 {
1074		nxp,kinetis-port-pins = < 1 2 >;
1075	};
1076	LPUART1_RX_PTE1: lpuart1_rx_pte1 {
1077		nxp,kinetis-port-pins = < 1 3 >;
1078	};
1079	SDHC0_D0_PTE1: sdhc0_d0_pte1 {
1080		nxp,kinetis-port-pins = < 1 4 >;
1081	};
1082	QSPI0A_SCLK_PTE1: qspi0a_sclk_pte1 {
1083		nxp,kinetis-port-pins = < 1 5 >;
1084	};
1085	I2C1_SCL_PTE1: i2c1_scl_pte1 {
1086		nxp,kinetis-port-pins = < 1 6 >;
1087	};
1088	SPI1_SIN_PTE1: spi1_sin_pte1 {
1089		nxp,kinetis-port-pins = < 1 7 >;
1090	};
1091	PTE2: GPIOE_PTE2: LLWU_P1_PTE2: gpioe_pte2 {
1092		nxp,kinetis-port-pins = < 2 1 >;
1093	};
1094	SPI1_SOUT_PTE2: spi1_sout_pte2 {
1095		nxp,kinetis-port-pins = < 2 2 >;
1096	};
1097	LPUART1_CTS_b_PTE2: lpuart1_cts_b_pte2 {
1098		nxp,kinetis-port-pins = < 2 3 >;
1099	};
1100	SDHC0_DCLK_PTE2: sdhc0_dclk_pte2 {
1101		nxp,kinetis-port-pins = < 2 4 >;
1102	};
1103	QSPI0A_DATA0_PTE2: qspi0a_data0_pte2 {
1104		nxp,kinetis-port-pins = < 2 5 >;
1105	};
1106	SPI1_SCK_PTE2: spi1_sck_pte2 {
1107		nxp,kinetis-port-pins = < 2 7 >;
1108	};
1109	PTE3: GPIOE_PTE3: gpioe_pte3 {
1110		nxp,kinetis-port-pins = < 3 1 >;
1111	};
1112	SPI1_PCS2_PTE3: spi1_pcs2_pte3 {
1113		nxp,kinetis-port-pins = < 3 2 >;
1114	};
1115	LPUART1_RTS_b_PTE3: lpuart1_rts_b_pte3 {
1116		nxp,kinetis-port-pins = < 3 3 >;
1117	};
1118	SDHC0_CMD_PTE3: sdhc0_cmd_pte3 {
1119		nxp,kinetis-port-pins = < 3 4 >;
1120	};
1121	QSPI0A_DATA2_PTE3: qspi0a_data2_pte3 {
1122		nxp,kinetis-port-pins = < 3 5 >;
1123	};
1124	SPI1_SOUT_PTE3: spi1_sout_pte3 {
1125		nxp,kinetis-port-pins = < 3 7 >;
1126	};
1127	PTE4: GPIOE_PTE4: LLWU_P2_PTE4: gpioe_pte4 {
1128		nxp,kinetis-port-pins = < 4 1 >;
1129	};
1130	SPI1_SIN_PTE4: spi1_sin_pte4 {
1131		nxp,kinetis-port-pins = < 4 2 >;
1132	};
1133	LPUART3_TX_PTE4: lpuart3_tx_pte4 {
1134		nxp,kinetis-port-pins = < 4 3 >;
1135	};
1136	SDHC0_D3_PTE4: sdhc0_d3_pte4 {
1137		nxp,kinetis-port-pins = < 4 4 >;
1138	};
1139	QSPI0A_DATA1_PTE4: qspi0a_data1_pte4 {
1140		nxp,kinetis-port-pins = < 4 5 >;
1141	};
1142	PTE5: GPIOE_PTE5: gpioe_pte5 {
1143		nxp,kinetis-port-pins = < 5 1 >;
1144	};
1145	SPI1_PCS0_PTE5: spi1_pcs0_pte5 {
1146		nxp,kinetis-port-pins = < 5 2 >;
1147	};
1148	LPUART3_RX_PTE5: lpuart3_rx_pte5 {
1149		nxp,kinetis-port-pins = < 5 3 >;
1150	};
1151	SDHC0_D2_PTE5: sdhc0_d2_pte5 {
1152		nxp,kinetis-port-pins = < 5 4 >;
1153	};
1154	QSPI0A_SS0_B_PTE5: qspi0a_ss0_b_pte5 {
1155		nxp,kinetis-port-pins = < 5 5 >;
1156	};
1157	FTM3_CH0_PTE5: ftm3_ch0_pte5 {
1158		nxp,kinetis-port-pins = < 5 6 >;
1159	};
1160	USB0_SOF_OUT_PTE5: usb0_sof_out_pte5 {
1161		nxp,kinetis-port-pins = < 5 7 >;
1162	};
1163	PTE6: GPIOE_PTE6: LLWU_P16_PTE6: gpioe_pte6 {
1164		nxp,kinetis-port-pins = < 6 1 >;
1165	};
1166	SPI1_PCS3_PTE6: spi1_pcs3_pte6 {
1167		nxp,kinetis-port-pins = < 6 2 >;
1168	};
1169	LPUART3_CTS_b_PTE6: lpuart3_cts_b_pte6 {
1170		nxp,kinetis-port-pins = < 6 3 >;
1171	};
1172	I2S0_MCLK_PTE6: i2s0_mclk_pte6 {
1173		nxp,kinetis-port-pins = < 6 4 >;
1174	};
1175	QSPI0B_DATA3_PTE6: qspi0b_data3_pte6 {
1176		nxp,kinetis-port-pins = < 6 5 >;
1177	};
1178	FTM3_CH1_PTE6: ftm3_ch1_pte6 {
1179		nxp,kinetis-port-pins = < 6 6 >;
1180	};
1181	SDHC0_D4_PTE6: sdhc0_d4_pte6 {
1182		nxp,kinetis-port-pins = < 6 7 >;
1183	};
1184	PTE7: GPIOE_PTE7: gpioe_pte7 {
1185		nxp,kinetis-port-pins = < 7 1 >;
1186	};
1187	SPI2_SCK_PTE7: spi2_sck_pte7 {
1188		nxp,kinetis-port-pins = < 7 2 >;
1189	};
1190	LPUART3_RTS_b_PTE7: lpuart3_rts_b_pte7 {
1191		nxp,kinetis-port-pins = < 7 3 >;
1192	};
1193	I2S0_RXD0_PTE7: i2s0_rxd0_pte7 {
1194		nxp,kinetis-port-pins = < 7 4 >;
1195	};
1196	QSPI0B_SCLK_PTE7: qspi0b_sclk_pte7 {
1197		nxp,kinetis-port-pins = < 7 5 >;
1198	};
1199	FTM3_CH2_PTE7: ftm3_ch2_pte7 {
1200		nxp,kinetis-port-pins = < 7 6 >;
1201	};
1202	QSPI0A_SS1_B_PTE7: qspi0a_ss1_b_pte7 {
1203		nxp,kinetis-port-pins = < 7 7 >;
1204	};
1205	PTE8: GPIOE_PTE8: gpioe_pte8 {
1206		nxp,kinetis-port-pins = < 8 1 >;
1207	};
1208	I2S0_RXD1_PTE8: i2s0_rxd1_pte8 {
1209		nxp,kinetis-port-pins = < 8 2 >;
1210	};
1211	SPI2_SOUT_PTE8: spi2_sout_pte8 {
1212		nxp,kinetis-port-pins = < 8 3 >;
1213	};
1214	I2S0_RX_FS_PTE8: i2s0_rx_fs_pte8 {
1215		nxp,kinetis-port-pins = < 8 4 >;
1216	};
1217	QSPI0B_DATA0_PTE8: qspi0b_data0_pte8 {
1218		nxp,kinetis-port-pins = < 8 5 >;
1219	};
1220	FTM3_CH3_PTE8: ftm3_ch3_pte8 {
1221		nxp,kinetis-port-pins = < 8 6 >;
1222	};
1223	SDHC0_D5_PTE8: sdhc0_d5_pte8 {
1224		nxp,kinetis-port-pins = < 8 7 >;
1225	};
1226	PTE9: GPIOE_PTE9: LLWU_P17_PTE9: gpioe_pte9 {
1227		nxp,kinetis-port-pins = < 9 1 >;
1228	};
1229	I2S0_TXD1_PTE9: i2s0_txd1_pte9 {
1230		nxp,kinetis-port-pins = < 9 2 >;
1231	};
1232	SPI2_PCS1_PTE9: spi2_pcs1_pte9 {
1233		nxp,kinetis-port-pins = < 9 3 >;
1234	};
1235	I2S0_RX_BCLK_PTE9: i2s0_rx_bclk_pte9 {
1236		nxp,kinetis-port-pins = < 9 4 >;
1237	};
1238	QSPI0B_DATA2_PTE9: qspi0b_data2_pte9 {
1239		nxp,kinetis-port-pins = < 9 5 >;
1240	};
1241	FTM3_CH4_PTE9: ftm3_ch4_pte9 {
1242		nxp,kinetis-port-pins = < 9 6 >;
1243	};
1244	SDHC0_D6_PTE9: sdhc0_d6_pte9 {
1245		nxp,kinetis-port-pins = < 9 7 >;
1246	};
1247	PTE10: GPIOE_PTE10: LLWU_P18_PTE10: gpioe_pte10 {
1248		nxp,kinetis-port-pins = < 10 1 >;
1249	};
1250	I2C3_SDA_PTE10: i2c3_sda_pte10 {
1251		nxp,kinetis-port-pins = < 10 2 >;
1252	};
1253	SPI2_SIN_PTE10: spi2_sin_pte10 {
1254		nxp,kinetis-port-pins = < 10 3 >;
1255	};
1256	I2S0_TXD0_PTE10: i2s0_txd0_pte10 {
1257		nxp,kinetis-port-pins = < 10 4 >;
1258	};
1259	QSPI0B_DATA1_PTE10: qspi0b_data1_pte10 {
1260		nxp,kinetis-port-pins = < 10 5 >;
1261	};
1262	FTM3_CH5_PTE10: ftm3_ch5_pte10 {
1263		nxp,kinetis-port-pins = < 10 6 >;
1264	};
1265	SDHC0_D7_PTE10: sdhc0_d7_pte10 {
1266		nxp,kinetis-port-pins = < 10 7 >;
1267	};
1268	PTE11: GPIOE_PTE11: gpioe_pte11 {
1269		nxp,kinetis-port-pins = < 11 1 >;
1270	};
1271	I2C3_SCL_PTE11: i2c3_scl_pte11 {
1272		nxp,kinetis-port-pins = < 11 2 >;
1273	};
1274	SPI2_PCS0_PTE11: spi2_pcs0_pte11 {
1275		nxp,kinetis-port-pins = < 11 3 >;
1276	};
1277	I2S0_TX_FS_PTE11: i2s0_tx_fs_pte11 {
1278		nxp,kinetis-port-pins = < 11 4 >;
1279	};
1280	QSPI0B_SS0_B_PTE11: qspi0b_ss0_b_pte11 {
1281		nxp,kinetis-port-pins = < 11 5 >;
1282	};
1283	FTM3_CH6_PTE11: ftm3_ch6_pte11 {
1284		nxp,kinetis-port-pins = < 11 6 >;
1285	};
1286	QSPI0A_DQS_PTE11: qspi0a_dqs_pte11 {
1287		nxp,kinetis-port-pins = < 11 7 >;
1288	};
1289};
1290
1291