1/* 2 * NOTE: Autogenerated file by kinetis_signal2dts.py 3 * for MK66FN2M0VMD18/signal_configuration.xml 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8/* 9 * Pin nodes are of the form: 10 * 11 * <SIGNAL[0..n]>: <signal[0]> { 12 * nxp,kinetis-port-pins = < PIN PCR[MUX] >; 13 * }; 14 */ 15 16&porta { 17 TSI0_CH1_PTA0: tsi0_ch1_pta0 { 18 nxp,kinetis-port-pins = < 0 0 >; 19 }; 20 PTA0: GPIOA_PTA0: gpioa_pta0 { 21 nxp,kinetis-port-pins = < 0 1 >; 22 }; 23 UART0_CTS_b_PTA0: uart0_cts_b_pta0 { 24 nxp,kinetis-port-pins = < 0 2 >; 25 }; 26 FTM0_CH5_PTA0: ftm0_ch5_pta0 { 27 nxp,kinetis-port-pins = < 0 3 >; 28 }; 29 LPUART0_CTS_b_PTA0: lpuart0_cts_b_pta0 { 30 nxp,kinetis-port-pins = < 0 5 >; 31 }; 32 JTAG_TCLK_PTA0: jtag_tclk_pta0 { 33 nxp,kinetis-port-pins = < 0 7 >; 34 }; 35 TSI0_CH2_PTA1: tsi0_ch2_pta1 { 36 nxp,kinetis-port-pins = < 1 0 >; 37 }; 38 PTA1: GPIOA_PTA1: gpioa_pta1 { 39 nxp,kinetis-port-pins = < 1 1 >; 40 }; 41 UART0_RX_PTA1: uart0_rx_pta1 { 42 nxp,kinetis-port-pins = < 1 2 >; 43 }; 44 FTM0_CH6_PTA1: ftm0_ch6_pta1 { 45 nxp,kinetis-port-pins = < 1 3 >; 46 }; 47 I2C3_SDA_PTA1: i2c3_sda_pta1 { 48 nxp,kinetis-port-pins = < 1 4 >; 49 }; 50 LPUART0_RX_PTA1: lpuart0_rx_pta1 { 51 nxp,kinetis-port-pins = < 1 5 >; 52 }; 53 JTAG_TDI_PTA1: jtag_tdi_pta1 { 54 nxp,kinetis-port-pins = < 1 7 >; 55 }; 56 TSI0_CH3_PTA2: tsi0_ch3_pta2 { 57 nxp,kinetis-port-pins = < 2 0 >; 58 }; 59 PTA2: GPIOA_PTA2: gpioa_pta2 { 60 nxp,kinetis-port-pins = < 2 1 >; 61 }; 62 UART0_TX_PTA2: uart0_tx_pta2 { 63 nxp,kinetis-port-pins = < 2 2 >; 64 }; 65 FTM0_CH7_PTA2: ftm0_ch7_pta2 { 66 nxp,kinetis-port-pins = < 2 3 >; 67 }; 68 I2C3_SCL_PTA2: i2c3_scl_pta2 { 69 nxp,kinetis-port-pins = < 2 4 >; 70 }; 71 LPUART0_TX_PTA2: lpuart0_tx_pta2 { 72 nxp,kinetis-port-pins = < 2 5 >; 73 }; 74 JTAG_TDO_PTA2: TRACE_SWO_PTA2: jtag_tdo_pta2 { 75 nxp,kinetis-port-pins = < 2 7 >; 76 }; 77 TSI0_CH4_PTA3: tsi0_ch4_pta3 { 78 nxp,kinetis-port-pins = < 3 0 >; 79 }; 80 PTA3: GPIOA_PTA3: gpioa_pta3 { 81 nxp,kinetis-port-pins = < 3 1 >; 82 }; 83 UART0_RTS_b_PTA3: uart0_rts_b_pta3 { 84 nxp,kinetis-port-pins = < 3 2 >; 85 }; 86 FTM0_CH0_PTA3: ftm0_ch0_pta3 { 87 nxp,kinetis-port-pins = < 3 3 >; 88 }; 89 LPUART0_RTS_b_PTA3: lpuart0_rts_b_pta3 { 90 nxp,kinetis-port-pins = < 3 5 >; 91 }; 92 JTAG_TMS_PTA3: jtag_tms_pta3 { 93 nxp,kinetis-port-pins = < 3 7 >; 94 }; 95 TSI0_CH5_PTA4: tsi0_ch5_pta4 { 96 nxp,kinetis-port-pins = < 4 0 >; 97 }; 98 PTA4: GPIOA_PTA4: LLWU_P3_PTA4: gpioa_pta4 { 99 nxp,kinetis-port-pins = < 4 1 >; 100 }; 101 FTM0_CH1_PTA4: ftm0_ch1_pta4 { 102 nxp,kinetis-port-pins = < 4 3 >; 103 }; 104 NMI_b_PTA4: nmi_b_pta4 { 105 nxp,kinetis-port-pins = < 4 7 >; 106 }; 107 PTA5: GPIOA_PTA5: gpioa_pta5 { 108 nxp,kinetis-port-pins = < 5 1 >; 109 }; 110 USB0_CLKIN_PTA5: usb0_clkin_pta5 { 111 nxp,kinetis-port-pins = < 5 2 >; 112 }; 113 FTM0_CH2_PTA5: ftm0_ch2_pta5 { 114 nxp,kinetis-port-pins = < 5 3 >; 115 }; 116 RMII0_RXER_PTA5: MII0_RXER_PTA5: rmii0_rxer_pta5 { 117 nxp,kinetis-port-pins = < 5 4 >; 118 }; 119 CMP2_OUT_PTA5: cmp2_out_pta5 { 120 nxp,kinetis-port-pins = < 5 5 >; 121 }; 122 I2S0_TX_BCLK_PTA5: i2s0_tx_bclk_pta5 { 123 nxp,kinetis-port-pins = < 5 6 >; 124 }; 125 JTAG_TRST_b_PTA5: jtag_trst_b_pta5 { 126 nxp,kinetis-port-pins = < 5 7 >; 127 }; 128 PTA6: GPIOA_PTA6: gpioa_pta6 { 129 nxp,kinetis-port-pins = < 6 1 >; 130 }; 131 FTM0_CH3_PTA6: ftm0_ch3_pta6 { 132 nxp,kinetis-port-pins = < 6 3 >; 133 }; 134 CLKOUT_PTA6: clkout_pta6 { 135 nxp,kinetis-port-pins = < 6 5 >; 136 }; 137 TRACE_CLKOUT_PTA6: trace_clkout_pta6 { 138 nxp,kinetis-port-pins = < 6 7 >; 139 }; 140 ADC0_SE10_PTA7: adc0_se10_pta7 { 141 nxp,kinetis-port-pins = < 7 0 >; 142 }; 143 PTA7: GPIOA_PTA7: gpioa_pta7 { 144 nxp,kinetis-port-pins = < 7 1 >; 145 }; 146 FTM0_CH4_PTA7: ftm0_ch4_pta7 { 147 nxp,kinetis-port-pins = < 7 3 >; 148 }; 149 RMII0_MDIO_PTA7: MII0_MDIO_PTA7: rmii0_mdio_pta7 { 150 nxp,kinetis-port-pins = < 7 5 >; 151 }; 152 TRACE_D3_PTA7: trace_d3_pta7 { 153 nxp,kinetis-port-pins = < 7 7 >; 154 }; 155 ADC0_SE11_PTA8: adc0_se11_pta8 { 156 nxp,kinetis-port-pins = < 8 0 >; 157 }; 158 PTA8: GPIOA_PTA8: gpioa_pta8 { 159 nxp,kinetis-port-pins = < 8 1 >; 160 }; 161 FTM1_CH0_PTA8: ftm1_ch0_pta8 { 162 nxp,kinetis-port-pins = < 8 3 >; 163 }; 164 RMII0_MDC_PTA8: MII0_MDC_PTA8: rmii0_mdc_pta8 { 165 nxp,kinetis-port-pins = < 8 5 >; 166 }; 167 FTM1_QD_PHA_PTA8: TPM1_CH0_PTA8: ftm1_qd_pha_pta8 { 168 nxp,kinetis-port-pins = < 8 6 >; 169 }; 170 TRACE_D2_PTA8: trace_d2_pta8 { 171 nxp,kinetis-port-pins = < 8 7 >; 172 }; 173 PTA9: GPIOA_PTA9: gpioa_pta9 { 174 nxp,kinetis-port-pins = < 9 1 >; 175 }; 176 FTM1_CH1_PTA9: ftm1_ch1_pta9 { 177 nxp,kinetis-port-pins = < 9 3 >; 178 }; 179 MII0_RXD3_PTA9: mii0_rxd3_pta9 { 180 nxp,kinetis-port-pins = < 9 4 >; 181 }; 182 FTM1_QD_PHB_PTA9: TPM1_CH1_PTA9: ftm1_qd_phb_pta9 { 183 nxp,kinetis-port-pins = < 9 6 >; 184 }; 185 TRACE_D1_PTA9: trace_d1_pta9 { 186 nxp,kinetis-port-pins = < 9 7 >; 187 }; 188 PTA10: GPIOA_PTA10: LLWU_P22_PTA10: gpioa_pta10 { 189 nxp,kinetis-port-pins = < 10 1 >; 190 }; 191 FTM2_CH0_PTA10: ftm2_ch0_pta10 { 192 nxp,kinetis-port-pins = < 10 3 >; 193 }; 194 MII0_RXD2_PTA10: mii0_rxd2_pta10 { 195 nxp,kinetis-port-pins = < 10 4 >; 196 }; 197 FTM2_QD_PHA_PTA10: TPM2_CH0_PTA10: ftm2_qd_pha_pta10 { 198 nxp,kinetis-port-pins = < 10 6 >; 199 }; 200 TRACE_D0_PTA10: trace_d0_pta10 { 201 nxp,kinetis-port-pins = < 10 7 >; 202 }; 203 PTA11: GPIOA_PTA11: LLWU_P23_PTA11: gpioa_pta11 { 204 nxp,kinetis-port-pins = < 11 1 >; 205 }; 206 FTM2_CH1_PTA11: ftm2_ch1_pta11 { 207 nxp,kinetis-port-pins = < 11 3 >; 208 }; 209 MII0_RXCLK_PTA11: mii0_rxclk_pta11 { 210 nxp,kinetis-port-pins = < 11 4 >; 211 }; 212 I2C2_SDA_PTA11: i2c2_sda_pta11 { 213 nxp,kinetis-port-pins = < 11 5 >; 214 }; 215 FTM2_QD_PHB_PTA11: TPM2_CH1_PTA11: ftm2_qd_phb_pta11 { 216 nxp,kinetis-port-pins = < 11 6 >; 217 }; 218 CMP2_IN0_PTA12: cmp2_in0_pta12 { 219 nxp,kinetis-port-pins = < 12 0 >; 220 }; 221 PTA12: GPIOA_PTA12: gpioa_pta12 { 222 nxp,kinetis-port-pins = < 12 1 >; 223 }; 224 CAN0_TX_PTA12: can0_tx_pta12 { 225 nxp,kinetis-port-pins = < 12 2 >; 226 }; 227 FTM1_CH0_PTA12: ftm1_ch0_pta12 { 228 nxp,kinetis-port-pins = < 12 3 >; 229 }; 230 RMII0_RXD1_PTA12: MII0_RXD1_PTA12: rmii0_rxd1_pta12 { 231 nxp,kinetis-port-pins = < 12 4 >; 232 }; 233 I2C2_SCL_PTA12: i2c2_scl_pta12 { 234 nxp,kinetis-port-pins = < 12 5 >; 235 }; 236 I2S0_TXD0_PTA12: i2s0_txd0_pta12 { 237 nxp,kinetis-port-pins = < 12 6 >; 238 }; 239 FTM1_QD_PHA_PTA12: TPM1_CH0_PTA12: ftm1_qd_pha_pta12 { 240 nxp,kinetis-port-pins = < 12 7 >; 241 }; 242 CMP2_IN1_PTA13: cmp2_in1_pta13 { 243 nxp,kinetis-port-pins = < 13 0 >; 244 }; 245 PTA13: GPIOA_PTA13: LLWU_P4_PTA13: gpioa_pta13 { 246 nxp,kinetis-port-pins = < 13 1 >; 247 }; 248 CAN0_RX_PTA13: can0_rx_pta13 { 249 nxp,kinetis-port-pins = < 13 2 >; 250 }; 251 FTM1_CH1_PTA13: ftm1_ch1_pta13 { 252 nxp,kinetis-port-pins = < 13 3 >; 253 }; 254 RMII0_RXD0_PTA13: MII0_RXD0_PTA13: rmii0_rxd0_pta13 { 255 nxp,kinetis-port-pins = < 13 4 >; 256 }; 257 I2C2_SDA_PTA13: i2c2_sda_pta13 { 258 nxp,kinetis-port-pins = < 13 5 >; 259 }; 260 I2S0_TX_FS_PTA13: i2s0_tx_fs_pta13 { 261 nxp,kinetis-port-pins = < 13 6 >; 262 }; 263 FTM1_QD_PHB_PTA13: TPM1_CH1_PTA13: ftm1_qd_phb_pta13 { 264 nxp,kinetis-port-pins = < 13 7 >; 265 }; 266 PTA14: GPIOA_PTA14: gpioa_pta14 { 267 nxp,kinetis-port-pins = < 14 1 >; 268 }; 269 SPI0_PCS0_PTA14: spi0_pcs0_pta14 { 270 nxp,kinetis-port-pins = < 14 2 >; 271 }; 272 UART0_TX_PTA14: uart0_tx_pta14 { 273 nxp,kinetis-port-pins = < 14 3 >; 274 }; 275 RMII0_CRS_DV_PTA14: MII0_RXDV_PTA14: rmii0_crs_dv_pta14 { 276 nxp,kinetis-port-pins = < 14 4 >; 277 }; 278 I2C2_SCL_PTA14: i2c2_scl_pta14 { 279 nxp,kinetis-port-pins = < 14 5 >; 280 }; 281 I2S0_RX_BCLK_PTA14: i2s0_rx_bclk_pta14 { 282 nxp,kinetis-port-pins = < 14 6 >; 283 }; 284 I2S0_TXD1_PTA14: i2s0_txd1_pta14 { 285 nxp,kinetis-port-pins = < 14 7 >; 286 }; 287 CMP3_IN1_PTA15: cmp3_in1_pta15 { 288 nxp,kinetis-port-pins = < 15 0 >; 289 }; 290 PTA15: GPIOA_PTA15: gpioa_pta15 { 291 nxp,kinetis-port-pins = < 15 1 >; 292 }; 293 SPI0_SCK_PTA15: spi0_sck_pta15 { 294 nxp,kinetis-port-pins = < 15 2 >; 295 }; 296 UART0_RX_PTA15: uart0_rx_pta15 { 297 nxp,kinetis-port-pins = < 15 3 >; 298 }; 299 RMII0_TXEN_PTA15: MII0_TXEN_PTA15: rmii0_txen_pta15 { 300 nxp,kinetis-port-pins = < 15 4 >; 301 }; 302 I2S0_RXD0_PTA15: i2s0_rxd0_pta15 { 303 nxp,kinetis-port-pins = < 15 6 >; 304 }; 305 CMP3_IN2_PTA16: cmp3_in2_pta16 { 306 nxp,kinetis-port-pins = < 16 0 >; 307 }; 308 PTA16: GPIOA_PTA16: gpioa_pta16 { 309 nxp,kinetis-port-pins = < 16 1 >; 310 }; 311 SPI0_SOUT_PTA16: spi0_sout_pta16 { 312 nxp,kinetis-port-pins = < 16 2 >; 313 }; 314 UART0_CTS_b_PTA16: uart0_cts_b_pta16 { 315 nxp,kinetis-port-pins = < 16 3 >; 316 }; 317 RMII0_TXD0_PTA16: MII0_TXD0_PTA16: rmii0_txd0_pta16 { 318 nxp,kinetis-port-pins = < 16 4 >; 319 }; 320 I2S0_RX_FS_PTA16: i2s0_rx_fs_pta16 { 321 nxp,kinetis-port-pins = < 16 6 >; 322 }; 323 I2S0_RXD1_PTA16: i2s0_rxd1_pta16 { 324 nxp,kinetis-port-pins = < 16 7 >; 325 }; 326 ADC1_SE17_PTA17: adc1_se17_pta17 { 327 nxp,kinetis-port-pins = < 17 0 >; 328 }; 329 PTA17: GPIOA_PTA17: gpioa_pta17 { 330 nxp,kinetis-port-pins = < 17 1 >; 331 }; 332 SPI0_SIN_PTA17: spi0_sin_pta17 { 333 nxp,kinetis-port-pins = < 17 2 >; 334 }; 335 UART0_RTS_b_PTA17: uart0_rts_b_pta17 { 336 nxp,kinetis-port-pins = < 17 3 >; 337 }; 338 RMII0_TXD1_PTA17: MII0_TXD1_PTA17: rmii0_txd1_pta17 { 339 nxp,kinetis-port-pins = < 17 4 >; 340 }; 341 I2S0_MCLK_PTA17: i2s0_mclk_pta17 { 342 nxp,kinetis-port-pins = < 17 6 >; 343 }; 344 EXTAL0_PTA18: extal0_pta18 { 345 nxp,kinetis-port-pins = < 18 0 >; 346 }; 347 PTA18: GPIOA_PTA18: gpioa_pta18 { 348 nxp,kinetis-port-pins = < 18 1 >; 349 }; 350 FTM0_FLT2_PTA18: ftm0_flt2_pta18 { 351 nxp,kinetis-port-pins = < 18 3 >; 352 }; 353 FTM_CLKIN0_PTA18: ftm_clkin0_pta18 { 354 nxp,kinetis-port-pins = < 18 4 >; 355 }; 356 TPM_CLKIN0_PTA18: tpm_clkin0_pta18 { 357 nxp,kinetis-port-pins = < 18 7 >; 358 }; 359 XTAL0_PTA19: xtal0_pta19 { 360 nxp,kinetis-port-pins = < 19 0 >; 361 }; 362 PTA19: GPIOA_PTA19: gpioa_pta19 { 363 nxp,kinetis-port-pins = < 19 1 >; 364 }; 365 FTM1_FLT0_PTA19: ftm1_flt0_pta19 { 366 nxp,kinetis-port-pins = < 19 3 >; 367 }; 368 FTM_CLKIN1_PTA19: ftm_clkin1_pta19 { 369 nxp,kinetis-port-pins = < 19 4 >; 370 }; 371 LPTMR0_ALT1_PTA19: lptmr0_alt1_pta19 { 372 nxp,kinetis-port-pins = < 19 6 >; 373 }; 374 TPM_CLKIN1_PTA19: tpm_clkin1_pta19 { 375 nxp,kinetis-port-pins = < 19 7 >; 376 }; 377 CMP3_IN4_PTA24: cmp3_in4_pta24 { 378 nxp,kinetis-port-pins = < 24 0 >; 379 }; 380 PTA24: GPIOA_PTA24: gpioa_pta24 { 381 nxp,kinetis-port-pins = < 24 1 >; 382 }; 383 MII0_TXD2_PTA24: mii0_txd2_pta24 { 384 nxp,kinetis-port-pins = < 24 4 >; 385 }; 386 CMP3_IN5_PTA25: cmp3_in5_pta25 { 387 nxp,kinetis-port-pins = < 25 0 >; 388 }; 389 PTA25: GPIOA_PTA25: gpioa_pta25 { 390 nxp,kinetis-port-pins = < 25 1 >; 391 }; 392 MII0_TXCLK_PTA25: mii0_txclk_pta25 { 393 nxp,kinetis-port-pins = < 25 4 >; 394 }; 395 PTA26: GPIOA_PTA26: gpioa_pta26 { 396 nxp,kinetis-port-pins = < 26 1 >; 397 }; 398 MII0_TXD3_PTA26: mii0_txd3_pta26 { 399 nxp,kinetis-port-pins = < 26 4 >; 400 }; 401 PTA27: GPIOA_PTA27: gpioa_pta27 { 402 nxp,kinetis-port-pins = < 27 1 >; 403 }; 404 MII0_CRS_PTA27: mii0_crs_pta27 { 405 nxp,kinetis-port-pins = < 27 4 >; 406 }; 407 PTA28: GPIOA_PTA28: gpioa_pta28 { 408 nxp,kinetis-port-pins = < 28 1 >; 409 }; 410 MII0_TXER_PTA28: mii0_txer_pta28 { 411 nxp,kinetis-port-pins = < 28 4 >; 412 }; 413 PTA29: GPIOA_PTA29: gpioa_pta29 { 414 nxp,kinetis-port-pins = < 29 1 >; 415 }; 416 MII0_COL_PTA29: mii0_col_pta29 { 417 nxp,kinetis-port-pins = < 29 4 >; 418 }; 419}; 420 421&portb { 422 ADC0_SE8_PTB0: ADC1_SE8_PTB0: TSI0_CH0_PTB0: adc0_se8_ptb0 { 423 nxp,kinetis-port-pins = < 0 0 >; 424 }; 425 PTB0: GPIOB_PTB0: LLWU_P5_PTB0: gpiob_ptb0 { 426 nxp,kinetis-port-pins = < 0 1 >; 427 }; 428 I2C0_SCL_PTB0: i2c0_scl_ptb0 { 429 nxp,kinetis-port-pins = < 0 2 >; 430 }; 431 FTM1_CH0_PTB0: ftm1_ch0_ptb0 { 432 nxp,kinetis-port-pins = < 0 3 >; 433 }; 434 RMII0_MDIO_PTB0: MII0_MDIO_PTB0: rmii0_mdio_ptb0 { 435 nxp,kinetis-port-pins = < 0 4 >; 436 }; 437 SDRAM_CAS_b_PTB0: sdram_cas_b_ptb0 { 438 nxp,kinetis-port-pins = < 0 5 >; 439 }; 440 FTM1_QD_PHA_PTB0: TPM1_CH0_PTB0: ftm1_qd_pha_ptb0 { 441 nxp,kinetis-port-pins = < 0 6 >; 442 }; 443 ADC0_SE9_PTB1: ADC1_SE9_PTB1: TSI0_CH6_PTB1: adc0_se9_ptb1 { 444 nxp,kinetis-port-pins = < 1 0 >; 445 }; 446 PTB1: GPIOB_PTB1: gpiob_ptb1 { 447 nxp,kinetis-port-pins = < 1 1 >; 448 }; 449 I2C0_SDA_PTB1: i2c0_sda_ptb1 { 450 nxp,kinetis-port-pins = < 1 2 >; 451 }; 452 FTM1_CH1_PTB1: ftm1_ch1_ptb1 { 453 nxp,kinetis-port-pins = < 1 3 >; 454 }; 455 RMII0_MDC_PTB1: MII0_MDC_PTB1: rmii0_mdc_ptb1 { 456 nxp,kinetis-port-pins = < 1 4 >; 457 }; 458 SDRAM_RAS_b_PTB1: sdram_ras_b_ptb1 { 459 nxp,kinetis-port-pins = < 1 5 >; 460 }; 461 FTM1_QD_PHB_PTB1: TPM1_CH1_PTB1: ftm1_qd_phb_ptb1 { 462 nxp,kinetis-port-pins = < 1 6 >; 463 }; 464 ADC0_SE12_PTB2: TSI0_CH7_PTB2: adc0_se12_ptb2 { 465 nxp,kinetis-port-pins = < 2 0 >; 466 }; 467 PTB2: GPIOB_PTB2: gpiob_ptb2 { 468 nxp,kinetis-port-pins = < 2 1 >; 469 }; 470 I2C0_SCL_PTB2: i2c0_scl_ptb2 { 471 nxp,kinetis-port-pins = < 2 2 >; 472 }; 473 UART0_RTS_b_PTB2: uart0_rts_b_ptb2 { 474 nxp,kinetis-port-pins = < 2 3 >; 475 }; 476 ENET0_1588_TMR0_PTB2: enet0_1588_tmr0_ptb2 { 477 nxp,kinetis-port-pins = < 2 4 >; 478 }; 479 SDRAM_WE_PTB2: sdram_we_ptb2 { 480 nxp,kinetis-port-pins = < 2 5 >; 481 }; 482 FTM0_FLT3_PTB2: ftm0_flt3_ptb2 { 483 nxp,kinetis-port-pins = < 2 6 >; 484 }; 485 ADC0_SE13_PTB3: TSI0_CH8_PTB3: adc0_se13_ptb3 { 486 nxp,kinetis-port-pins = < 3 0 >; 487 }; 488 PTB3: GPIOB_PTB3: gpiob_ptb3 { 489 nxp,kinetis-port-pins = < 3 1 >; 490 }; 491 I2C0_SDA_PTB3: i2c0_sda_ptb3 { 492 nxp,kinetis-port-pins = < 3 2 >; 493 }; 494 UART0_CTS_b_PTB3: uart0_cts_b_ptb3 { 495 nxp,kinetis-port-pins = < 3 3 >; 496 }; 497 ENET0_1588_TMR1_PTB3: enet0_1588_tmr1_ptb3 { 498 nxp,kinetis-port-pins = < 3 4 >; 499 }; 500 SDRAM_CS0_b_PTB3: sdram_cs0_b_ptb3 { 501 nxp,kinetis-port-pins = < 3 5 >; 502 }; 503 FTM0_FLT0_PTB3: ftm0_flt0_ptb3 { 504 nxp,kinetis-port-pins = < 3 6 >; 505 }; 506 ADC1_SE10_PTB4: adc1_se10_ptb4 { 507 nxp,kinetis-port-pins = < 4 0 >; 508 }; 509 PTB4: GPIOB_PTB4: gpiob_ptb4 { 510 nxp,kinetis-port-pins = < 4 1 >; 511 }; 512 ENET0_1588_TMR2_PTB4: enet0_1588_tmr2_ptb4 { 513 nxp,kinetis-port-pins = < 4 4 >; 514 }; 515 SDRAM_CS1_b_PTB4: sdram_cs1_b_ptb4 { 516 nxp,kinetis-port-pins = < 4 5 >; 517 }; 518 FTM1_FLT0_PTB4: ftm1_flt0_ptb4 { 519 nxp,kinetis-port-pins = < 4 6 >; 520 }; 521 ADC1_SE11_PTB5: adc1_se11_ptb5 { 522 nxp,kinetis-port-pins = < 5 0 >; 523 }; 524 PTB5: GPIOB_PTB5: gpiob_ptb5 { 525 nxp,kinetis-port-pins = < 5 1 >; 526 }; 527 ENET0_1588_TMR3_PTB5: enet0_1588_tmr3_ptb5 { 528 nxp,kinetis-port-pins = < 5 4 >; 529 }; 530 FTM2_FLT0_PTB5: ftm2_flt0_ptb5 { 531 nxp,kinetis-port-pins = < 5 6 >; 532 }; 533 ADC1_SE12_PTB6: adc1_se12_ptb6 { 534 nxp,kinetis-port-pins = < 6 0 >; 535 }; 536 PTB6: GPIOB_PTB6: gpiob_ptb6 { 537 nxp,kinetis-port-pins = < 6 1 >; 538 }; 539 SDRAM_D23_PTB6: sdram_d23_ptb6 { 540 nxp,kinetis-port-pins = < 6 5 >; 541 }; 542 ADC1_SE13_PTB7: adc1_se13_ptb7 { 543 nxp,kinetis-port-pins = < 7 0 >; 544 }; 545 PTB7: GPIOB_PTB7: gpiob_ptb7 { 546 nxp,kinetis-port-pins = < 7 1 >; 547 }; 548 SDRAM_D22_PTB7: sdram_d22_ptb7 { 549 nxp,kinetis-port-pins = < 7 5 >; 550 }; 551 PTB8: GPIOB_PTB8: gpiob_ptb8 { 552 nxp,kinetis-port-pins = < 8 1 >; 553 }; 554 UART3_RTS_b_PTB8: uart3_rts_b_ptb8 { 555 nxp,kinetis-port-pins = < 8 3 >; 556 }; 557 SDRAM_D21_PTB8: sdram_d21_ptb8 { 558 nxp,kinetis-port-pins = < 8 5 >; 559 }; 560 PTB9: GPIOB_PTB9: gpiob_ptb9 { 561 nxp,kinetis-port-pins = < 9 1 >; 562 }; 563 SPI1_PCS1_PTB9: spi1_pcs1_ptb9 { 564 nxp,kinetis-port-pins = < 9 2 >; 565 }; 566 UART3_CTS_b_PTB9: uart3_cts_b_ptb9 { 567 nxp,kinetis-port-pins = < 9 3 >; 568 }; 569 SDRAM_D20_PTB9: sdram_d20_ptb9 { 570 nxp,kinetis-port-pins = < 9 5 >; 571 }; 572 ADC1_SE14_PTB10: adc1_se14_ptb10 { 573 nxp,kinetis-port-pins = < 10 0 >; 574 }; 575 PTB10: GPIOB_PTB10: gpiob_ptb10 { 576 nxp,kinetis-port-pins = < 10 1 >; 577 }; 578 SPI1_PCS0_PTB10: spi1_pcs0_ptb10 { 579 nxp,kinetis-port-pins = < 10 2 >; 580 }; 581 UART3_RX_PTB10: uart3_rx_ptb10 { 582 nxp,kinetis-port-pins = < 10 3 >; 583 }; 584 SDRAM_D19_PTB10: sdram_d19_ptb10 { 585 nxp,kinetis-port-pins = < 10 5 >; 586 }; 587 FTM0_FLT1_PTB10: ftm0_flt1_ptb10 { 588 nxp,kinetis-port-pins = < 10 6 >; 589 }; 590 ADC1_SE15_PTB11: adc1_se15_ptb11 { 591 nxp,kinetis-port-pins = < 11 0 >; 592 }; 593 PTB11: GPIOB_PTB11: gpiob_ptb11 { 594 nxp,kinetis-port-pins = < 11 1 >; 595 }; 596 SPI1_SCK_PTB11: spi1_sck_ptb11 { 597 nxp,kinetis-port-pins = < 11 2 >; 598 }; 599 UART3_TX_PTB11: uart3_tx_ptb11 { 600 nxp,kinetis-port-pins = < 11 3 >; 601 }; 602 SDRAM_D18_PTB11: sdram_d18_ptb11 { 603 nxp,kinetis-port-pins = < 11 5 >; 604 }; 605 FTM0_FLT2_PTB11: ftm0_flt2_ptb11 { 606 nxp,kinetis-port-pins = < 11 6 >; 607 }; 608 TSI0_CH9_PTB16: tsi0_ch9_ptb16 { 609 nxp,kinetis-port-pins = < 16 0 >; 610 }; 611 PTB16: GPIOB_PTB16: gpiob_ptb16 { 612 nxp,kinetis-port-pins = < 16 1 >; 613 }; 614 SPI1_SOUT_PTB16: spi1_sout_ptb16 { 615 nxp,kinetis-port-pins = < 16 2 >; 616 }; 617 UART0_RX_PTB16: uart0_rx_ptb16 { 618 nxp,kinetis-port-pins = < 16 3 >; 619 }; 620 FTM_CLKIN0_PTB16: ftm_clkin0_ptb16 { 621 nxp,kinetis-port-pins = < 16 4 >; 622 }; 623 SDRAM_D17_PTB16: sdram_d17_ptb16 { 624 nxp,kinetis-port-pins = < 16 5 >; 625 }; 626 EWM_IN_PTB16: ewm_in_ptb16 { 627 nxp,kinetis-port-pins = < 16 6 >; 628 }; 629 TPM_CLKIN0_PTB16: tpm_clkin0_ptb16 { 630 nxp,kinetis-port-pins = < 16 7 >; 631 }; 632 TSI0_CH10_PTB17: tsi0_ch10_ptb17 { 633 nxp,kinetis-port-pins = < 17 0 >; 634 }; 635 PTB17: GPIOB_PTB17: gpiob_ptb17 { 636 nxp,kinetis-port-pins = < 17 1 >; 637 }; 638 SPI1_SIN_PTB17: spi1_sin_ptb17 { 639 nxp,kinetis-port-pins = < 17 2 >; 640 }; 641 UART0_TX_PTB17: uart0_tx_ptb17 { 642 nxp,kinetis-port-pins = < 17 3 >; 643 }; 644 FTM_CLKIN1_PTB17: ftm_clkin1_ptb17 { 645 nxp,kinetis-port-pins = < 17 4 >; 646 }; 647 SDRAM_D16_PTB17: sdram_d16_ptb17 { 648 nxp,kinetis-port-pins = < 17 5 >; 649 }; 650 EWM_OUT_b_PTB17: ewm_out_b_ptb17 { 651 nxp,kinetis-port-pins = < 17 6 >; 652 }; 653 TPM_CLKIN1_PTB17: tpm_clkin1_ptb17 { 654 nxp,kinetis-port-pins = < 17 7 >; 655 }; 656 TSI0_CH11_PTB18: tsi0_ch11_ptb18 { 657 nxp,kinetis-port-pins = < 18 0 >; 658 }; 659 PTB18: GPIOB_PTB18: gpiob_ptb18 { 660 nxp,kinetis-port-pins = < 18 1 >; 661 }; 662 CAN0_TX_PTB18: can0_tx_ptb18 { 663 nxp,kinetis-port-pins = < 18 2 >; 664 }; 665 FTM2_CH0_PTB18: ftm2_ch0_ptb18 { 666 nxp,kinetis-port-pins = < 18 3 >; 667 }; 668 I2S0_TX_BCLK_PTB18: i2s0_tx_bclk_ptb18 { 669 nxp,kinetis-port-pins = < 18 4 >; 670 }; 671 SDRAM_A23_PTB18: sdram_a23_ptb18 { 672 nxp,kinetis-port-pins = < 18 5 >; 673 }; 674 FTM2_QD_PHA_PTB18: TPM2_CH0_PTB18: ftm2_qd_pha_ptb18 { 675 nxp,kinetis-port-pins = < 18 6 >; 676 }; 677 TSI0_CH12_PTB19: tsi0_ch12_ptb19 { 678 nxp,kinetis-port-pins = < 19 0 >; 679 }; 680 PTB19: GPIOB_PTB19: gpiob_ptb19 { 681 nxp,kinetis-port-pins = < 19 1 >; 682 }; 683 CAN0_RX_PTB19: can0_rx_ptb19 { 684 nxp,kinetis-port-pins = < 19 2 >; 685 }; 686 FTM2_CH1_PTB19: ftm2_ch1_ptb19 { 687 nxp,kinetis-port-pins = < 19 3 >; 688 }; 689 I2S0_TX_FS_PTB19: i2s0_tx_fs_ptb19 { 690 nxp,kinetis-port-pins = < 19 4 >; 691 }; 692 FTM2_QD_PHB_PTB19: TPM2_CH1_PTB19: ftm2_qd_phb_ptb19 { 693 nxp,kinetis-port-pins = < 19 6 >; 694 }; 695 PTB20: GPIOB_PTB20: gpiob_ptb20 { 696 nxp,kinetis-port-pins = < 20 1 >; 697 }; 698 SPI2_PCS0_PTB20: spi2_pcs0_ptb20 { 699 nxp,kinetis-port-pins = < 20 2 >; 700 }; 701 SDRAM_D31_PTB20: sdram_d31_ptb20 { 702 nxp,kinetis-port-pins = < 20 5 >; 703 }; 704 CMP0_OUT_PTB20: cmp0_out_ptb20 { 705 nxp,kinetis-port-pins = < 20 6 >; 706 }; 707 PTB21: GPIOB_PTB21: gpiob_ptb21 { 708 nxp,kinetis-port-pins = < 21 1 >; 709 }; 710 SPI2_SCK_PTB21: spi2_sck_ptb21 { 711 nxp,kinetis-port-pins = < 21 2 >; 712 }; 713 SDRAM_D30_PTB21: sdram_d30_ptb21 { 714 nxp,kinetis-port-pins = < 21 5 >; 715 }; 716 CMP1_OUT_PTB21: cmp1_out_ptb21 { 717 nxp,kinetis-port-pins = < 21 6 >; 718 }; 719 PTB22: GPIOB_PTB22: gpiob_ptb22 { 720 nxp,kinetis-port-pins = < 22 1 >; 721 }; 722 SPI2_SOUT_PTB22: spi2_sout_ptb22 { 723 nxp,kinetis-port-pins = < 22 2 >; 724 }; 725 SDRAM_D29_PTB22: sdram_d29_ptb22 { 726 nxp,kinetis-port-pins = < 22 5 >; 727 }; 728 CMP2_OUT_PTB22: cmp2_out_ptb22 { 729 nxp,kinetis-port-pins = < 22 6 >; 730 }; 731 PTB23: GPIOB_PTB23: gpiob_ptb23 { 732 nxp,kinetis-port-pins = < 23 1 >; 733 }; 734 SPI2_SIN_PTB23: spi2_sin_ptb23 { 735 nxp,kinetis-port-pins = < 23 2 >; 736 }; 737 SPI0_PCS5_PTB23: spi0_pcs5_ptb23 { 738 nxp,kinetis-port-pins = < 23 3 >; 739 }; 740 SDRAM_D28_PTB23: sdram_d28_ptb23 { 741 nxp,kinetis-port-pins = < 23 5 >; 742 }; 743 CMP3_OUT_PTB23: cmp3_out_ptb23 { 744 nxp,kinetis-port-pins = < 23 6 >; 745 }; 746}; 747 748&portc { 749 ADC0_SE14_PTC0: TSI0_CH13_PTC0: adc0_se14_ptc0 { 750 nxp,kinetis-port-pins = < 0 0 >; 751 }; 752 PTC0: GPIOC_PTC0: gpioc_ptc0 { 753 nxp,kinetis-port-pins = < 0 1 >; 754 }; 755 SPI0_PCS4_PTC0: spi0_pcs4_ptc0 { 756 nxp,kinetis-port-pins = < 0 2 >; 757 }; 758 PDB0_EXTRG_PTC0: pdb0_extrg_ptc0 { 759 nxp,kinetis-port-pins = < 0 3 >; 760 }; 761 USB0_SOF_OUT_PTC0: usb0_sof_out_ptc0 { 762 nxp,kinetis-port-pins = < 0 4 >; 763 }; 764 SDRAM_A22_PTC0: sdram_a22_ptc0 { 765 nxp,kinetis-port-pins = < 0 5 >; 766 }; 767 I2S0_TXD1_PTC0: i2s0_txd1_ptc0 { 768 nxp,kinetis-port-pins = < 0 6 >; 769 }; 770 ADC0_SE15_PTC1: TSI0_CH14_PTC1: adc0_se15_ptc1 { 771 nxp,kinetis-port-pins = < 1 0 >; 772 }; 773 PTC1: GPIOC_PTC1: LLWU_P6_PTC1: gpioc_ptc1 { 774 nxp,kinetis-port-pins = < 1 1 >; 775 }; 776 SPI0_PCS3_PTC1: spi0_pcs3_ptc1 { 777 nxp,kinetis-port-pins = < 1 2 >; 778 }; 779 UART1_RTS_b_PTC1: uart1_rts_b_ptc1 { 780 nxp,kinetis-port-pins = < 1 3 >; 781 }; 782 FTM0_CH0_PTC1: ftm0_ch0_ptc1 { 783 nxp,kinetis-port-pins = < 1 4 >; 784 }; 785 SDRAM_A21_PTC1: sdram_a21_ptc1 { 786 nxp,kinetis-port-pins = < 1 5 >; 787 }; 788 I2S0_TXD0_PTC1: i2s0_txd0_ptc1 { 789 nxp,kinetis-port-pins = < 1 6 >; 790 }; 791 ADC0_SE4b_PTC2: CMP1_IN0_PTC2: TSI0_CH15_PTC2: adc0_se4b_ptc2 { 792 nxp,kinetis-port-pins = < 2 0 >; 793 }; 794 PTC2: GPIOC_PTC2: gpioc_ptc2 { 795 nxp,kinetis-port-pins = < 2 1 >; 796 }; 797 SPI0_PCS2_PTC2: spi0_pcs2_ptc2 { 798 nxp,kinetis-port-pins = < 2 2 >; 799 }; 800 UART1_CTS_b_PTC2: uart1_cts_b_ptc2 { 801 nxp,kinetis-port-pins = < 2 3 >; 802 }; 803 FTM0_CH1_PTC2: ftm0_ch1_ptc2 { 804 nxp,kinetis-port-pins = < 2 4 >; 805 }; 806 SDRAM_A20_PTC2: sdram_a20_ptc2 { 807 nxp,kinetis-port-pins = < 2 5 >; 808 }; 809 I2S0_TX_FS_PTC2: i2s0_tx_fs_ptc2 { 810 nxp,kinetis-port-pins = < 2 6 >; 811 }; 812 CMP1_IN1_PTC3: cmp1_in1_ptc3 { 813 nxp,kinetis-port-pins = < 3 0 >; 814 }; 815 PTC3: GPIOC_PTC3: LLWU_P7_PTC3: gpioc_ptc3 { 816 nxp,kinetis-port-pins = < 3 1 >; 817 }; 818 SPI0_PCS1_PTC3: spi0_pcs1_ptc3 { 819 nxp,kinetis-port-pins = < 3 2 >; 820 }; 821 UART1_RX_PTC3: uart1_rx_ptc3 { 822 nxp,kinetis-port-pins = < 3 3 >; 823 }; 824 FTM0_CH2_PTC3: ftm0_ch2_ptc3 { 825 nxp,kinetis-port-pins = < 3 4 >; 826 }; 827 CLKOUT_PTC3: clkout_ptc3 { 828 nxp,kinetis-port-pins = < 3 5 >; 829 }; 830 I2S0_TX_BCLK_PTC3: i2s0_tx_bclk_ptc3 { 831 nxp,kinetis-port-pins = < 3 6 >; 832 }; 833 PTC4: GPIOC_PTC4: LLWU_P8_PTC4: gpioc_ptc4 { 834 nxp,kinetis-port-pins = < 4 1 >; 835 }; 836 SPI0_PCS0_PTC4: spi0_pcs0_ptc4 { 837 nxp,kinetis-port-pins = < 4 2 >; 838 }; 839 UART1_TX_PTC4: uart1_tx_ptc4 { 840 nxp,kinetis-port-pins = < 4 3 >; 841 }; 842 FTM0_CH3_PTC4: ftm0_ch3_ptc4 { 843 nxp,kinetis-port-pins = < 4 4 >; 844 }; 845 SDRAM_A19_PTC4: sdram_a19_ptc4 { 846 nxp,kinetis-port-pins = < 4 5 >; 847 }; 848 CMP1_OUT_PTC4: cmp1_out_ptc4 { 849 nxp,kinetis-port-pins = < 4 6 >; 850 }; 851 PTC5: GPIOC_PTC5: LLWU_P9_PTC5: gpioc_ptc5 { 852 nxp,kinetis-port-pins = < 5 1 >; 853 }; 854 SPI0_SCK_PTC5: spi0_sck_ptc5 { 855 nxp,kinetis-port-pins = < 5 2 >; 856 }; 857 LPTMR0_ALT2_PTC5: lptmr0_alt2_ptc5 { 858 nxp,kinetis-port-pins = < 5 3 >; 859 }; 860 I2S0_RXD0_PTC5: i2s0_rxd0_ptc5 { 861 nxp,kinetis-port-pins = < 5 4 >; 862 }; 863 SDRAM_A18_PTC5: sdram_a18_ptc5 { 864 nxp,kinetis-port-pins = < 5 5 >; 865 }; 866 CMP0_OUT_PTC5: cmp0_out_ptc5 { 867 nxp,kinetis-port-pins = < 5 6 >; 868 }; 869 FTM0_CH2_PTC5: ftm0_ch2_ptc5 { 870 nxp,kinetis-port-pins = < 5 7 >; 871 }; 872 CMP0_IN0_PTC6: cmp0_in0_ptc6 { 873 nxp,kinetis-port-pins = < 6 0 >; 874 }; 875 PTC6: GPIOC_PTC6: LLWU_P10_PTC6: gpioc_ptc6 { 876 nxp,kinetis-port-pins = < 6 1 >; 877 }; 878 SPI0_SOUT_PTC6: spi0_sout_ptc6 { 879 nxp,kinetis-port-pins = < 6 2 >; 880 }; 881 PDB0_EXTRG_PTC6: pdb0_extrg_ptc6 { 882 nxp,kinetis-port-pins = < 6 3 >; 883 }; 884 I2S0_RX_BCLK_PTC6: i2s0_rx_bclk_ptc6 { 885 nxp,kinetis-port-pins = < 6 4 >; 886 }; 887 SDRAM_A17_PTC6: sdram_a17_ptc6 { 888 nxp,kinetis-port-pins = < 6 5 >; 889 }; 890 I2S0_MCLK_PTC6: i2s0_mclk_ptc6 { 891 nxp,kinetis-port-pins = < 6 6 >; 892 }; 893 CMP0_IN1_PTC7: cmp0_in1_ptc7 { 894 nxp,kinetis-port-pins = < 7 0 >; 895 }; 896 PTC7: GPIOC_PTC7: gpioc_ptc7 { 897 nxp,kinetis-port-pins = < 7 1 >; 898 }; 899 SPI0_SIN_PTC7: spi0_sin_ptc7 { 900 nxp,kinetis-port-pins = < 7 2 >; 901 }; 902 USB0_SOF_OUT_PTC7: usb0_sof_out_ptc7 { 903 nxp,kinetis-port-pins = < 7 3 >; 904 }; 905 I2S0_RX_FS_PTC7: i2s0_rx_fs_ptc7 { 906 nxp,kinetis-port-pins = < 7 4 >; 907 }; 908 SDRAM_A16_PTC7: sdram_a16_ptc7 { 909 nxp,kinetis-port-pins = < 7 5 >; 910 }; 911 ADC1_SE4b_PTC8: CMP0_IN2_PTC8: adc1_se4b_ptc8 { 912 nxp,kinetis-port-pins = < 8 0 >; 913 }; 914 PTC8: GPIOC_PTC8: gpioc_ptc8 { 915 nxp,kinetis-port-pins = < 8 1 >; 916 }; 917 FTM3_CH4_PTC8: ftm3_ch4_ptc8 { 918 nxp,kinetis-port-pins = < 8 3 >; 919 }; 920 I2S0_MCLK_PTC8: i2s0_mclk_ptc8 { 921 nxp,kinetis-port-pins = < 8 4 >; 922 }; 923 SDRAM_A15_PTC8: sdram_a15_ptc8 { 924 nxp,kinetis-port-pins = < 8 5 >; 925 }; 926 ADC1_SE5b_PTC9: CMP0_IN3_PTC9: adc1_se5b_ptc9 { 927 nxp,kinetis-port-pins = < 9 0 >; 928 }; 929 PTC9: GPIOC_PTC9: gpioc_ptc9 { 930 nxp,kinetis-port-pins = < 9 1 >; 931 }; 932 FTM3_CH5_PTC9: ftm3_ch5_ptc9 { 933 nxp,kinetis-port-pins = < 9 3 >; 934 }; 935 I2S0_RX_BCLK_PTC9: i2s0_rx_bclk_ptc9 { 936 nxp,kinetis-port-pins = < 9 4 >; 937 }; 938 SDRAM_A14_PTC9: sdram_a14_ptc9 { 939 nxp,kinetis-port-pins = < 9 5 >; 940 }; 941 FTM2_FLT0_PTC9: ftm2_flt0_ptc9 { 942 nxp,kinetis-port-pins = < 9 6 >; 943 }; 944 ADC1_SE6b_PTC10: adc1_se6b_ptc10 { 945 nxp,kinetis-port-pins = < 10 0 >; 946 }; 947 PTC10: GPIOC_PTC10: gpioc_ptc10 { 948 nxp,kinetis-port-pins = < 10 1 >; 949 }; 950 I2C1_SCL_PTC10: i2c1_scl_ptc10 { 951 nxp,kinetis-port-pins = < 10 2 >; 952 }; 953 FTM3_CH6_PTC10: ftm3_ch6_ptc10 { 954 nxp,kinetis-port-pins = < 10 3 >; 955 }; 956 I2S0_RX_FS_PTC10: i2s0_rx_fs_ptc10 { 957 nxp,kinetis-port-pins = < 10 4 >; 958 }; 959 SDRAM_A13_PTC10: sdram_a13_ptc10 { 960 nxp,kinetis-port-pins = < 10 5 >; 961 }; 962 ADC1_SE7b_PTC11: adc1_se7b_ptc11 { 963 nxp,kinetis-port-pins = < 11 0 >; 964 }; 965 PTC11: GPIOC_PTC11: LLWU_P11_PTC11: gpioc_ptc11 { 966 nxp,kinetis-port-pins = < 11 1 >; 967 }; 968 I2C1_SDA_PTC11: i2c1_sda_ptc11 { 969 nxp,kinetis-port-pins = < 11 2 >; 970 }; 971 FTM3_CH7_PTC11: ftm3_ch7_ptc11 { 972 nxp,kinetis-port-pins = < 11 3 >; 973 }; 974 I2S0_RXD1_PTC11: i2s0_rxd1_ptc11 { 975 nxp,kinetis-port-pins = < 11 4 >; 976 }; 977 PTC12: GPIOC_PTC12: gpioc_ptc12 { 978 nxp,kinetis-port-pins = < 12 1 >; 979 }; 980 UART4_RTS_b_PTC12: uart4_rts_b_ptc12 { 981 nxp,kinetis-port-pins = < 12 3 >; 982 }; 983 FTM_CLKIN0_PTC12: ftm_clkin0_ptc12 { 984 nxp,kinetis-port-pins = < 12 4 >; 985 }; 986 SDRAM_D27_PTC12: sdram_d27_ptc12 { 987 nxp,kinetis-port-pins = < 12 5 >; 988 }; 989 FTM3_FLT0_PTC12: ftm3_flt0_ptc12 { 990 nxp,kinetis-port-pins = < 12 6 >; 991 }; 992 TPM_CLKIN0_PTC12: tpm_clkin0_ptc12 { 993 nxp,kinetis-port-pins = < 12 7 >; 994 }; 995 PTC13: GPIOC_PTC13: gpioc_ptc13 { 996 nxp,kinetis-port-pins = < 13 1 >; 997 }; 998 UART4_CTS_b_PTC13: uart4_cts_b_ptc13 { 999 nxp,kinetis-port-pins = < 13 3 >; 1000 }; 1001 FTM_CLKIN1_PTC13: ftm_clkin1_ptc13 { 1002 nxp,kinetis-port-pins = < 13 4 >; 1003 }; 1004 SDRAM_D26_PTC13: sdram_d26_ptc13 { 1005 nxp,kinetis-port-pins = < 13 5 >; 1006 }; 1007 TPM_CLKIN1_PTC13: tpm_clkin1_ptc13 { 1008 nxp,kinetis-port-pins = < 13 7 >; 1009 }; 1010 PTC14: GPIOC_PTC14: gpioc_ptc14 { 1011 nxp,kinetis-port-pins = < 14 1 >; 1012 }; 1013 UART4_RX_PTC14: uart4_rx_ptc14 { 1014 nxp,kinetis-port-pins = < 14 3 >; 1015 }; 1016 SDRAM_D25_PTC14: sdram_d25_ptc14 { 1017 nxp,kinetis-port-pins = < 14 5 >; 1018 }; 1019 PTC15: GPIOC_PTC15: gpioc_ptc15 { 1020 nxp,kinetis-port-pins = < 15 1 >; 1021 }; 1022 UART4_TX_PTC15: uart4_tx_ptc15 { 1023 nxp,kinetis-port-pins = < 15 3 >; 1024 }; 1025 SDRAM_D24_PTC15: sdram_d24_ptc15 { 1026 nxp,kinetis-port-pins = < 15 5 >; 1027 }; 1028 PTC16: GPIOC_PTC16: gpioc_ptc16 { 1029 nxp,kinetis-port-pins = < 16 1 >; 1030 }; 1031 CAN1_RX_PTC16: can1_rx_ptc16 { 1032 nxp,kinetis-port-pins = < 16 2 >; 1033 }; 1034 UART3_RX_PTC16: uart3_rx_ptc16 { 1035 nxp,kinetis-port-pins = < 16 3 >; 1036 }; 1037 ENET0_1588_TMR0_PTC16: enet0_1588_tmr0_ptc16 { 1038 nxp,kinetis-port-pins = < 16 4 >; 1039 }; 1040 SDRAM_DQM2_PTC16: sdram_dqm2_ptc16 { 1041 nxp,kinetis-port-pins = < 16 5 >; 1042 }; 1043 PTC17: GPIOC_PTC17: gpioc_ptc17 { 1044 nxp,kinetis-port-pins = < 17 1 >; 1045 }; 1046 CAN1_TX_PTC17: can1_tx_ptc17 { 1047 nxp,kinetis-port-pins = < 17 2 >; 1048 }; 1049 UART3_TX_PTC17: uart3_tx_ptc17 { 1050 nxp,kinetis-port-pins = < 17 3 >; 1051 }; 1052 ENET0_1588_TMR1_PTC17: enet0_1588_tmr1_ptc17 { 1053 nxp,kinetis-port-pins = < 17 4 >; 1054 }; 1055 SDRAM_DQM3_PTC17: sdram_dqm3_ptc17 { 1056 nxp,kinetis-port-pins = < 17 5 >; 1057 }; 1058 PTC18: GPIOC_PTC18: gpioc_ptc18 { 1059 nxp,kinetis-port-pins = < 18 1 >; 1060 }; 1061 UART3_RTS_b_PTC18: uart3_rts_b_ptc18 { 1062 nxp,kinetis-port-pins = < 18 3 >; 1063 }; 1064 ENET0_1588_TMR2_PTC18: enet0_1588_tmr2_ptc18 { 1065 nxp,kinetis-port-pins = < 18 4 >; 1066 }; 1067 SDRAM_DQM1_PTC18: sdram_dqm1_ptc18 { 1068 nxp,kinetis-port-pins = < 18 5 >; 1069 }; 1070 PTC19: GPIOC_PTC19: gpioc_ptc19 { 1071 nxp,kinetis-port-pins = < 19 1 >; 1072 }; 1073 UART3_CTS_b_PTC19: uart3_cts_b_ptc19 { 1074 nxp,kinetis-port-pins = < 19 3 >; 1075 }; 1076 ENET0_1588_TMR3_PTC19: enet0_1588_tmr3_ptc19 { 1077 nxp,kinetis-port-pins = < 19 4 >; 1078 }; 1079 SDRAM_DQM0_PTC19: sdram_dqm0_ptc19 { 1080 nxp,kinetis-port-pins = < 19 5 >; 1081 }; 1082}; 1083 1084&portd { 1085 PTD0: GPIOD_PTD0: LLWU_P12_PTD0: gpiod_ptd0 { 1086 nxp,kinetis-port-pins = < 0 1 >; 1087 }; 1088 SPI0_PCS0_PTD0: spi0_pcs0_ptd0 { 1089 nxp,kinetis-port-pins = < 0 2 >; 1090 }; 1091 UART2_RTS_b_PTD0: uart2_rts_b_ptd0 { 1092 nxp,kinetis-port-pins = < 0 3 >; 1093 }; 1094 FTM3_CH0_PTD0: ftm3_ch0_ptd0 { 1095 nxp,kinetis-port-pins = < 0 4 >; 1096 }; 1097 ADC0_SE5b_PTD1: adc0_se5b_ptd1 { 1098 nxp,kinetis-port-pins = < 1 0 >; 1099 }; 1100 PTD1: GPIOD_PTD1: gpiod_ptd1 { 1101 nxp,kinetis-port-pins = < 1 1 >; 1102 }; 1103 SPI0_SCK_PTD1: spi0_sck_ptd1 { 1104 nxp,kinetis-port-pins = < 1 2 >; 1105 }; 1106 UART2_CTS_b_PTD1: uart2_cts_b_ptd1 { 1107 nxp,kinetis-port-pins = < 1 3 >; 1108 }; 1109 FTM3_CH1_PTD1: ftm3_ch1_ptd1 { 1110 nxp,kinetis-port-pins = < 1 4 >; 1111 }; 1112 PTD2: GPIOD_PTD2: LLWU_P13_PTD2: gpiod_ptd2 { 1113 nxp,kinetis-port-pins = < 2 1 >; 1114 }; 1115 SPI0_SOUT_PTD2: spi0_sout_ptd2 { 1116 nxp,kinetis-port-pins = < 2 2 >; 1117 }; 1118 UART2_RX_PTD2: uart2_rx_ptd2 { 1119 nxp,kinetis-port-pins = < 2 3 >; 1120 }; 1121 FTM3_CH2_PTD2: ftm3_ch2_ptd2 { 1122 nxp,kinetis-port-pins = < 2 4 >; 1123 }; 1124 SDRAM_A12_PTD2: sdram_a12_ptd2 { 1125 nxp,kinetis-port-pins = < 2 5 >; 1126 }; 1127 I2C0_SCL_PTD2: i2c0_scl_ptd2 { 1128 nxp,kinetis-port-pins = < 2 7 >; 1129 }; 1130 PTD3: GPIOD_PTD3: gpiod_ptd3 { 1131 nxp,kinetis-port-pins = < 3 1 >; 1132 }; 1133 SPI0_SIN_PTD3: spi0_sin_ptd3 { 1134 nxp,kinetis-port-pins = < 3 2 >; 1135 }; 1136 UART2_TX_PTD3: uart2_tx_ptd3 { 1137 nxp,kinetis-port-pins = < 3 3 >; 1138 }; 1139 FTM3_CH3_PTD3: ftm3_ch3_ptd3 { 1140 nxp,kinetis-port-pins = < 3 4 >; 1141 }; 1142 SDRAM_A11_PTD3: sdram_a11_ptd3 { 1143 nxp,kinetis-port-pins = < 3 5 >; 1144 }; 1145 I2C0_SDA_PTD3: i2c0_sda_ptd3 { 1146 nxp,kinetis-port-pins = < 3 7 >; 1147 }; 1148 PTD4: GPIOD_PTD4: LLWU_P14_PTD4: gpiod_ptd4 { 1149 nxp,kinetis-port-pins = < 4 1 >; 1150 }; 1151 SPI0_PCS1_PTD4: spi0_pcs1_ptd4 { 1152 nxp,kinetis-port-pins = < 4 2 >; 1153 }; 1154 UART0_RTS_b_PTD4: uart0_rts_b_ptd4 { 1155 nxp,kinetis-port-pins = < 4 3 >; 1156 }; 1157 FTM0_CH4_PTD4: ftm0_ch4_ptd4 { 1158 nxp,kinetis-port-pins = < 4 4 >; 1159 }; 1160 SDRAM_A10_PTD4: sdram_a10_ptd4 { 1161 nxp,kinetis-port-pins = < 4 5 >; 1162 }; 1163 EWM_IN_PTD4: ewm_in_ptd4 { 1164 nxp,kinetis-port-pins = < 4 6 >; 1165 }; 1166 SPI1_PCS0_PTD4: spi1_pcs0_ptd4 { 1167 nxp,kinetis-port-pins = < 4 7 >; 1168 }; 1169 ADC0_SE6b_PTD5: adc0_se6b_ptd5 { 1170 nxp,kinetis-port-pins = < 5 0 >; 1171 }; 1172 PTD5: GPIOD_PTD5: gpiod_ptd5 { 1173 nxp,kinetis-port-pins = < 5 1 >; 1174 }; 1175 SPI0_PCS2_PTD5: spi0_pcs2_ptd5 { 1176 nxp,kinetis-port-pins = < 5 2 >; 1177 }; 1178 UART0_CTS_b_PTD5: uart0_cts_b_ptd5 { 1179 nxp,kinetis-port-pins = < 5 3 >; 1180 }; 1181 FTM0_CH5_PTD5: ftm0_ch5_ptd5 { 1182 nxp,kinetis-port-pins = < 5 4 >; 1183 }; 1184 SDRAM_A9_PTD5: sdram_a9_ptd5 { 1185 nxp,kinetis-port-pins = < 5 5 >; 1186 }; 1187 EWM_OUT_b_PTD5: ewm_out_b_ptd5 { 1188 nxp,kinetis-port-pins = < 5 6 >; 1189 }; 1190 SPI1_SCK_PTD5: spi1_sck_ptd5 { 1191 nxp,kinetis-port-pins = < 5 7 >; 1192 }; 1193 ADC0_SE7b_PTD6: adc0_se7b_ptd6 { 1194 nxp,kinetis-port-pins = < 6 0 >; 1195 }; 1196 PTD6: GPIOD_PTD6: LLWU_P15_PTD6: gpiod_ptd6 { 1197 nxp,kinetis-port-pins = < 6 1 >; 1198 }; 1199 SPI0_PCS3_PTD6: spi0_pcs3_ptd6 { 1200 nxp,kinetis-port-pins = < 6 2 >; 1201 }; 1202 UART0_RX_PTD6: uart0_rx_ptd6 { 1203 nxp,kinetis-port-pins = < 6 3 >; 1204 }; 1205 FTM0_CH6_PTD6: ftm0_ch6_ptd6 { 1206 nxp,kinetis-port-pins = < 6 4 >; 1207 }; 1208 FTM0_FLT0_PTD6: ftm0_flt0_ptd6 { 1209 nxp,kinetis-port-pins = < 6 6 >; 1210 }; 1211 SPI1_SOUT_PTD6: spi1_sout_ptd6 { 1212 nxp,kinetis-port-pins = < 6 7 >; 1213 }; 1214 PTD7: GPIOD_PTD7: gpiod_ptd7 { 1215 nxp,kinetis-port-pins = < 7 1 >; 1216 }; 1217 CMT_IRO_PTD7: cmt_iro_ptd7 { 1218 nxp,kinetis-port-pins = < 7 2 >; 1219 }; 1220 UART0_TX_PTD7: uart0_tx_ptd7 { 1221 nxp,kinetis-port-pins = < 7 3 >; 1222 }; 1223 FTM0_CH7_PTD7: ftm0_ch7_ptd7 { 1224 nxp,kinetis-port-pins = < 7 4 >; 1225 }; 1226 SDRAM_CKE_PTD7: sdram_cke_ptd7 { 1227 nxp,kinetis-port-pins = < 7 5 >; 1228 }; 1229 FTM0_FLT1_PTD7: ftm0_flt1_ptd7 { 1230 nxp,kinetis-port-pins = < 7 6 >; 1231 }; 1232 SPI1_SIN_PTD7: spi1_sin_ptd7 { 1233 nxp,kinetis-port-pins = < 7 7 >; 1234 }; 1235 PTD8: GPIOD_PTD8: LLWU_P24_PTD8: gpiod_ptd8 { 1236 nxp,kinetis-port-pins = < 8 1 >; 1237 }; 1238 I2C0_SCL_PTD8: i2c0_scl_ptd8 { 1239 nxp,kinetis-port-pins = < 8 2 >; 1240 }; 1241 LPUART0_RX_PTD8: lpuart0_rx_ptd8 { 1242 nxp,kinetis-port-pins = < 8 5 >; 1243 }; 1244 PTD9: GPIOD_PTD9: gpiod_ptd9 { 1245 nxp,kinetis-port-pins = < 9 1 >; 1246 }; 1247 I2C0_SDA_PTD9: i2c0_sda_ptd9 { 1248 nxp,kinetis-port-pins = < 9 2 >; 1249 }; 1250 LPUART0_TX_PTD9: lpuart0_tx_ptd9 { 1251 nxp,kinetis-port-pins = < 9 5 >; 1252 }; 1253 PTD10: GPIOD_PTD10: gpiod_ptd10 { 1254 nxp,kinetis-port-pins = < 10 1 >; 1255 }; 1256 LPUART0_RTS_b_PTD10: lpuart0_rts_b_ptd10 { 1257 nxp,kinetis-port-pins = < 10 5 >; 1258 }; 1259 PTD11: GPIOD_PTD11: LLWU_P25_PTD11: gpiod_ptd11 { 1260 nxp,kinetis-port-pins = < 11 1 >; 1261 }; 1262 SPI2_PCS0_PTD11: spi2_pcs0_ptd11 { 1263 nxp,kinetis-port-pins = < 11 2 >; 1264 }; 1265 SDHC0_CLKIN_PTD11: sdhc0_clkin_ptd11 { 1266 nxp,kinetis-port-pins = < 11 4 >; 1267 }; 1268 LPUART0_CTS_b_PTD11: lpuart0_cts_b_ptd11 { 1269 nxp,kinetis-port-pins = < 11 5 >; 1270 }; 1271 PTD12: GPIOD_PTD12: gpiod_ptd12 { 1272 nxp,kinetis-port-pins = < 12 1 >; 1273 }; 1274 SPI2_SCK_PTD12: spi2_sck_ptd12 { 1275 nxp,kinetis-port-pins = < 12 2 >; 1276 }; 1277 FTM3_FLT0_PTD12: ftm3_flt0_ptd12 { 1278 nxp,kinetis-port-pins = < 12 3 >; 1279 }; 1280 SDHC0_D4_PTD12: sdhc0_d4_ptd12 { 1281 nxp,kinetis-port-pins = < 12 4 >; 1282 }; 1283 PTD13: GPIOD_PTD13: gpiod_ptd13 { 1284 nxp,kinetis-port-pins = < 13 1 >; 1285 }; 1286 SPI2_SOUT_PTD13: spi2_sout_ptd13 { 1287 nxp,kinetis-port-pins = < 13 2 >; 1288 }; 1289 SDHC0_D5_PTD13: sdhc0_d5_ptd13 { 1290 nxp,kinetis-port-pins = < 13 4 >; 1291 }; 1292 PTD14: GPIOD_PTD14: gpiod_ptd14 { 1293 nxp,kinetis-port-pins = < 14 1 >; 1294 }; 1295 SPI2_SIN_PTD14: spi2_sin_ptd14 { 1296 nxp,kinetis-port-pins = < 14 2 >; 1297 }; 1298 SDHC0_D6_PTD14: sdhc0_d6_ptd14 { 1299 nxp,kinetis-port-pins = < 14 4 >; 1300 }; 1301 PTD15: GPIOD_PTD15: gpiod_ptd15 { 1302 nxp,kinetis-port-pins = < 15 1 >; 1303 }; 1304 SPI2_PCS1_PTD15: spi2_pcs1_ptd15 { 1305 nxp,kinetis-port-pins = < 15 2 >; 1306 }; 1307 SDHC0_D7_PTD15: sdhc0_d7_ptd15 { 1308 nxp,kinetis-port-pins = < 15 4 >; 1309 }; 1310}; 1311 1312&porte { 1313 ADC1_SE4a_PTE0: adc1_se4a_pte0 { 1314 nxp,kinetis-port-pins = < 0 0 >; 1315 }; 1316 PTE0: GPIOE_PTE0: gpioe_pte0 { 1317 nxp,kinetis-port-pins = < 0 1 >; 1318 }; 1319 SPI1_PCS1_PTE0: spi1_pcs1_pte0 { 1320 nxp,kinetis-port-pins = < 0 2 >; 1321 }; 1322 UART1_TX_PTE0: uart1_tx_pte0 { 1323 nxp,kinetis-port-pins = < 0 3 >; 1324 }; 1325 SDHC0_D1_PTE0: sdhc0_d1_pte0 { 1326 nxp,kinetis-port-pins = < 0 4 >; 1327 }; 1328 TRACE_CLKOUT_PTE0: trace_clkout_pte0 { 1329 nxp,kinetis-port-pins = < 0 5 >; 1330 }; 1331 I2C1_SDA_PTE0: i2c1_sda_pte0 { 1332 nxp,kinetis-port-pins = < 0 6 >; 1333 }; 1334 RTC_CLKOUT_PTE0: rtc_clkout_pte0 { 1335 nxp,kinetis-port-pins = < 0 7 >; 1336 }; 1337 ADC1_SE5a_PTE1: adc1_se5a_pte1 { 1338 nxp,kinetis-port-pins = < 1 0 >; 1339 }; 1340 PTE1: GPIOE_PTE1: LLWU_P0_PTE1: gpioe_pte1 { 1341 nxp,kinetis-port-pins = < 1 1 >; 1342 }; 1343 SPI1_SOUT_PTE1: spi1_sout_pte1 { 1344 nxp,kinetis-port-pins = < 1 2 >; 1345 }; 1346 UART1_RX_PTE1: uart1_rx_pte1 { 1347 nxp,kinetis-port-pins = < 1 3 >; 1348 }; 1349 SDHC0_D0_PTE1: sdhc0_d0_pte1 { 1350 nxp,kinetis-port-pins = < 1 4 >; 1351 }; 1352 TRACE_D3_PTE1: trace_d3_pte1 { 1353 nxp,kinetis-port-pins = < 1 5 >; 1354 }; 1355 I2C1_SCL_PTE1: i2c1_scl_pte1 { 1356 nxp,kinetis-port-pins = < 1 6 >; 1357 }; 1358 SPI1_SIN_PTE1: spi1_sin_pte1 { 1359 nxp,kinetis-port-pins = < 1 7 >; 1360 }; 1361 ADC1_SE6a_PTE2: adc1_se6a_pte2 { 1362 nxp,kinetis-port-pins = < 2 0 >; 1363 }; 1364 PTE2: GPIOE_PTE2: LLWU_P1_PTE2: gpioe_pte2 { 1365 nxp,kinetis-port-pins = < 2 1 >; 1366 }; 1367 SPI1_SCK_PTE2: spi1_sck_pte2 { 1368 nxp,kinetis-port-pins = < 2 2 >; 1369 }; 1370 UART1_CTS_b_PTE2: uart1_cts_b_pte2 { 1371 nxp,kinetis-port-pins = < 2 3 >; 1372 }; 1373 SDHC0_DCLK_PTE2: sdhc0_dclk_pte2 { 1374 nxp,kinetis-port-pins = < 2 4 >; 1375 }; 1376 TRACE_D2_PTE2: trace_d2_pte2 { 1377 nxp,kinetis-port-pins = < 2 5 >; 1378 }; 1379 ADC1_SE7a_PTE3: adc1_se7a_pte3 { 1380 nxp,kinetis-port-pins = < 3 0 >; 1381 }; 1382 PTE3: GPIOE_PTE3: gpioe_pte3 { 1383 nxp,kinetis-port-pins = < 3 1 >; 1384 }; 1385 SPI1_SIN_PTE3: spi1_sin_pte3 { 1386 nxp,kinetis-port-pins = < 3 2 >; 1387 }; 1388 UART1_RTS_b_PTE3: uart1_rts_b_pte3 { 1389 nxp,kinetis-port-pins = < 3 3 >; 1390 }; 1391 SDHC0_CMD_PTE3: sdhc0_cmd_pte3 { 1392 nxp,kinetis-port-pins = < 3 4 >; 1393 }; 1394 TRACE_D1_PTE3: trace_d1_pte3 { 1395 nxp,kinetis-port-pins = < 3 5 >; 1396 }; 1397 SPI1_SOUT_PTE3: spi1_sout_pte3 { 1398 nxp,kinetis-port-pins = < 3 7 >; 1399 }; 1400 PTE4: GPIOE_PTE4: LLWU_P2_PTE4: gpioe_pte4 { 1401 nxp,kinetis-port-pins = < 4 1 >; 1402 }; 1403 SPI1_PCS0_PTE4: spi1_pcs0_pte4 { 1404 nxp,kinetis-port-pins = < 4 2 >; 1405 }; 1406 UART3_TX_PTE4: uart3_tx_pte4 { 1407 nxp,kinetis-port-pins = < 4 3 >; 1408 }; 1409 SDHC0_D3_PTE4: sdhc0_d3_pte4 { 1410 nxp,kinetis-port-pins = < 4 4 >; 1411 }; 1412 TRACE_D0_PTE4: trace_d0_pte4 { 1413 nxp,kinetis-port-pins = < 4 5 >; 1414 }; 1415 PTE5: GPIOE_PTE5: gpioe_pte5 { 1416 nxp,kinetis-port-pins = < 5 1 >; 1417 }; 1418 SPI1_PCS2_PTE5: spi1_pcs2_pte5 { 1419 nxp,kinetis-port-pins = < 5 2 >; 1420 }; 1421 UART3_RX_PTE5: uart3_rx_pte5 { 1422 nxp,kinetis-port-pins = < 5 3 >; 1423 }; 1424 SDHC0_D2_PTE5: sdhc0_d2_pte5 { 1425 nxp,kinetis-port-pins = < 5 4 >; 1426 }; 1427 FTM3_CH0_PTE5: ftm3_ch0_pte5 { 1428 nxp,kinetis-port-pins = < 5 6 >; 1429 }; 1430 PTE6: GPIOE_PTE6: LLWU_P16_PTE6: gpioe_pte6 { 1431 nxp,kinetis-port-pins = < 6 1 >; 1432 }; 1433 SPI1_PCS3_PTE6: spi1_pcs3_pte6 { 1434 nxp,kinetis-port-pins = < 6 2 >; 1435 }; 1436 UART3_CTS_b_PTE6: uart3_cts_b_pte6 { 1437 nxp,kinetis-port-pins = < 6 3 >; 1438 }; 1439 I2S0_MCLK_PTE6: i2s0_mclk_pte6 { 1440 nxp,kinetis-port-pins = < 6 4 >; 1441 }; 1442 FTM3_CH1_PTE6: ftm3_ch1_pte6 { 1443 nxp,kinetis-port-pins = < 6 6 >; 1444 }; 1445 USB0_SOF_OUT_PTE6: usb0_sof_out_pte6 { 1446 nxp,kinetis-port-pins = < 6 7 >; 1447 }; 1448 PTE7: GPIOE_PTE7: gpioe_pte7 { 1449 nxp,kinetis-port-pins = < 7 1 >; 1450 }; 1451 UART3_RTS_b_PTE7: uart3_rts_b_pte7 { 1452 nxp,kinetis-port-pins = < 7 3 >; 1453 }; 1454 I2S0_RXD0_PTE7: i2s0_rxd0_pte7 { 1455 nxp,kinetis-port-pins = < 7 4 >; 1456 }; 1457 FTM3_CH2_PTE7: ftm3_ch2_pte7 { 1458 nxp,kinetis-port-pins = < 7 6 >; 1459 }; 1460 PTE8: GPIOE_PTE8: gpioe_pte8 { 1461 nxp,kinetis-port-pins = < 8 1 >; 1462 }; 1463 I2S0_RXD1_PTE8: i2s0_rxd1_pte8 { 1464 nxp,kinetis-port-pins = < 8 2 >; 1465 }; 1466 I2S0_RX_FS_PTE8: i2s0_rx_fs_pte8 { 1467 nxp,kinetis-port-pins = < 8 4 >; 1468 }; 1469 LPUART0_TX_PTE8: lpuart0_tx_pte8 { 1470 nxp,kinetis-port-pins = < 8 5 >; 1471 }; 1472 FTM3_CH3_PTE8: ftm3_ch3_pte8 { 1473 nxp,kinetis-port-pins = < 8 6 >; 1474 }; 1475 PTE9: GPIOE_PTE9: LLWU_P17_PTE9: gpioe_pte9 { 1476 nxp,kinetis-port-pins = < 9 1 >; 1477 }; 1478 I2S0_TXD1_PTE9: i2s0_txd1_pte9 { 1479 nxp,kinetis-port-pins = < 9 2 >; 1480 }; 1481 I2S0_RX_BCLK_PTE9: i2s0_rx_bclk_pte9 { 1482 nxp,kinetis-port-pins = < 9 4 >; 1483 }; 1484 LPUART0_RX_PTE9: lpuart0_rx_pte9 { 1485 nxp,kinetis-port-pins = < 9 5 >; 1486 }; 1487 FTM3_CH4_PTE9: ftm3_ch4_pte9 { 1488 nxp,kinetis-port-pins = < 9 6 >; 1489 }; 1490 PTE10: GPIOE_PTE10: LLWU_P18_PTE10: gpioe_pte10 { 1491 nxp,kinetis-port-pins = < 10 1 >; 1492 }; 1493 I2C3_SDA_PTE10: i2c3_sda_pte10 { 1494 nxp,kinetis-port-pins = < 10 2 >; 1495 }; 1496 I2S0_TXD0_PTE10: i2s0_txd0_pte10 { 1497 nxp,kinetis-port-pins = < 10 4 >; 1498 }; 1499 LPUART0_CTS_b_PTE10: lpuart0_cts_b_pte10 { 1500 nxp,kinetis-port-pins = < 10 5 >; 1501 }; 1502 FTM3_CH5_PTE10: ftm3_ch5_pte10 { 1503 nxp,kinetis-port-pins = < 10 6 >; 1504 }; 1505 USB1_ID_PTE10: usb1_id_pte10 { 1506 nxp,kinetis-port-pins = < 10 7 >; 1507 }; 1508 PTE11: GPIOE_PTE11: gpioe_pte11 { 1509 nxp,kinetis-port-pins = < 11 1 >; 1510 }; 1511 I2C3_SCL_PTE11: i2c3_scl_pte11 { 1512 nxp,kinetis-port-pins = < 11 2 >; 1513 }; 1514 I2S0_TX_FS_PTE11: i2s0_tx_fs_pte11 { 1515 nxp,kinetis-port-pins = < 11 4 >; 1516 }; 1517 LPUART0_RTS_b_PTE11: lpuart0_rts_b_pte11 { 1518 nxp,kinetis-port-pins = < 11 5 >; 1519 }; 1520 FTM3_CH6_PTE11: ftm3_ch6_pte11 { 1521 nxp,kinetis-port-pins = < 11 6 >; 1522 }; 1523 PTE12: GPIOE_PTE12: gpioe_pte12 { 1524 nxp,kinetis-port-pins = < 12 1 >; 1525 }; 1526 I2S0_TX_BCLK_PTE12: i2s0_tx_bclk_pte12 { 1527 nxp,kinetis-port-pins = < 12 4 >; 1528 }; 1529 FTM3_CH7_PTE12: ftm3_ch7_pte12 { 1530 nxp,kinetis-port-pins = < 12 6 >; 1531 }; 1532 ADC0_SE17_PTE24: adc0_se17_pte24 { 1533 nxp,kinetis-port-pins = < 24 0 >; 1534 }; 1535 PTE24: GPIOE_PTE24: gpioe_pte24 { 1536 nxp,kinetis-port-pins = < 24 1 >; 1537 }; 1538 CAN1_TX_PTE24: can1_tx_pte24 { 1539 nxp,kinetis-port-pins = < 24 2 >; 1540 }; 1541 UART4_TX_PTE24: uart4_tx_pte24 { 1542 nxp,kinetis-port-pins = < 24 3 >; 1543 }; 1544 I2C0_SCL_PTE24: i2c0_scl_pte24 { 1545 nxp,kinetis-port-pins = < 24 5 >; 1546 }; 1547 EWM_OUT_b_PTE24: ewm_out_b_pte24 { 1548 nxp,kinetis-port-pins = < 24 6 >; 1549 }; 1550 ADC0_SE18_PTE25: adc0_se18_pte25 { 1551 nxp,kinetis-port-pins = < 25 0 >; 1552 }; 1553 PTE25: GPIOE_PTE25: LLWU_P21_PTE25: gpioe_pte25 { 1554 nxp,kinetis-port-pins = < 25 1 >; 1555 }; 1556 CAN1_RX_PTE25: can1_rx_pte25 { 1557 nxp,kinetis-port-pins = < 25 2 >; 1558 }; 1559 UART4_RX_PTE25: uart4_rx_pte25 { 1560 nxp,kinetis-port-pins = < 25 3 >; 1561 }; 1562 I2C0_SDA_PTE25: i2c0_sda_pte25 { 1563 nxp,kinetis-port-pins = < 25 5 >; 1564 }; 1565 EWM_IN_PTE25: ewm_in_pte25 { 1566 nxp,kinetis-port-pins = < 25 6 >; 1567 }; 1568 PTE26: GPIOE_PTE26: gpioe_pte26 { 1569 nxp,kinetis-port-pins = < 26 1 >; 1570 }; 1571 ENET_1588_CLKIN_PTE26: enet_1588_clkin_pte26 { 1572 nxp,kinetis-port-pins = < 26 2 >; 1573 }; 1574 UART4_CTS_b_PTE26: uart4_cts_b_pte26 { 1575 nxp,kinetis-port-pins = < 26 3 >; 1576 }; 1577 RTC_CLKOUT_PTE26: rtc_clkout_pte26 { 1578 nxp,kinetis-port-pins = < 26 6 >; 1579 }; 1580 USB0_CLKIN_PTE26: usb0_clkin_pte26 { 1581 nxp,kinetis-port-pins = < 26 7 >; 1582 }; 1583 PTE27: GPIOE_PTE27: gpioe_pte27 { 1584 nxp,kinetis-port-pins = < 27 1 >; 1585 }; 1586 UART4_RTS_b_PTE27: uart4_rts_b_pte27 { 1587 nxp,kinetis-port-pins = < 27 3 >; 1588 }; 1589 PTE28: GPIOE_PTE28: gpioe_pte28 { 1590 nxp,kinetis-port-pins = < 28 1 >; 1591 }; 1592}; 1593 1594
