1/*
2 * NOTE: Autogenerated file by kinetis_signal2dts.py
3 *       for MK66FN2M0VLQ18/signal_configuration.xml
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8&porta {
9	TSI0_CH1_PTA0: tsi0_ch1_pta0 {
10		/* < PIN PCR[MUX] > */
11		nxp,kinetis-port-pins = < 0 0 >;
12	};
13	PTA0: GPIOA_PTA0: gpioa_pta0 {
14		/* < PIN PCR[MUX] > */
15		nxp,kinetis-port-pins = < 0 1 >;
16	};
17	UART0_CTS_b_PTA0: uart0_cts_b_pta0 {
18		/* < PIN PCR[MUX] > */
19		nxp,kinetis-port-pins = < 0 2 >;
20	};
21	FTM0_CH5_PTA0: ftm0_ch5_pta0 {
22		/* < PIN PCR[MUX] > */
23		nxp,kinetis-port-pins = < 0 3 >;
24	};
25	LPUART0_CTS_b_PTA0: lpuart0_cts_b_pta0 {
26		/* < PIN PCR[MUX] > */
27		nxp,kinetis-port-pins = < 0 5 >;
28	};
29	JTAG_TCLK_PTA0: jtag_tclk_pta0 {
30		/* < PIN PCR[MUX] > */
31		nxp,kinetis-port-pins = < 0 7 >;
32	};
33	TSI0_CH2_PTA1: tsi0_ch2_pta1 {
34		/* < PIN PCR[MUX] > */
35		nxp,kinetis-port-pins = < 1 0 >;
36	};
37	PTA1: GPIOA_PTA1: gpioa_pta1 {
38		/* < PIN PCR[MUX] > */
39		nxp,kinetis-port-pins = < 1 1 >;
40	};
41	UART0_RX_PTA1: uart0_rx_pta1 {
42		/* < PIN PCR[MUX] > */
43		nxp,kinetis-port-pins = < 1 2 >;
44	};
45	FTM0_CH6_PTA1: ftm0_ch6_pta1 {
46		/* < PIN PCR[MUX] > */
47		nxp,kinetis-port-pins = < 1 3 >;
48	};
49	I2C3_SDA_PTA1: i2c3_sda_pta1 {
50		/* < PIN PCR[MUX] > */
51		nxp,kinetis-port-pins = < 1 4 >;
52	};
53	LPUART0_RX_PTA1: lpuart0_rx_pta1 {
54		/* < PIN PCR[MUX] > */
55		nxp,kinetis-port-pins = < 1 5 >;
56	};
57	JTAG_TDI_PTA1: jtag_tdi_pta1 {
58		/* < PIN PCR[MUX] > */
59		nxp,kinetis-port-pins = < 1 7 >;
60	};
61	TSI0_CH3_PTA2: tsi0_ch3_pta2 {
62		/* < PIN PCR[MUX] > */
63		nxp,kinetis-port-pins = < 2 0 >;
64	};
65	PTA2: GPIOA_PTA2: gpioa_pta2 {
66		/* < PIN PCR[MUX] > */
67		nxp,kinetis-port-pins = < 2 1 >;
68	};
69	UART0_TX_PTA2: uart0_tx_pta2 {
70		/* < PIN PCR[MUX] > */
71		nxp,kinetis-port-pins = < 2 2 >;
72	};
73	FTM0_CH7_PTA2: ftm0_ch7_pta2 {
74		/* < PIN PCR[MUX] > */
75		nxp,kinetis-port-pins = < 2 3 >;
76	};
77	I2C3_SCL_PTA2: i2c3_scl_pta2 {
78		/* < PIN PCR[MUX] > */
79		nxp,kinetis-port-pins = < 2 4 >;
80	};
81	LPUART0_TX_PTA2: lpuart0_tx_pta2 {
82		/* < PIN PCR[MUX] > */
83		nxp,kinetis-port-pins = < 2 5 >;
84	};
85	JTAG_TDO_PTA2: jtag_tdo_pta2 {
86		/* < PIN PCR[MUX] > */
87		nxp,kinetis-port-pins = < 2 7 >;
88	};
89	TRACE_SWO_PTA2: trace_swo_pta2 {
90		/* < PIN PCR[MUX] > */
91		nxp,kinetis-port-pins = < 2 7 >;
92	};
93	TSI0_CH4_PTA3: tsi0_ch4_pta3 {
94		/* < PIN PCR[MUX] > */
95		nxp,kinetis-port-pins = < 3 0 >;
96	};
97	PTA3: GPIOA_PTA3: gpioa_pta3 {
98		/* < PIN PCR[MUX] > */
99		nxp,kinetis-port-pins = < 3 1 >;
100	};
101	UART0_RTS_b_PTA3: uart0_rts_b_pta3 {
102		/* < PIN PCR[MUX] > */
103		nxp,kinetis-port-pins = < 3 2 >;
104	};
105	FTM0_CH0_PTA3: ftm0_ch0_pta3 {
106		/* < PIN PCR[MUX] > */
107		nxp,kinetis-port-pins = < 3 3 >;
108	};
109	LPUART0_RTS_b_PTA3: lpuart0_rts_b_pta3 {
110		/* < PIN PCR[MUX] > */
111		nxp,kinetis-port-pins = < 3 5 >;
112	};
113	JTAG_TMS_PTA3: jtag_tms_pta3 {
114		/* < PIN PCR[MUX] > */
115		nxp,kinetis-port-pins = < 3 7 >;
116	};
117	TSI0_CH5_PTA4: tsi0_ch5_pta4 {
118		/* < PIN PCR[MUX] > */
119		nxp,kinetis-port-pins = < 4 0 >;
120	};
121	PTA4: GPIOA_PTA4: gpioa_pta4 {
122		/* < PIN PCR[MUX] > */
123		nxp,kinetis-port-pins = < 4 1 >;
124	};
125	LLWU_P3_PTA4: llwu_p3_pta4 {
126		/* < PIN PCR[MUX] > */
127		nxp,kinetis-port-pins = < 4 1 >;
128	};
129	FTM0_CH1_PTA4: ftm0_ch1_pta4 {
130		/* < PIN PCR[MUX] > */
131		nxp,kinetis-port-pins = < 4 3 >;
132	};
133	NMI_b_PTA4: nmi_b_pta4 {
134		/* < PIN PCR[MUX] > */
135		nxp,kinetis-port-pins = < 4 7 >;
136	};
137	PTA5: GPIOA_PTA5: gpioa_pta5 {
138		/* < PIN PCR[MUX] > */
139		nxp,kinetis-port-pins = < 5 1 >;
140	};
141	USB0_CLKIN_PTA5: usb0_clkin_pta5 {
142		/* < PIN PCR[MUX] > */
143		nxp,kinetis-port-pins = < 5 2 >;
144	};
145	FTM0_CH2_PTA5: ftm0_ch2_pta5 {
146		/* < PIN PCR[MUX] > */
147		nxp,kinetis-port-pins = < 5 3 >;
148	};
149	RMII0_RXER_PTA5: rmii0_rxer_pta5 {
150		/* < PIN PCR[MUX] > */
151		nxp,kinetis-port-pins = < 5 4 >;
152	};
153	MII0_RXER_PTA5: mii0_rxer_pta5 {
154		/* < PIN PCR[MUX] > */
155		nxp,kinetis-port-pins = < 5 4 >;
156	};
157	CMP2_OUT_PTA5: cmp2_out_pta5 {
158		/* < PIN PCR[MUX] > */
159		nxp,kinetis-port-pins = < 5 5 >;
160	};
161	I2S0_TX_BCLK_PTA5: i2s0_tx_bclk_pta5 {
162		/* < PIN PCR[MUX] > */
163		nxp,kinetis-port-pins = < 5 6 >;
164	};
165	JTAG_TRST_b_PTA5: jtag_trst_b_pta5 {
166		/* < PIN PCR[MUX] > */
167		nxp,kinetis-port-pins = < 5 7 >;
168	};
169	PTA6: GPIOA_PTA6: gpioa_pta6 {
170		/* < PIN PCR[MUX] > */
171		nxp,kinetis-port-pins = < 6 1 >;
172	};
173	FTM0_CH3_PTA6: ftm0_ch3_pta6 {
174		/* < PIN PCR[MUX] > */
175		nxp,kinetis-port-pins = < 6 3 >;
176	};
177	CLKOUT_PTA6: clkout_pta6 {
178		/* < PIN PCR[MUX] > */
179		nxp,kinetis-port-pins = < 6 5 >;
180	};
181	TRACE_CLKOUT_PTA6: trace_clkout_pta6 {
182		/* < PIN PCR[MUX] > */
183		nxp,kinetis-port-pins = < 6 7 >;
184	};
185	ADC0_SE10_PTA7: adc0_se10_pta7 {
186		/* < PIN PCR[MUX] > */
187		nxp,kinetis-port-pins = < 7 0 >;
188	};
189	PTA7: GPIOA_PTA7: gpioa_pta7 {
190		/* < PIN PCR[MUX] > */
191		nxp,kinetis-port-pins = < 7 1 >;
192	};
193	FTM0_CH4_PTA7: ftm0_ch4_pta7 {
194		/* < PIN PCR[MUX] > */
195		nxp,kinetis-port-pins = < 7 3 >;
196	};
197	RMII0_MDIO_PTA7: rmii0_mdio_pta7 {
198		/* < PIN PCR[MUX] > */
199		nxp,kinetis-port-pins = < 7 5 >;
200	};
201	MII0_MDIO_PTA7: mii0_mdio_pta7 {
202		/* < PIN PCR[MUX] > */
203		nxp,kinetis-port-pins = < 7 5 >;
204	};
205	TRACE_D3_PTA7: trace_d3_pta7 {
206		/* < PIN PCR[MUX] > */
207		nxp,kinetis-port-pins = < 7 7 >;
208	};
209	ADC0_SE11_PTA8: adc0_se11_pta8 {
210		/* < PIN PCR[MUX] > */
211		nxp,kinetis-port-pins = < 8 0 >;
212	};
213	PTA8: GPIOA_PTA8: gpioa_pta8 {
214		/* < PIN PCR[MUX] > */
215		nxp,kinetis-port-pins = < 8 1 >;
216	};
217	FTM1_CH0_PTA8: ftm1_ch0_pta8 {
218		/* < PIN PCR[MUX] > */
219		nxp,kinetis-port-pins = < 8 3 >;
220	};
221	RMII0_MDC_PTA8: rmii0_mdc_pta8 {
222		/* < PIN PCR[MUX] > */
223		nxp,kinetis-port-pins = < 8 5 >;
224	};
225	MII0_MDC_PTA8: mii0_mdc_pta8 {
226		/* < PIN PCR[MUX] > */
227		nxp,kinetis-port-pins = < 8 5 >;
228	};
229	FTM1_QD_PHA_PTA8: ftm1_qd_pha_pta8 {
230		/* < PIN PCR[MUX] > */
231		nxp,kinetis-port-pins = < 8 6 >;
232	};
233	TPM1_CH0_PTA8: tpm1_ch0_pta8 {
234		/* < PIN PCR[MUX] > */
235		nxp,kinetis-port-pins = < 8 6 >;
236	};
237	TRACE_D2_PTA8: trace_d2_pta8 {
238		/* < PIN PCR[MUX] > */
239		nxp,kinetis-port-pins = < 8 7 >;
240	};
241	PTA9: GPIOA_PTA9: gpioa_pta9 {
242		/* < PIN PCR[MUX] > */
243		nxp,kinetis-port-pins = < 9 1 >;
244	};
245	FTM1_CH1_PTA9: ftm1_ch1_pta9 {
246		/* < PIN PCR[MUX] > */
247		nxp,kinetis-port-pins = < 9 3 >;
248	};
249	MII0_RXD3_PTA9: mii0_rxd3_pta9 {
250		/* < PIN PCR[MUX] > */
251		nxp,kinetis-port-pins = < 9 4 >;
252	};
253	FTM1_QD_PHB_PTA9: ftm1_qd_phb_pta9 {
254		/* < PIN PCR[MUX] > */
255		nxp,kinetis-port-pins = < 9 6 >;
256	};
257	TPM1_CH1_PTA9: tpm1_ch1_pta9 {
258		/* < PIN PCR[MUX] > */
259		nxp,kinetis-port-pins = < 9 6 >;
260	};
261	TRACE_D1_PTA9: trace_d1_pta9 {
262		/* < PIN PCR[MUX] > */
263		nxp,kinetis-port-pins = < 9 7 >;
264	};
265	PTA10: GPIOA_PTA10: gpioa_pta10 {
266		/* < PIN PCR[MUX] > */
267		nxp,kinetis-port-pins = < 10 1 >;
268	};
269	LLWU_P22_PTA10: llwu_p22_pta10 {
270		/* < PIN PCR[MUX] > */
271		nxp,kinetis-port-pins = < 10 1 >;
272	};
273	FTM2_CH0_PTA10: ftm2_ch0_pta10 {
274		/* < PIN PCR[MUX] > */
275		nxp,kinetis-port-pins = < 10 3 >;
276	};
277	MII0_RXD2_PTA10: mii0_rxd2_pta10 {
278		/* < PIN PCR[MUX] > */
279		nxp,kinetis-port-pins = < 10 4 >;
280	};
281	FTM2_QD_PHA_PTA10: ftm2_qd_pha_pta10 {
282		/* < PIN PCR[MUX] > */
283		nxp,kinetis-port-pins = < 10 6 >;
284	};
285	TPM2_CH0_PTA10: tpm2_ch0_pta10 {
286		/* < PIN PCR[MUX] > */
287		nxp,kinetis-port-pins = < 10 6 >;
288	};
289	TRACE_D0_PTA10: trace_d0_pta10 {
290		/* < PIN PCR[MUX] > */
291		nxp,kinetis-port-pins = < 10 7 >;
292	};
293	PTA11: GPIOA_PTA11: gpioa_pta11 {
294		/* < PIN PCR[MUX] > */
295		nxp,kinetis-port-pins = < 11 1 >;
296	};
297	LLWU_P23_PTA11: llwu_p23_pta11 {
298		/* < PIN PCR[MUX] > */
299		nxp,kinetis-port-pins = < 11 1 >;
300	};
301	FTM2_CH1_PTA11: ftm2_ch1_pta11 {
302		/* < PIN PCR[MUX] > */
303		nxp,kinetis-port-pins = < 11 3 >;
304	};
305	MII0_RXCLK_PTA11: mii0_rxclk_pta11 {
306		/* < PIN PCR[MUX] > */
307		nxp,kinetis-port-pins = < 11 4 >;
308	};
309	I2C2_SDA_PTA11: i2c2_sda_pta11 {
310		/* < PIN PCR[MUX] > */
311		nxp,kinetis-port-pins = < 11 5 >;
312	};
313	FTM2_QD_PHB_PTA11: ftm2_qd_phb_pta11 {
314		/* < PIN PCR[MUX] > */
315		nxp,kinetis-port-pins = < 11 6 >;
316	};
317	TPM2_CH1_PTA11: tpm2_ch1_pta11 {
318		/* < PIN PCR[MUX] > */
319		nxp,kinetis-port-pins = < 11 6 >;
320	};
321	CMP2_IN0_PTA12: cmp2_in0_pta12 {
322		/* < PIN PCR[MUX] > */
323		nxp,kinetis-port-pins = < 12 0 >;
324	};
325	PTA12: GPIOA_PTA12: gpioa_pta12 {
326		/* < PIN PCR[MUX] > */
327		nxp,kinetis-port-pins = < 12 1 >;
328	};
329	CAN0_TX_PTA12: can0_tx_pta12 {
330		/* < PIN PCR[MUX] > */
331		nxp,kinetis-port-pins = < 12 2 >;
332	};
333	FTM1_CH0_PTA12: ftm1_ch0_pta12 {
334		/* < PIN PCR[MUX] > */
335		nxp,kinetis-port-pins = < 12 3 >;
336	};
337	RMII0_RXD1_PTA12: rmii0_rxd1_pta12 {
338		/* < PIN PCR[MUX] > */
339		nxp,kinetis-port-pins = < 12 4 >;
340	};
341	MII0_RXD1_PTA12: mii0_rxd1_pta12 {
342		/* < PIN PCR[MUX] > */
343		nxp,kinetis-port-pins = < 12 4 >;
344	};
345	I2C2_SCL_PTA12: i2c2_scl_pta12 {
346		/* < PIN PCR[MUX] > */
347		nxp,kinetis-port-pins = < 12 5 >;
348	};
349	I2S0_TXD0_PTA12: i2s0_txd0_pta12 {
350		/* < PIN PCR[MUX] > */
351		nxp,kinetis-port-pins = < 12 6 >;
352	};
353	FTM1_QD_PHA_PTA12: ftm1_qd_pha_pta12 {
354		/* < PIN PCR[MUX] > */
355		nxp,kinetis-port-pins = < 12 7 >;
356	};
357	TPM1_CH0_PTA12: tpm1_ch0_pta12 {
358		/* < PIN PCR[MUX] > */
359		nxp,kinetis-port-pins = < 12 7 >;
360	};
361	CMP2_IN1_PTA13: cmp2_in1_pta13 {
362		/* < PIN PCR[MUX] > */
363		nxp,kinetis-port-pins = < 13 0 >;
364	};
365	PTA13: GPIOA_PTA13: gpioa_pta13 {
366		/* < PIN PCR[MUX] > */
367		nxp,kinetis-port-pins = < 13 1 >;
368	};
369	LLWU_P4_PTA13: llwu_p4_pta13 {
370		/* < PIN PCR[MUX] > */
371		nxp,kinetis-port-pins = < 13 1 >;
372	};
373	CAN0_RX_PTA13: can0_rx_pta13 {
374		/* < PIN PCR[MUX] > */
375		nxp,kinetis-port-pins = < 13 2 >;
376	};
377	FTM1_CH1_PTA13: ftm1_ch1_pta13 {
378		/* < PIN PCR[MUX] > */
379		nxp,kinetis-port-pins = < 13 3 >;
380	};
381	RMII0_RXD0_PTA13: rmii0_rxd0_pta13 {
382		/* < PIN PCR[MUX] > */
383		nxp,kinetis-port-pins = < 13 4 >;
384	};
385	MII0_RXD0_PTA13: mii0_rxd0_pta13 {
386		/* < PIN PCR[MUX] > */
387		nxp,kinetis-port-pins = < 13 4 >;
388	};
389	I2C2_SDA_PTA13: i2c2_sda_pta13 {
390		/* < PIN PCR[MUX] > */
391		nxp,kinetis-port-pins = < 13 5 >;
392	};
393	I2S0_TX_FS_PTA13: i2s0_tx_fs_pta13 {
394		/* < PIN PCR[MUX] > */
395		nxp,kinetis-port-pins = < 13 6 >;
396	};
397	FTM1_QD_PHB_PTA13: ftm1_qd_phb_pta13 {
398		/* < PIN PCR[MUX] > */
399		nxp,kinetis-port-pins = < 13 7 >;
400	};
401	TPM1_CH1_PTA13: tpm1_ch1_pta13 {
402		/* < PIN PCR[MUX] > */
403		nxp,kinetis-port-pins = < 13 7 >;
404	};
405	PTA14: GPIOA_PTA14: gpioa_pta14 {
406		/* < PIN PCR[MUX] > */
407		nxp,kinetis-port-pins = < 14 1 >;
408	};
409	SPI0_PCS0_PTA14: spi0_pcs0_pta14 {
410		/* < PIN PCR[MUX] > */
411		nxp,kinetis-port-pins = < 14 2 >;
412	};
413	UART0_TX_PTA14: uart0_tx_pta14 {
414		/* < PIN PCR[MUX] > */
415		nxp,kinetis-port-pins = < 14 3 >;
416	};
417	RMII0_CRS_DV_PTA14: rmii0_crs_dv_pta14 {
418		/* < PIN PCR[MUX] > */
419		nxp,kinetis-port-pins = < 14 4 >;
420	};
421	MII0_RXDV_PTA14: mii0_rxdv_pta14 {
422		/* < PIN PCR[MUX] > */
423		nxp,kinetis-port-pins = < 14 4 >;
424	};
425	I2C2_SCL_PTA14: i2c2_scl_pta14 {
426		/* < PIN PCR[MUX] > */
427		nxp,kinetis-port-pins = < 14 5 >;
428	};
429	I2S0_RX_BCLK_PTA14: i2s0_rx_bclk_pta14 {
430		/* < PIN PCR[MUX] > */
431		nxp,kinetis-port-pins = < 14 6 >;
432	};
433	I2S0_TXD1_PTA14: i2s0_txd1_pta14 {
434		/* < PIN PCR[MUX] > */
435		nxp,kinetis-port-pins = < 14 7 >;
436	};
437	CMP3_IN1_PTA15: cmp3_in1_pta15 {
438		/* < PIN PCR[MUX] > */
439		nxp,kinetis-port-pins = < 15 0 >;
440	};
441	PTA15: GPIOA_PTA15: gpioa_pta15 {
442		/* < PIN PCR[MUX] > */
443		nxp,kinetis-port-pins = < 15 1 >;
444	};
445	SPI0_SCK_PTA15: spi0_sck_pta15 {
446		/* < PIN PCR[MUX] > */
447		nxp,kinetis-port-pins = < 15 2 >;
448	};
449	UART0_RX_PTA15: uart0_rx_pta15 {
450		/* < PIN PCR[MUX] > */
451		nxp,kinetis-port-pins = < 15 3 >;
452	};
453	RMII0_TXEN_PTA15: rmii0_txen_pta15 {
454		/* < PIN PCR[MUX] > */
455		nxp,kinetis-port-pins = < 15 4 >;
456	};
457	MII0_TXEN_PTA15: mii0_txen_pta15 {
458		/* < PIN PCR[MUX] > */
459		nxp,kinetis-port-pins = < 15 4 >;
460	};
461	I2S0_RXD0_PTA15: i2s0_rxd0_pta15 {
462		/* < PIN PCR[MUX] > */
463		nxp,kinetis-port-pins = < 15 6 >;
464	};
465	CMP3_IN2_PTA16: cmp3_in2_pta16 {
466		/* < PIN PCR[MUX] > */
467		nxp,kinetis-port-pins = < 16 0 >;
468	};
469	PTA16: GPIOA_PTA16: gpioa_pta16 {
470		/* < PIN PCR[MUX] > */
471		nxp,kinetis-port-pins = < 16 1 >;
472	};
473	SPI0_SOUT_PTA16: spi0_sout_pta16 {
474		/* < PIN PCR[MUX] > */
475		nxp,kinetis-port-pins = < 16 2 >;
476	};
477	UART0_CTS_b_PTA16: uart0_cts_b_pta16 {
478		/* < PIN PCR[MUX] > */
479		nxp,kinetis-port-pins = < 16 3 >;
480	};
481	RMII0_TXD0_PTA16: rmii0_txd0_pta16 {
482		/* < PIN PCR[MUX] > */
483		nxp,kinetis-port-pins = < 16 4 >;
484	};
485	MII0_TXD0_PTA16: mii0_txd0_pta16 {
486		/* < PIN PCR[MUX] > */
487		nxp,kinetis-port-pins = < 16 4 >;
488	};
489	I2S0_RX_FS_PTA16: i2s0_rx_fs_pta16 {
490		/* < PIN PCR[MUX] > */
491		nxp,kinetis-port-pins = < 16 6 >;
492	};
493	I2S0_RXD1_PTA16: i2s0_rxd1_pta16 {
494		/* < PIN PCR[MUX] > */
495		nxp,kinetis-port-pins = < 16 7 >;
496	};
497	ADC1_SE17_PTA17: adc1_se17_pta17 {
498		/* < PIN PCR[MUX] > */
499		nxp,kinetis-port-pins = < 17 0 >;
500	};
501	PTA17: GPIOA_PTA17: gpioa_pta17 {
502		/* < PIN PCR[MUX] > */
503		nxp,kinetis-port-pins = < 17 1 >;
504	};
505	SPI0_SIN_PTA17: spi0_sin_pta17 {
506		/* < PIN PCR[MUX] > */
507		nxp,kinetis-port-pins = < 17 2 >;
508	};
509	UART0_RTS_b_PTA17: uart0_rts_b_pta17 {
510		/* < PIN PCR[MUX] > */
511		nxp,kinetis-port-pins = < 17 3 >;
512	};
513	RMII0_TXD1_PTA17: rmii0_txd1_pta17 {
514		/* < PIN PCR[MUX] > */
515		nxp,kinetis-port-pins = < 17 4 >;
516	};
517	MII0_TXD1_PTA17: mii0_txd1_pta17 {
518		/* < PIN PCR[MUX] > */
519		nxp,kinetis-port-pins = < 17 4 >;
520	};
521	I2S0_MCLK_PTA17: i2s0_mclk_pta17 {
522		/* < PIN PCR[MUX] > */
523		nxp,kinetis-port-pins = < 17 6 >;
524	};
525	EXTAL0_PTA18: extal0_pta18 {
526		/* < PIN PCR[MUX] > */
527		nxp,kinetis-port-pins = < 18 0 >;
528	};
529	PTA18: GPIOA_PTA18: gpioa_pta18 {
530		/* < PIN PCR[MUX] > */
531		nxp,kinetis-port-pins = < 18 1 >;
532	};
533	FTM0_FLT2_PTA18: ftm0_flt2_pta18 {
534		/* < PIN PCR[MUX] > */
535		nxp,kinetis-port-pins = < 18 3 >;
536	};
537	FTM_CLKIN0_PTA18: ftm_clkin0_pta18 {
538		/* < PIN PCR[MUX] > */
539		nxp,kinetis-port-pins = < 18 4 >;
540	};
541	TPM_CLKIN0_PTA18: tpm_clkin0_pta18 {
542		/* < PIN PCR[MUX] > */
543		nxp,kinetis-port-pins = < 18 7 >;
544	};
545	XTAL0_PTA19: xtal0_pta19 {
546		/* < PIN PCR[MUX] > */
547		nxp,kinetis-port-pins = < 19 0 >;
548	};
549	PTA19: GPIOA_PTA19: gpioa_pta19 {
550		/* < PIN PCR[MUX] > */
551		nxp,kinetis-port-pins = < 19 1 >;
552	};
553	FTM1_FLT0_PTA19: ftm1_flt0_pta19 {
554		/* < PIN PCR[MUX] > */
555		nxp,kinetis-port-pins = < 19 3 >;
556	};
557	FTM_CLKIN1_PTA19: ftm_clkin1_pta19 {
558		/* < PIN PCR[MUX] > */
559		nxp,kinetis-port-pins = < 19 4 >;
560	};
561	LPTMR0_ALT1_PTA19: lptmr0_alt1_pta19 {
562		/* < PIN PCR[MUX] > */
563		nxp,kinetis-port-pins = < 19 6 >;
564	};
565	TPM_CLKIN1_PTA19: tpm_clkin1_pta19 {
566		/* < PIN PCR[MUX] > */
567		nxp,kinetis-port-pins = < 19 7 >;
568	};
569	CMP3_IN4_PTA24: cmp3_in4_pta24 {
570		/* < PIN PCR[MUX] > */
571		nxp,kinetis-port-pins = < 24 0 >;
572	};
573	PTA24: GPIOA_PTA24: gpioa_pta24 {
574		/* < PIN PCR[MUX] > */
575		nxp,kinetis-port-pins = < 24 1 >;
576	};
577	MII0_TXD2_PTA24: mii0_txd2_pta24 {
578		/* < PIN PCR[MUX] > */
579		nxp,kinetis-port-pins = < 24 4 >;
580	};
581	CMP3_IN5_PTA25: cmp3_in5_pta25 {
582		/* < PIN PCR[MUX] > */
583		nxp,kinetis-port-pins = < 25 0 >;
584	};
585	PTA25: GPIOA_PTA25: gpioa_pta25 {
586		/* < PIN PCR[MUX] > */
587		nxp,kinetis-port-pins = < 25 1 >;
588	};
589	MII0_TXCLK_PTA25: mii0_txclk_pta25 {
590		/* < PIN PCR[MUX] > */
591		nxp,kinetis-port-pins = < 25 4 >;
592	};
593	PTA26: GPIOA_PTA26: gpioa_pta26 {
594		/* < PIN PCR[MUX] > */
595		nxp,kinetis-port-pins = < 26 1 >;
596	};
597	MII0_TXD3_PTA26: mii0_txd3_pta26 {
598		/* < PIN PCR[MUX] > */
599		nxp,kinetis-port-pins = < 26 4 >;
600	};
601	PTA27: GPIOA_PTA27: gpioa_pta27 {
602		/* < PIN PCR[MUX] > */
603		nxp,kinetis-port-pins = < 27 1 >;
604	};
605	MII0_CRS_PTA27: mii0_crs_pta27 {
606		/* < PIN PCR[MUX] > */
607		nxp,kinetis-port-pins = < 27 4 >;
608	};
609	PTA28: GPIOA_PTA28: gpioa_pta28 {
610		/* < PIN PCR[MUX] > */
611		nxp,kinetis-port-pins = < 28 1 >;
612	};
613	MII0_TXER_PTA28: mii0_txer_pta28 {
614		/* < PIN PCR[MUX] > */
615		nxp,kinetis-port-pins = < 28 4 >;
616	};
617	PTA29: GPIOA_PTA29: gpioa_pta29 {
618		/* < PIN PCR[MUX] > */
619		nxp,kinetis-port-pins = < 29 1 >;
620	};
621	MII0_COL_PTA29: mii0_col_pta29 {
622		/* < PIN PCR[MUX] > */
623		nxp,kinetis-port-pins = < 29 4 >;
624	};
625};
626
627&portb {
628	ADC0_SE8_PTB0: adc0_se8_ptb0 {
629		/* < PIN PCR[MUX] > */
630		nxp,kinetis-port-pins = < 0 0 >;
631	};
632	ADC1_SE8_PTB0: adc1_se8_ptb0 {
633		/* < PIN PCR[MUX] > */
634		nxp,kinetis-port-pins = < 0 0 >;
635	};
636	TSI0_CH0_PTB0: tsi0_ch0_ptb0 {
637		/* < PIN PCR[MUX] > */
638		nxp,kinetis-port-pins = < 0 0 >;
639	};
640	PTB0: GPIOB_PTB0: gpiob_ptb0 {
641		/* < PIN PCR[MUX] > */
642		nxp,kinetis-port-pins = < 0 1 >;
643	};
644	LLWU_P5_PTB0: llwu_p5_ptb0 {
645		/* < PIN PCR[MUX] > */
646		nxp,kinetis-port-pins = < 0 1 >;
647	};
648	I2C0_SCL_PTB0: i2c0_scl_ptb0 {
649		/* < PIN PCR[MUX] > */
650		nxp,kinetis-port-pins = < 0 2 >;
651	};
652	FTM1_CH0_PTB0: ftm1_ch0_ptb0 {
653		/* < PIN PCR[MUX] > */
654		nxp,kinetis-port-pins = < 0 3 >;
655	};
656	RMII0_MDIO_PTB0: rmii0_mdio_ptb0 {
657		/* < PIN PCR[MUX] > */
658		nxp,kinetis-port-pins = < 0 4 >;
659	};
660	MII0_MDIO_PTB0: mii0_mdio_ptb0 {
661		/* < PIN PCR[MUX] > */
662		nxp,kinetis-port-pins = < 0 4 >;
663	};
664	SDRAM_CAS_b_PTB0: sdram_cas_b_ptb0 {
665		/* < PIN PCR[MUX] > */
666		nxp,kinetis-port-pins = < 0 5 >;
667	};
668	FTM1_QD_PHA_PTB0: ftm1_qd_pha_ptb0 {
669		/* < PIN PCR[MUX] > */
670		nxp,kinetis-port-pins = < 0 6 >;
671	};
672	TPM1_CH0_PTB0: tpm1_ch0_ptb0 {
673		/* < PIN PCR[MUX] > */
674		nxp,kinetis-port-pins = < 0 6 >;
675	};
676	ADC0_SE9_PTB1: adc0_se9_ptb1 {
677		/* < PIN PCR[MUX] > */
678		nxp,kinetis-port-pins = < 1 0 >;
679	};
680	ADC1_SE9_PTB1: adc1_se9_ptb1 {
681		/* < PIN PCR[MUX] > */
682		nxp,kinetis-port-pins = < 1 0 >;
683	};
684	TSI0_CH6_PTB1: tsi0_ch6_ptb1 {
685		/* < PIN PCR[MUX] > */
686		nxp,kinetis-port-pins = < 1 0 >;
687	};
688	PTB1: GPIOB_PTB1: gpiob_ptb1 {
689		/* < PIN PCR[MUX] > */
690		nxp,kinetis-port-pins = < 1 1 >;
691	};
692	I2C0_SDA_PTB1: i2c0_sda_ptb1 {
693		/* < PIN PCR[MUX] > */
694		nxp,kinetis-port-pins = < 1 2 >;
695	};
696	FTM1_CH1_PTB1: ftm1_ch1_ptb1 {
697		/* < PIN PCR[MUX] > */
698		nxp,kinetis-port-pins = < 1 3 >;
699	};
700	RMII0_MDC_PTB1: rmii0_mdc_ptb1 {
701		/* < PIN PCR[MUX] > */
702		nxp,kinetis-port-pins = < 1 4 >;
703	};
704	MII0_MDC_PTB1: mii0_mdc_ptb1 {
705		/* < PIN PCR[MUX] > */
706		nxp,kinetis-port-pins = < 1 4 >;
707	};
708	SDRAM_RAS_b_PTB1: sdram_ras_b_ptb1 {
709		/* < PIN PCR[MUX] > */
710		nxp,kinetis-port-pins = < 1 5 >;
711	};
712	FTM1_QD_PHB_PTB1: ftm1_qd_phb_ptb1 {
713		/* < PIN PCR[MUX] > */
714		nxp,kinetis-port-pins = < 1 6 >;
715	};
716	TPM1_CH1_PTB1: tpm1_ch1_ptb1 {
717		/* < PIN PCR[MUX] > */
718		nxp,kinetis-port-pins = < 1 6 >;
719	};
720	ADC0_SE12_PTB2: adc0_se12_ptb2 {
721		/* < PIN PCR[MUX] > */
722		nxp,kinetis-port-pins = < 2 0 >;
723	};
724	TSI0_CH7_PTB2: tsi0_ch7_ptb2 {
725		/* < PIN PCR[MUX] > */
726		nxp,kinetis-port-pins = < 2 0 >;
727	};
728	PTB2: GPIOB_PTB2: gpiob_ptb2 {
729		/* < PIN PCR[MUX] > */
730		nxp,kinetis-port-pins = < 2 1 >;
731	};
732	I2C0_SCL_PTB2: i2c0_scl_ptb2 {
733		/* < PIN PCR[MUX] > */
734		nxp,kinetis-port-pins = < 2 2 >;
735	};
736	UART0_RTS_b_PTB2: uart0_rts_b_ptb2 {
737		/* < PIN PCR[MUX] > */
738		nxp,kinetis-port-pins = < 2 3 >;
739	};
740	ENET0_1588_TMR0_PTB2: enet0_1588_tmr0_ptb2 {
741		/* < PIN PCR[MUX] > */
742		nxp,kinetis-port-pins = < 2 4 >;
743	};
744	SDRAM_WE_PTB2: sdram_we_ptb2 {
745		/* < PIN PCR[MUX] > */
746		nxp,kinetis-port-pins = < 2 5 >;
747	};
748	FTM0_FLT3_PTB2: ftm0_flt3_ptb2 {
749		/* < PIN PCR[MUX] > */
750		nxp,kinetis-port-pins = < 2 6 >;
751	};
752	ADC0_SE13_PTB3: adc0_se13_ptb3 {
753		/* < PIN PCR[MUX] > */
754		nxp,kinetis-port-pins = < 3 0 >;
755	};
756	TSI0_CH8_PTB3: tsi0_ch8_ptb3 {
757		/* < PIN PCR[MUX] > */
758		nxp,kinetis-port-pins = < 3 0 >;
759	};
760	PTB3: GPIOB_PTB3: gpiob_ptb3 {
761		/* < PIN PCR[MUX] > */
762		nxp,kinetis-port-pins = < 3 1 >;
763	};
764	I2C0_SDA_PTB3: i2c0_sda_ptb3 {
765		/* < PIN PCR[MUX] > */
766		nxp,kinetis-port-pins = < 3 2 >;
767	};
768	UART0_CTS_b_PTB3: uart0_cts_b_ptb3 {
769		/* < PIN PCR[MUX] > */
770		nxp,kinetis-port-pins = < 3 3 >;
771	};
772	ENET0_1588_TMR1_PTB3: enet0_1588_tmr1_ptb3 {
773		/* < PIN PCR[MUX] > */
774		nxp,kinetis-port-pins = < 3 4 >;
775	};
776	SDRAM_CS0_b_PTB3: sdram_cs0_b_ptb3 {
777		/* < PIN PCR[MUX] > */
778		nxp,kinetis-port-pins = < 3 5 >;
779	};
780	FTM0_FLT0_PTB3: ftm0_flt0_ptb3 {
781		/* < PIN PCR[MUX] > */
782		nxp,kinetis-port-pins = < 3 6 >;
783	};
784	ADC1_SE10_PTB4: adc1_se10_ptb4 {
785		/* < PIN PCR[MUX] > */
786		nxp,kinetis-port-pins = < 4 0 >;
787	};
788	PTB4: GPIOB_PTB4: gpiob_ptb4 {
789		/* < PIN PCR[MUX] > */
790		nxp,kinetis-port-pins = < 4 1 >;
791	};
792	ENET0_1588_TMR2_PTB4: enet0_1588_tmr2_ptb4 {
793		/* < PIN PCR[MUX] > */
794		nxp,kinetis-port-pins = < 4 4 >;
795	};
796	SDRAM_CS1_b_PTB4: sdram_cs1_b_ptb4 {
797		/* < PIN PCR[MUX] > */
798		nxp,kinetis-port-pins = < 4 5 >;
799	};
800	FTM1_FLT0_PTB4: ftm1_flt0_ptb4 {
801		/* < PIN PCR[MUX] > */
802		nxp,kinetis-port-pins = < 4 6 >;
803	};
804	ADC1_SE11_PTB5: adc1_se11_ptb5 {
805		/* < PIN PCR[MUX] > */
806		nxp,kinetis-port-pins = < 5 0 >;
807	};
808	PTB5: GPIOB_PTB5: gpiob_ptb5 {
809		/* < PIN PCR[MUX] > */
810		nxp,kinetis-port-pins = < 5 1 >;
811	};
812	ENET0_1588_TMR3_PTB5: enet0_1588_tmr3_ptb5 {
813		/* < PIN PCR[MUX] > */
814		nxp,kinetis-port-pins = < 5 4 >;
815	};
816	FTM2_FLT0_PTB5: ftm2_flt0_ptb5 {
817		/* < PIN PCR[MUX] > */
818		nxp,kinetis-port-pins = < 5 6 >;
819	};
820	ADC1_SE12_PTB6: adc1_se12_ptb6 {
821		/* < PIN PCR[MUX] > */
822		nxp,kinetis-port-pins = < 6 0 >;
823	};
824	PTB6: GPIOB_PTB6: gpiob_ptb6 {
825		/* < PIN PCR[MUX] > */
826		nxp,kinetis-port-pins = < 6 1 >;
827	};
828	SDRAM_D23_PTB6: sdram_d23_ptb6 {
829		/* < PIN PCR[MUX] > */
830		nxp,kinetis-port-pins = < 6 5 >;
831	};
832	ADC1_SE13_PTB7: adc1_se13_ptb7 {
833		/* < PIN PCR[MUX] > */
834		nxp,kinetis-port-pins = < 7 0 >;
835	};
836	PTB7: GPIOB_PTB7: gpiob_ptb7 {
837		/* < PIN PCR[MUX] > */
838		nxp,kinetis-port-pins = < 7 1 >;
839	};
840	SDRAM_D22_PTB7: sdram_d22_ptb7 {
841		/* < PIN PCR[MUX] > */
842		nxp,kinetis-port-pins = < 7 5 >;
843	};
844	PTB8: GPIOB_PTB8: gpiob_ptb8 {
845		/* < PIN PCR[MUX] > */
846		nxp,kinetis-port-pins = < 8 1 >;
847	};
848	UART3_RTS_b_PTB8: uart3_rts_b_ptb8 {
849		/* < PIN PCR[MUX] > */
850		nxp,kinetis-port-pins = < 8 3 >;
851	};
852	SDRAM_D21_PTB8: sdram_d21_ptb8 {
853		/* < PIN PCR[MUX] > */
854		nxp,kinetis-port-pins = < 8 5 >;
855	};
856	PTB9: GPIOB_PTB9: gpiob_ptb9 {
857		/* < PIN PCR[MUX] > */
858		nxp,kinetis-port-pins = < 9 1 >;
859	};
860	SPI1_PCS1_PTB9: spi1_pcs1_ptb9 {
861		/* < PIN PCR[MUX] > */
862		nxp,kinetis-port-pins = < 9 2 >;
863	};
864	UART3_CTS_b_PTB9: uart3_cts_b_ptb9 {
865		/* < PIN PCR[MUX] > */
866		nxp,kinetis-port-pins = < 9 3 >;
867	};
868	SDRAM_D20_PTB9: sdram_d20_ptb9 {
869		/* < PIN PCR[MUX] > */
870		nxp,kinetis-port-pins = < 9 5 >;
871	};
872	ADC1_SE14_PTB10: adc1_se14_ptb10 {
873		/* < PIN PCR[MUX] > */
874		nxp,kinetis-port-pins = < 10 0 >;
875	};
876	PTB10: GPIOB_PTB10: gpiob_ptb10 {
877		/* < PIN PCR[MUX] > */
878		nxp,kinetis-port-pins = < 10 1 >;
879	};
880	SPI1_PCS0_PTB10: spi1_pcs0_ptb10 {
881		/* < PIN PCR[MUX] > */
882		nxp,kinetis-port-pins = < 10 2 >;
883	};
884	UART3_RX_PTB10: uart3_rx_ptb10 {
885		/* < PIN PCR[MUX] > */
886		nxp,kinetis-port-pins = < 10 3 >;
887	};
888	SDRAM_D19_PTB10: sdram_d19_ptb10 {
889		/* < PIN PCR[MUX] > */
890		nxp,kinetis-port-pins = < 10 5 >;
891	};
892	FTM0_FLT1_PTB10: ftm0_flt1_ptb10 {
893		/* < PIN PCR[MUX] > */
894		nxp,kinetis-port-pins = < 10 6 >;
895	};
896	ADC1_SE15_PTB11: adc1_se15_ptb11 {
897		/* < PIN PCR[MUX] > */
898		nxp,kinetis-port-pins = < 11 0 >;
899	};
900	PTB11: GPIOB_PTB11: gpiob_ptb11 {
901		/* < PIN PCR[MUX] > */
902		nxp,kinetis-port-pins = < 11 1 >;
903	};
904	SPI1_SCK_PTB11: spi1_sck_ptb11 {
905		/* < PIN PCR[MUX] > */
906		nxp,kinetis-port-pins = < 11 2 >;
907	};
908	UART3_TX_PTB11: uart3_tx_ptb11 {
909		/* < PIN PCR[MUX] > */
910		nxp,kinetis-port-pins = < 11 3 >;
911	};
912	SDRAM_D18_PTB11: sdram_d18_ptb11 {
913		/* < PIN PCR[MUX] > */
914		nxp,kinetis-port-pins = < 11 5 >;
915	};
916	FTM0_FLT2_PTB11: ftm0_flt2_ptb11 {
917		/* < PIN PCR[MUX] > */
918		nxp,kinetis-port-pins = < 11 6 >;
919	};
920	TSI0_CH9_PTB16: tsi0_ch9_ptb16 {
921		/* < PIN PCR[MUX] > */
922		nxp,kinetis-port-pins = < 16 0 >;
923	};
924	PTB16: GPIOB_PTB16: gpiob_ptb16 {
925		/* < PIN PCR[MUX] > */
926		nxp,kinetis-port-pins = < 16 1 >;
927	};
928	SPI1_SOUT_PTB16: spi1_sout_ptb16 {
929		/* < PIN PCR[MUX] > */
930		nxp,kinetis-port-pins = < 16 2 >;
931	};
932	UART0_RX_PTB16: uart0_rx_ptb16 {
933		/* < PIN PCR[MUX] > */
934		nxp,kinetis-port-pins = < 16 3 >;
935	};
936	FTM_CLKIN0_PTB16: ftm_clkin0_ptb16 {
937		/* < PIN PCR[MUX] > */
938		nxp,kinetis-port-pins = < 16 4 >;
939	};
940	SDRAM_D17_PTB16: sdram_d17_ptb16 {
941		/* < PIN PCR[MUX] > */
942		nxp,kinetis-port-pins = < 16 5 >;
943	};
944	EWM_IN_PTB16: ewm_in_ptb16 {
945		/* < PIN PCR[MUX] > */
946		nxp,kinetis-port-pins = < 16 6 >;
947	};
948	TPM_CLKIN0_PTB16: tpm_clkin0_ptb16 {
949		/* < PIN PCR[MUX] > */
950		nxp,kinetis-port-pins = < 16 7 >;
951	};
952	TSI0_CH10_PTB17: tsi0_ch10_ptb17 {
953		/* < PIN PCR[MUX] > */
954		nxp,kinetis-port-pins = < 17 0 >;
955	};
956	PTB17: GPIOB_PTB17: gpiob_ptb17 {
957		/* < PIN PCR[MUX] > */
958		nxp,kinetis-port-pins = < 17 1 >;
959	};
960	SPI1_SIN_PTB17: spi1_sin_ptb17 {
961		/* < PIN PCR[MUX] > */
962		nxp,kinetis-port-pins = < 17 2 >;
963	};
964	UART0_TX_PTB17: uart0_tx_ptb17 {
965		/* < PIN PCR[MUX] > */
966		nxp,kinetis-port-pins = < 17 3 >;
967	};
968	FTM_CLKIN1_PTB17: ftm_clkin1_ptb17 {
969		/* < PIN PCR[MUX] > */
970		nxp,kinetis-port-pins = < 17 4 >;
971	};
972	SDRAM_D16_PTB17: sdram_d16_ptb17 {
973		/* < PIN PCR[MUX] > */
974		nxp,kinetis-port-pins = < 17 5 >;
975	};
976	EWM_OUT_b_PTB17: ewm_out_b_ptb17 {
977		/* < PIN PCR[MUX] > */
978		nxp,kinetis-port-pins = < 17 6 >;
979	};
980	TPM_CLKIN1_PTB17: tpm_clkin1_ptb17 {
981		/* < PIN PCR[MUX] > */
982		nxp,kinetis-port-pins = < 17 7 >;
983	};
984	TSI0_CH11_PTB18: tsi0_ch11_ptb18 {
985		/* < PIN PCR[MUX] > */
986		nxp,kinetis-port-pins = < 18 0 >;
987	};
988	PTB18: GPIOB_PTB18: gpiob_ptb18 {
989		/* < PIN PCR[MUX] > */
990		nxp,kinetis-port-pins = < 18 1 >;
991	};
992	CAN0_TX_PTB18: can0_tx_ptb18 {
993		/* < PIN PCR[MUX] > */
994		nxp,kinetis-port-pins = < 18 2 >;
995	};
996	FTM2_CH0_PTB18: ftm2_ch0_ptb18 {
997		/* < PIN PCR[MUX] > */
998		nxp,kinetis-port-pins = < 18 3 >;
999	};
1000	I2S0_TX_BCLK_PTB18: i2s0_tx_bclk_ptb18 {
1001		/* < PIN PCR[MUX] > */
1002		nxp,kinetis-port-pins = < 18 4 >;
1003	};
1004	SDRAM_A23_PTB18: sdram_a23_ptb18 {
1005		/* < PIN PCR[MUX] > */
1006		nxp,kinetis-port-pins = < 18 5 >;
1007	};
1008	FTM2_QD_PHA_PTB18: ftm2_qd_pha_ptb18 {
1009		/* < PIN PCR[MUX] > */
1010		nxp,kinetis-port-pins = < 18 6 >;
1011	};
1012	TPM2_CH0_PTB18: tpm2_ch0_ptb18 {
1013		/* < PIN PCR[MUX] > */
1014		nxp,kinetis-port-pins = < 18 6 >;
1015	};
1016	TSI0_CH12_PTB19: tsi0_ch12_ptb19 {
1017		/* < PIN PCR[MUX] > */
1018		nxp,kinetis-port-pins = < 19 0 >;
1019	};
1020	PTB19: GPIOB_PTB19: gpiob_ptb19 {
1021		/* < PIN PCR[MUX] > */
1022		nxp,kinetis-port-pins = < 19 1 >;
1023	};
1024	CAN0_RX_PTB19: can0_rx_ptb19 {
1025		/* < PIN PCR[MUX] > */
1026		nxp,kinetis-port-pins = < 19 2 >;
1027	};
1028	FTM2_CH1_PTB19: ftm2_ch1_ptb19 {
1029		/* < PIN PCR[MUX] > */
1030		nxp,kinetis-port-pins = < 19 3 >;
1031	};
1032	I2S0_TX_FS_PTB19: i2s0_tx_fs_ptb19 {
1033		/* < PIN PCR[MUX] > */
1034		nxp,kinetis-port-pins = < 19 4 >;
1035	};
1036	FTM2_QD_PHB_PTB19: ftm2_qd_phb_ptb19 {
1037		/* < PIN PCR[MUX] > */
1038		nxp,kinetis-port-pins = < 19 6 >;
1039	};
1040	TPM2_CH1_PTB19: tpm2_ch1_ptb19 {
1041		/* < PIN PCR[MUX] > */
1042		nxp,kinetis-port-pins = < 19 6 >;
1043	};
1044	PTB20: GPIOB_PTB20: gpiob_ptb20 {
1045		/* < PIN PCR[MUX] > */
1046		nxp,kinetis-port-pins = < 20 1 >;
1047	};
1048	SPI2_PCS0_PTB20: spi2_pcs0_ptb20 {
1049		/* < PIN PCR[MUX] > */
1050		nxp,kinetis-port-pins = < 20 2 >;
1051	};
1052	SDRAM_D31_PTB20: sdram_d31_ptb20 {
1053		/* < PIN PCR[MUX] > */
1054		nxp,kinetis-port-pins = < 20 5 >;
1055	};
1056	CMP0_OUT_PTB20: cmp0_out_ptb20 {
1057		/* < PIN PCR[MUX] > */
1058		nxp,kinetis-port-pins = < 20 6 >;
1059	};
1060	PTB21: GPIOB_PTB21: gpiob_ptb21 {
1061		/* < PIN PCR[MUX] > */
1062		nxp,kinetis-port-pins = < 21 1 >;
1063	};
1064	SPI2_SCK_PTB21: spi2_sck_ptb21 {
1065		/* < PIN PCR[MUX] > */
1066		nxp,kinetis-port-pins = < 21 2 >;
1067	};
1068	SDRAM_D30_PTB21: sdram_d30_ptb21 {
1069		/* < PIN PCR[MUX] > */
1070		nxp,kinetis-port-pins = < 21 5 >;
1071	};
1072	CMP1_OUT_PTB21: cmp1_out_ptb21 {
1073		/* < PIN PCR[MUX] > */
1074		nxp,kinetis-port-pins = < 21 6 >;
1075	};
1076	PTB22: GPIOB_PTB22: gpiob_ptb22 {
1077		/* < PIN PCR[MUX] > */
1078		nxp,kinetis-port-pins = < 22 1 >;
1079	};
1080	SPI2_SOUT_PTB22: spi2_sout_ptb22 {
1081		/* < PIN PCR[MUX] > */
1082		nxp,kinetis-port-pins = < 22 2 >;
1083	};
1084	SDRAM_D29_PTB22: sdram_d29_ptb22 {
1085		/* < PIN PCR[MUX] > */
1086		nxp,kinetis-port-pins = < 22 5 >;
1087	};
1088	CMP2_OUT_PTB22: cmp2_out_ptb22 {
1089		/* < PIN PCR[MUX] > */
1090		nxp,kinetis-port-pins = < 22 6 >;
1091	};
1092	PTB23: GPIOB_PTB23: gpiob_ptb23 {
1093		/* < PIN PCR[MUX] > */
1094		nxp,kinetis-port-pins = < 23 1 >;
1095	};
1096	SPI2_SIN_PTB23: spi2_sin_ptb23 {
1097		/* < PIN PCR[MUX] > */
1098		nxp,kinetis-port-pins = < 23 2 >;
1099	};
1100	SPI0_PCS5_PTB23: spi0_pcs5_ptb23 {
1101		/* < PIN PCR[MUX] > */
1102		nxp,kinetis-port-pins = < 23 3 >;
1103	};
1104	SDRAM_D28_PTB23: sdram_d28_ptb23 {
1105		/* < PIN PCR[MUX] > */
1106		nxp,kinetis-port-pins = < 23 5 >;
1107	};
1108	CMP3_OUT_PTB23: cmp3_out_ptb23 {
1109		/* < PIN PCR[MUX] > */
1110		nxp,kinetis-port-pins = < 23 6 >;
1111	};
1112};
1113
1114&portc {
1115	ADC0_SE14_PTC0: adc0_se14_ptc0 {
1116		/* < PIN PCR[MUX] > */
1117		nxp,kinetis-port-pins = < 0 0 >;
1118	};
1119	TSI0_CH13_PTC0: tsi0_ch13_ptc0 {
1120		/* < PIN PCR[MUX] > */
1121		nxp,kinetis-port-pins = < 0 0 >;
1122	};
1123	PTC0: GPIOC_PTC0: gpioc_ptc0 {
1124		/* < PIN PCR[MUX] > */
1125		nxp,kinetis-port-pins = < 0 1 >;
1126	};
1127	SPI0_PCS4_PTC0: spi0_pcs4_ptc0 {
1128		/* < PIN PCR[MUX] > */
1129		nxp,kinetis-port-pins = < 0 2 >;
1130	};
1131	PDB0_EXTRG_PTC0: pdb0_extrg_ptc0 {
1132		/* < PIN PCR[MUX] > */
1133		nxp,kinetis-port-pins = < 0 3 >;
1134	};
1135	USB0_SOF_OUT_PTC0: usb0_sof_out_ptc0 {
1136		/* < PIN PCR[MUX] > */
1137		nxp,kinetis-port-pins = < 0 4 >;
1138	};
1139	SDRAM_A22_PTC0: sdram_a22_ptc0 {
1140		/* < PIN PCR[MUX] > */
1141		nxp,kinetis-port-pins = < 0 5 >;
1142	};
1143	I2S0_TXD1_PTC0: i2s0_txd1_ptc0 {
1144		/* < PIN PCR[MUX] > */
1145		nxp,kinetis-port-pins = < 0 6 >;
1146	};
1147	ADC0_SE15_PTC1: adc0_se15_ptc1 {
1148		/* < PIN PCR[MUX] > */
1149		nxp,kinetis-port-pins = < 1 0 >;
1150	};
1151	TSI0_CH14_PTC1: tsi0_ch14_ptc1 {
1152		/* < PIN PCR[MUX] > */
1153		nxp,kinetis-port-pins = < 1 0 >;
1154	};
1155	PTC1: GPIOC_PTC1: gpioc_ptc1 {
1156		/* < PIN PCR[MUX] > */
1157		nxp,kinetis-port-pins = < 1 1 >;
1158	};
1159	LLWU_P6_PTC1: llwu_p6_ptc1 {
1160		/* < PIN PCR[MUX] > */
1161		nxp,kinetis-port-pins = < 1 1 >;
1162	};
1163	SPI0_PCS3_PTC1: spi0_pcs3_ptc1 {
1164		/* < PIN PCR[MUX] > */
1165		nxp,kinetis-port-pins = < 1 2 >;
1166	};
1167	UART1_RTS_b_PTC1: uart1_rts_b_ptc1 {
1168		/* < PIN PCR[MUX] > */
1169		nxp,kinetis-port-pins = < 1 3 >;
1170	};
1171	FTM0_CH0_PTC1: ftm0_ch0_ptc1 {
1172		/* < PIN PCR[MUX] > */
1173		nxp,kinetis-port-pins = < 1 4 >;
1174	};
1175	SDRAM_A21_PTC1: sdram_a21_ptc1 {
1176		/* < PIN PCR[MUX] > */
1177		nxp,kinetis-port-pins = < 1 5 >;
1178	};
1179	I2S0_TXD0_PTC1: i2s0_txd0_ptc1 {
1180		/* < PIN PCR[MUX] > */
1181		nxp,kinetis-port-pins = < 1 6 >;
1182	};
1183	ADC0_SE4b_PTC2: adc0_se4b_ptc2 {
1184		/* < PIN PCR[MUX] > */
1185		nxp,kinetis-port-pins = < 2 0 >;
1186	};
1187	CMP1_IN0_PTC2: cmp1_in0_ptc2 {
1188		/* < PIN PCR[MUX] > */
1189		nxp,kinetis-port-pins = < 2 0 >;
1190	};
1191	TSI0_CH15_PTC2: tsi0_ch15_ptc2 {
1192		/* < PIN PCR[MUX] > */
1193		nxp,kinetis-port-pins = < 2 0 >;
1194	};
1195	PTC2: GPIOC_PTC2: gpioc_ptc2 {
1196		/* < PIN PCR[MUX] > */
1197		nxp,kinetis-port-pins = < 2 1 >;
1198	};
1199	SPI0_PCS2_PTC2: spi0_pcs2_ptc2 {
1200		/* < PIN PCR[MUX] > */
1201		nxp,kinetis-port-pins = < 2 2 >;
1202	};
1203	UART1_CTS_b_PTC2: uart1_cts_b_ptc2 {
1204		/* < PIN PCR[MUX] > */
1205		nxp,kinetis-port-pins = < 2 3 >;
1206	};
1207	FTM0_CH1_PTC2: ftm0_ch1_ptc2 {
1208		/* < PIN PCR[MUX] > */
1209		nxp,kinetis-port-pins = < 2 4 >;
1210	};
1211	SDRAM_A20_PTC2: sdram_a20_ptc2 {
1212		/* < PIN PCR[MUX] > */
1213		nxp,kinetis-port-pins = < 2 5 >;
1214	};
1215	I2S0_TX_FS_PTC2: i2s0_tx_fs_ptc2 {
1216		/* < PIN PCR[MUX] > */
1217		nxp,kinetis-port-pins = < 2 6 >;
1218	};
1219	CMP1_IN1_PTC3: cmp1_in1_ptc3 {
1220		/* < PIN PCR[MUX] > */
1221		nxp,kinetis-port-pins = < 3 0 >;
1222	};
1223	PTC3: GPIOC_PTC3: gpioc_ptc3 {
1224		/* < PIN PCR[MUX] > */
1225		nxp,kinetis-port-pins = < 3 1 >;
1226	};
1227	LLWU_P7_PTC3: llwu_p7_ptc3 {
1228		/* < PIN PCR[MUX] > */
1229		nxp,kinetis-port-pins = < 3 1 >;
1230	};
1231	SPI0_PCS1_PTC3: spi0_pcs1_ptc3 {
1232		/* < PIN PCR[MUX] > */
1233		nxp,kinetis-port-pins = < 3 2 >;
1234	};
1235	UART1_RX_PTC3: uart1_rx_ptc3 {
1236		/* < PIN PCR[MUX] > */
1237		nxp,kinetis-port-pins = < 3 3 >;
1238	};
1239	FTM0_CH2_PTC3: ftm0_ch2_ptc3 {
1240		/* < PIN PCR[MUX] > */
1241		nxp,kinetis-port-pins = < 3 4 >;
1242	};
1243	CLKOUT_PTC3: clkout_ptc3 {
1244		/* < PIN PCR[MUX] > */
1245		nxp,kinetis-port-pins = < 3 5 >;
1246	};
1247	I2S0_TX_BCLK_PTC3: i2s0_tx_bclk_ptc3 {
1248		/* < PIN PCR[MUX] > */
1249		nxp,kinetis-port-pins = < 3 6 >;
1250	};
1251	PTC4: GPIOC_PTC4: gpioc_ptc4 {
1252		/* < PIN PCR[MUX] > */
1253		nxp,kinetis-port-pins = < 4 1 >;
1254	};
1255	LLWU_P8_PTC4: llwu_p8_ptc4 {
1256		/* < PIN PCR[MUX] > */
1257		nxp,kinetis-port-pins = < 4 1 >;
1258	};
1259	SPI0_PCS0_PTC4: spi0_pcs0_ptc4 {
1260		/* < PIN PCR[MUX] > */
1261		nxp,kinetis-port-pins = < 4 2 >;
1262	};
1263	UART1_TX_PTC4: uart1_tx_ptc4 {
1264		/* < PIN PCR[MUX] > */
1265		nxp,kinetis-port-pins = < 4 3 >;
1266	};
1267	FTM0_CH3_PTC4: ftm0_ch3_ptc4 {
1268		/* < PIN PCR[MUX] > */
1269		nxp,kinetis-port-pins = < 4 4 >;
1270	};
1271	SDRAM_A19_PTC4: sdram_a19_ptc4 {
1272		/* < PIN PCR[MUX] > */
1273		nxp,kinetis-port-pins = < 4 5 >;
1274	};
1275	CMP1_OUT_PTC4: cmp1_out_ptc4 {
1276		/* < PIN PCR[MUX] > */
1277		nxp,kinetis-port-pins = < 4 6 >;
1278	};
1279	PTC5: GPIOC_PTC5: gpioc_ptc5 {
1280		/* < PIN PCR[MUX] > */
1281		nxp,kinetis-port-pins = < 5 1 >;
1282	};
1283	LLWU_P9_PTC5: llwu_p9_ptc5 {
1284		/* < PIN PCR[MUX] > */
1285		nxp,kinetis-port-pins = < 5 1 >;
1286	};
1287	SPI0_SCK_PTC5: spi0_sck_ptc5 {
1288		/* < PIN PCR[MUX] > */
1289		nxp,kinetis-port-pins = < 5 2 >;
1290	};
1291	LPTMR0_ALT2_PTC5: lptmr0_alt2_ptc5 {
1292		/* < PIN PCR[MUX] > */
1293		nxp,kinetis-port-pins = < 5 3 >;
1294	};
1295	I2S0_RXD0_PTC5: i2s0_rxd0_ptc5 {
1296		/* < PIN PCR[MUX] > */
1297		nxp,kinetis-port-pins = < 5 4 >;
1298	};
1299	SDRAM_A18_PTC5: sdram_a18_ptc5 {
1300		/* < PIN PCR[MUX] > */
1301		nxp,kinetis-port-pins = < 5 5 >;
1302	};
1303	CMP0_OUT_PTC5: cmp0_out_ptc5 {
1304		/* < PIN PCR[MUX] > */
1305		nxp,kinetis-port-pins = < 5 6 >;
1306	};
1307	FTM0_CH2_PTC5: ftm0_ch2_ptc5 {
1308		/* < PIN PCR[MUX] > */
1309		nxp,kinetis-port-pins = < 5 7 >;
1310	};
1311	CMP0_IN0_PTC6: cmp0_in0_ptc6 {
1312		/* < PIN PCR[MUX] > */
1313		nxp,kinetis-port-pins = < 6 0 >;
1314	};
1315	PTC6: GPIOC_PTC6: gpioc_ptc6 {
1316		/* < PIN PCR[MUX] > */
1317		nxp,kinetis-port-pins = < 6 1 >;
1318	};
1319	LLWU_P10_PTC6: llwu_p10_ptc6 {
1320		/* < PIN PCR[MUX] > */
1321		nxp,kinetis-port-pins = < 6 1 >;
1322	};
1323	SPI0_SOUT_PTC6: spi0_sout_ptc6 {
1324		/* < PIN PCR[MUX] > */
1325		nxp,kinetis-port-pins = < 6 2 >;
1326	};
1327	PDB0_EXTRG_PTC6: pdb0_extrg_ptc6 {
1328		/* < PIN PCR[MUX] > */
1329		nxp,kinetis-port-pins = < 6 3 >;
1330	};
1331	I2S0_RX_BCLK_PTC6: i2s0_rx_bclk_ptc6 {
1332		/* < PIN PCR[MUX] > */
1333		nxp,kinetis-port-pins = < 6 4 >;
1334	};
1335	SDRAM_A17_PTC6: sdram_a17_ptc6 {
1336		/* < PIN PCR[MUX] > */
1337		nxp,kinetis-port-pins = < 6 5 >;
1338	};
1339	I2S0_MCLK_PTC6: i2s0_mclk_ptc6 {
1340		/* < PIN PCR[MUX] > */
1341		nxp,kinetis-port-pins = < 6 6 >;
1342	};
1343	CMP0_IN1_PTC7: cmp0_in1_ptc7 {
1344		/* < PIN PCR[MUX] > */
1345		nxp,kinetis-port-pins = < 7 0 >;
1346	};
1347	PTC7: GPIOC_PTC7: gpioc_ptc7 {
1348		/* < PIN PCR[MUX] > */
1349		nxp,kinetis-port-pins = < 7 1 >;
1350	};
1351	SPI0_SIN_PTC7: spi0_sin_ptc7 {
1352		/* < PIN PCR[MUX] > */
1353		nxp,kinetis-port-pins = < 7 2 >;
1354	};
1355	USB0_SOF_OUT_PTC7: usb0_sof_out_ptc7 {
1356		/* < PIN PCR[MUX] > */
1357		nxp,kinetis-port-pins = < 7 3 >;
1358	};
1359	I2S0_RX_FS_PTC7: i2s0_rx_fs_ptc7 {
1360		/* < PIN PCR[MUX] > */
1361		nxp,kinetis-port-pins = < 7 4 >;
1362	};
1363	SDRAM_A16_PTC7: sdram_a16_ptc7 {
1364		/* < PIN PCR[MUX] > */
1365		nxp,kinetis-port-pins = < 7 5 >;
1366	};
1367	ADC1_SE4b_PTC8: adc1_se4b_ptc8 {
1368		/* < PIN PCR[MUX] > */
1369		nxp,kinetis-port-pins = < 8 0 >;
1370	};
1371	CMP0_IN2_PTC8: cmp0_in2_ptc8 {
1372		/* < PIN PCR[MUX] > */
1373		nxp,kinetis-port-pins = < 8 0 >;
1374	};
1375	PTC8: GPIOC_PTC8: gpioc_ptc8 {
1376		/* < PIN PCR[MUX] > */
1377		nxp,kinetis-port-pins = < 8 1 >;
1378	};
1379	FTM3_CH4_PTC8: ftm3_ch4_ptc8 {
1380		/* < PIN PCR[MUX] > */
1381		nxp,kinetis-port-pins = < 8 3 >;
1382	};
1383	I2S0_MCLK_PTC8: i2s0_mclk_ptc8 {
1384		/* < PIN PCR[MUX] > */
1385		nxp,kinetis-port-pins = < 8 4 >;
1386	};
1387	SDRAM_A15_PTC8: sdram_a15_ptc8 {
1388		/* < PIN PCR[MUX] > */
1389		nxp,kinetis-port-pins = < 8 5 >;
1390	};
1391	ADC1_SE5b_PTC9: adc1_se5b_ptc9 {
1392		/* < PIN PCR[MUX] > */
1393		nxp,kinetis-port-pins = < 9 0 >;
1394	};
1395	CMP0_IN3_PTC9: cmp0_in3_ptc9 {
1396		/* < PIN PCR[MUX] > */
1397		nxp,kinetis-port-pins = < 9 0 >;
1398	};
1399	PTC9: GPIOC_PTC9: gpioc_ptc9 {
1400		/* < PIN PCR[MUX] > */
1401		nxp,kinetis-port-pins = < 9 1 >;
1402	};
1403	FTM3_CH5_PTC9: ftm3_ch5_ptc9 {
1404		/* < PIN PCR[MUX] > */
1405		nxp,kinetis-port-pins = < 9 3 >;
1406	};
1407	I2S0_RX_BCLK_PTC9: i2s0_rx_bclk_ptc9 {
1408		/* < PIN PCR[MUX] > */
1409		nxp,kinetis-port-pins = < 9 4 >;
1410	};
1411	SDRAM_A14_PTC9: sdram_a14_ptc9 {
1412		/* < PIN PCR[MUX] > */
1413		nxp,kinetis-port-pins = < 9 5 >;
1414	};
1415	FTM2_FLT0_PTC9: ftm2_flt0_ptc9 {
1416		/* < PIN PCR[MUX] > */
1417		nxp,kinetis-port-pins = < 9 6 >;
1418	};
1419	ADC1_SE6b_PTC10: adc1_se6b_ptc10 {
1420		/* < PIN PCR[MUX] > */
1421		nxp,kinetis-port-pins = < 10 0 >;
1422	};
1423	PTC10: GPIOC_PTC10: gpioc_ptc10 {
1424		/* < PIN PCR[MUX] > */
1425		nxp,kinetis-port-pins = < 10 1 >;
1426	};
1427	I2C1_SCL_PTC10: i2c1_scl_ptc10 {
1428		/* < PIN PCR[MUX] > */
1429		nxp,kinetis-port-pins = < 10 2 >;
1430	};
1431	FTM3_CH6_PTC10: ftm3_ch6_ptc10 {
1432		/* < PIN PCR[MUX] > */
1433		nxp,kinetis-port-pins = < 10 3 >;
1434	};
1435	I2S0_RX_FS_PTC10: i2s0_rx_fs_ptc10 {
1436		/* < PIN PCR[MUX] > */
1437		nxp,kinetis-port-pins = < 10 4 >;
1438	};
1439	SDRAM_A13_PTC10: sdram_a13_ptc10 {
1440		/* < PIN PCR[MUX] > */
1441		nxp,kinetis-port-pins = < 10 5 >;
1442	};
1443	ADC1_SE7b_PTC11: adc1_se7b_ptc11 {
1444		/* < PIN PCR[MUX] > */
1445		nxp,kinetis-port-pins = < 11 0 >;
1446	};
1447	PTC11: GPIOC_PTC11: gpioc_ptc11 {
1448		/* < PIN PCR[MUX] > */
1449		nxp,kinetis-port-pins = < 11 1 >;
1450	};
1451	LLWU_P11_PTC11: llwu_p11_ptc11 {
1452		/* < PIN PCR[MUX] > */
1453		nxp,kinetis-port-pins = < 11 1 >;
1454	};
1455	I2C1_SDA_PTC11: i2c1_sda_ptc11 {
1456		/* < PIN PCR[MUX] > */
1457		nxp,kinetis-port-pins = < 11 2 >;
1458	};
1459	FTM3_CH7_PTC11: ftm3_ch7_ptc11 {
1460		/* < PIN PCR[MUX] > */
1461		nxp,kinetis-port-pins = < 11 3 >;
1462	};
1463	I2S0_RXD1_PTC11: i2s0_rxd1_ptc11 {
1464		/* < PIN PCR[MUX] > */
1465		nxp,kinetis-port-pins = < 11 4 >;
1466	};
1467	PTC12: GPIOC_PTC12: gpioc_ptc12 {
1468		/* < PIN PCR[MUX] > */
1469		nxp,kinetis-port-pins = < 12 1 >;
1470	};
1471	UART4_RTS_b_PTC12: uart4_rts_b_ptc12 {
1472		/* < PIN PCR[MUX] > */
1473		nxp,kinetis-port-pins = < 12 3 >;
1474	};
1475	FTM_CLKIN0_PTC12: ftm_clkin0_ptc12 {
1476		/* < PIN PCR[MUX] > */
1477		nxp,kinetis-port-pins = < 12 4 >;
1478	};
1479	SDRAM_D27_PTC12: sdram_d27_ptc12 {
1480		/* < PIN PCR[MUX] > */
1481		nxp,kinetis-port-pins = < 12 5 >;
1482	};
1483	FTM3_FLT0_PTC12: ftm3_flt0_ptc12 {
1484		/* < PIN PCR[MUX] > */
1485		nxp,kinetis-port-pins = < 12 6 >;
1486	};
1487	TPM_CLKIN0_PTC12: tpm_clkin0_ptc12 {
1488		/* < PIN PCR[MUX] > */
1489		nxp,kinetis-port-pins = < 12 7 >;
1490	};
1491	PTC13: GPIOC_PTC13: gpioc_ptc13 {
1492		/* < PIN PCR[MUX] > */
1493		nxp,kinetis-port-pins = < 13 1 >;
1494	};
1495	UART4_CTS_b_PTC13: uart4_cts_b_ptc13 {
1496		/* < PIN PCR[MUX] > */
1497		nxp,kinetis-port-pins = < 13 3 >;
1498	};
1499	FTM_CLKIN1_PTC13: ftm_clkin1_ptc13 {
1500		/* < PIN PCR[MUX] > */
1501		nxp,kinetis-port-pins = < 13 4 >;
1502	};
1503	SDRAM_D26_PTC13: sdram_d26_ptc13 {
1504		/* < PIN PCR[MUX] > */
1505		nxp,kinetis-port-pins = < 13 5 >;
1506	};
1507	TPM_CLKIN1_PTC13: tpm_clkin1_ptc13 {
1508		/* < PIN PCR[MUX] > */
1509		nxp,kinetis-port-pins = < 13 7 >;
1510	};
1511	PTC14: GPIOC_PTC14: gpioc_ptc14 {
1512		/* < PIN PCR[MUX] > */
1513		nxp,kinetis-port-pins = < 14 1 >;
1514	};
1515	UART4_RX_PTC14: uart4_rx_ptc14 {
1516		/* < PIN PCR[MUX] > */
1517		nxp,kinetis-port-pins = < 14 3 >;
1518	};
1519	SDRAM_D25_PTC14: sdram_d25_ptc14 {
1520		/* < PIN PCR[MUX] > */
1521		nxp,kinetis-port-pins = < 14 5 >;
1522	};
1523	PTC15: GPIOC_PTC15: gpioc_ptc15 {
1524		/* < PIN PCR[MUX] > */
1525		nxp,kinetis-port-pins = < 15 1 >;
1526	};
1527	UART4_TX_PTC15: uart4_tx_ptc15 {
1528		/* < PIN PCR[MUX] > */
1529		nxp,kinetis-port-pins = < 15 3 >;
1530	};
1531	SDRAM_D24_PTC15: sdram_d24_ptc15 {
1532		/* < PIN PCR[MUX] > */
1533		nxp,kinetis-port-pins = < 15 5 >;
1534	};
1535	PTC16: GPIOC_PTC16: gpioc_ptc16 {
1536		/* < PIN PCR[MUX] > */
1537		nxp,kinetis-port-pins = < 16 1 >;
1538	};
1539	CAN1_RX_PTC16: can1_rx_ptc16 {
1540		/* < PIN PCR[MUX] > */
1541		nxp,kinetis-port-pins = < 16 2 >;
1542	};
1543	UART3_RX_PTC16: uart3_rx_ptc16 {
1544		/* < PIN PCR[MUX] > */
1545		nxp,kinetis-port-pins = < 16 3 >;
1546	};
1547	ENET0_1588_TMR0_PTC16: enet0_1588_tmr0_ptc16 {
1548		/* < PIN PCR[MUX] > */
1549		nxp,kinetis-port-pins = < 16 4 >;
1550	};
1551	SDRAM_DQM2_PTC16: sdram_dqm2_ptc16 {
1552		/* < PIN PCR[MUX] > */
1553		nxp,kinetis-port-pins = < 16 5 >;
1554	};
1555	PTC17: GPIOC_PTC17: gpioc_ptc17 {
1556		/* < PIN PCR[MUX] > */
1557		nxp,kinetis-port-pins = < 17 1 >;
1558	};
1559	CAN1_TX_PTC17: can1_tx_ptc17 {
1560		/* < PIN PCR[MUX] > */
1561		nxp,kinetis-port-pins = < 17 2 >;
1562	};
1563	UART3_TX_PTC17: uart3_tx_ptc17 {
1564		/* < PIN PCR[MUX] > */
1565		nxp,kinetis-port-pins = < 17 3 >;
1566	};
1567	ENET0_1588_TMR1_PTC17: enet0_1588_tmr1_ptc17 {
1568		/* < PIN PCR[MUX] > */
1569		nxp,kinetis-port-pins = < 17 4 >;
1570	};
1571	SDRAM_DQM3_PTC17: sdram_dqm3_ptc17 {
1572		/* < PIN PCR[MUX] > */
1573		nxp,kinetis-port-pins = < 17 5 >;
1574	};
1575	PTC18: GPIOC_PTC18: gpioc_ptc18 {
1576		/* < PIN PCR[MUX] > */
1577		nxp,kinetis-port-pins = < 18 1 >;
1578	};
1579	UART3_RTS_b_PTC18: uart3_rts_b_ptc18 {
1580		/* < PIN PCR[MUX] > */
1581		nxp,kinetis-port-pins = < 18 3 >;
1582	};
1583	ENET0_1588_TMR2_PTC18: enet0_1588_tmr2_ptc18 {
1584		/* < PIN PCR[MUX] > */
1585		nxp,kinetis-port-pins = < 18 4 >;
1586	};
1587	SDRAM_DQM1_PTC18: sdram_dqm1_ptc18 {
1588		/* < PIN PCR[MUX] > */
1589		nxp,kinetis-port-pins = < 18 5 >;
1590	};
1591	PTC19: GPIOC_PTC19: gpioc_ptc19 {
1592		/* < PIN PCR[MUX] > */
1593		nxp,kinetis-port-pins = < 19 1 >;
1594	};
1595	UART3_CTS_b_PTC19: uart3_cts_b_ptc19 {
1596		/* < PIN PCR[MUX] > */
1597		nxp,kinetis-port-pins = < 19 3 >;
1598	};
1599	ENET0_1588_TMR3_PTC19: enet0_1588_tmr3_ptc19 {
1600		/* < PIN PCR[MUX] > */
1601		nxp,kinetis-port-pins = < 19 4 >;
1602	};
1603	SDRAM_DQM0_PTC19: sdram_dqm0_ptc19 {
1604		/* < PIN PCR[MUX] > */
1605		nxp,kinetis-port-pins = < 19 5 >;
1606	};
1607};
1608
1609&portd {
1610	PTD0: GPIOD_PTD0: gpiod_ptd0 {
1611		/* < PIN PCR[MUX] > */
1612		nxp,kinetis-port-pins = < 0 1 >;
1613	};
1614	LLWU_P12_PTD0: llwu_p12_ptd0 {
1615		/* < PIN PCR[MUX] > */
1616		nxp,kinetis-port-pins = < 0 1 >;
1617	};
1618	SPI0_PCS0_PTD0: spi0_pcs0_ptd0 {
1619		/* < PIN PCR[MUX] > */
1620		nxp,kinetis-port-pins = < 0 2 >;
1621	};
1622	UART2_RTS_b_PTD0: uart2_rts_b_ptd0 {
1623		/* < PIN PCR[MUX] > */
1624		nxp,kinetis-port-pins = < 0 3 >;
1625	};
1626	FTM3_CH0_PTD0: ftm3_ch0_ptd0 {
1627		/* < PIN PCR[MUX] > */
1628		nxp,kinetis-port-pins = < 0 4 >;
1629	};
1630	ADC0_SE5b_PTD1: adc0_se5b_ptd1 {
1631		/* < PIN PCR[MUX] > */
1632		nxp,kinetis-port-pins = < 1 0 >;
1633	};
1634	PTD1: GPIOD_PTD1: gpiod_ptd1 {
1635		/* < PIN PCR[MUX] > */
1636		nxp,kinetis-port-pins = < 1 1 >;
1637	};
1638	SPI0_SCK_PTD1: spi0_sck_ptd1 {
1639		/* < PIN PCR[MUX] > */
1640		nxp,kinetis-port-pins = < 1 2 >;
1641	};
1642	UART2_CTS_b_PTD1: uart2_cts_b_ptd1 {
1643		/* < PIN PCR[MUX] > */
1644		nxp,kinetis-port-pins = < 1 3 >;
1645	};
1646	FTM3_CH1_PTD1: ftm3_ch1_ptd1 {
1647		/* < PIN PCR[MUX] > */
1648		nxp,kinetis-port-pins = < 1 4 >;
1649	};
1650	PTD2: GPIOD_PTD2: gpiod_ptd2 {
1651		/* < PIN PCR[MUX] > */
1652		nxp,kinetis-port-pins = < 2 1 >;
1653	};
1654	LLWU_P13_PTD2: llwu_p13_ptd2 {
1655		/* < PIN PCR[MUX] > */
1656		nxp,kinetis-port-pins = < 2 1 >;
1657	};
1658	SPI0_SOUT_PTD2: spi0_sout_ptd2 {
1659		/* < PIN PCR[MUX] > */
1660		nxp,kinetis-port-pins = < 2 2 >;
1661	};
1662	UART2_RX_PTD2: uart2_rx_ptd2 {
1663		/* < PIN PCR[MUX] > */
1664		nxp,kinetis-port-pins = < 2 3 >;
1665	};
1666	FTM3_CH2_PTD2: ftm3_ch2_ptd2 {
1667		/* < PIN PCR[MUX] > */
1668		nxp,kinetis-port-pins = < 2 4 >;
1669	};
1670	SDRAM_A12_PTD2: sdram_a12_ptd2 {
1671		/* < PIN PCR[MUX] > */
1672		nxp,kinetis-port-pins = < 2 5 >;
1673	};
1674	I2C0_SCL_PTD2: i2c0_scl_ptd2 {
1675		/* < PIN PCR[MUX] > */
1676		nxp,kinetis-port-pins = < 2 7 >;
1677	};
1678	PTD3: GPIOD_PTD3: gpiod_ptd3 {
1679		/* < PIN PCR[MUX] > */
1680		nxp,kinetis-port-pins = < 3 1 >;
1681	};
1682	SPI0_SIN_PTD3: spi0_sin_ptd3 {
1683		/* < PIN PCR[MUX] > */
1684		nxp,kinetis-port-pins = < 3 2 >;
1685	};
1686	UART2_TX_PTD3: uart2_tx_ptd3 {
1687		/* < PIN PCR[MUX] > */
1688		nxp,kinetis-port-pins = < 3 3 >;
1689	};
1690	FTM3_CH3_PTD3: ftm3_ch3_ptd3 {
1691		/* < PIN PCR[MUX] > */
1692		nxp,kinetis-port-pins = < 3 4 >;
1693	};
1694	SDRAM_A11_PTD3: sdram_a11_ptd3 {
1695		/* < PIN PCR[MUX] > */
1696		nxp,kinetis-port-pins = < 3 5 >;
1697	};
1698	I2C0_SDA_PTD3: i2c0_sda_ptd3 {
1699		/* < PIN PCR[MUX] > */
1700		nxp,kinetis-port-pins = < 3 7 >;
1701	};
1702	PTD4: GPIOD_PTD4: gpiod_ptd4 {
1703		/* < PIN PCR[MUX] > */
1704		nxp,kinetis-port-pins = < 4 1 >;
1705	};
1706	LLWU_P14_PTD4: llwu_p14_ptd4 {
1707		/* < PIN PCR[MUX] > */
1708		nxp,kinetis-port-pins = < 4 1 >;
1709	};
1710	SPI0_PCS1_PTD4: spi0_pcs1_ptd4 {
1711		/* < PIN PCR[MUX] > */
1712		nxp,kinetis-port-pins = < 4 2 >;
1713	};
1714	UART0_RTS_b_PTD4: uart0_rts_b_ptd4 {
1715		/* < PIN PCR[MUX] > */
1716		nxp,kinetis-port-pins = < 4 3 >;
1717	};
1718	FTM0_CH4_PTD4: ftm0_ch4_ptd4 {
1719		/* < PIN PCR[MUX] > */
1720		nxp,kinetis-port-pins = < 4 4 >;
1721	};
1722	SDRAM_A10_PTD4: sdram_a10_ptd4 {
1723		/* < PIN PCR[MUX] > */
1724		nxp,kinetis-port-pins = < 4 5 >;
1725	};
1726	EWM_IN_PTD4: ewm_in_ptd4 {
1727		/* < PIN PCR[MUX] > */
1728		nxp,kinetis-port-pins = < 4 6 >;
1729	};
1730	SPI1_PCS0_PTD4: spi1_pcs0_ptd4 {
1731		/* < PIN PCR[MUX] > */
1732		nxp,kinetis-port-pins = < 4 7 >;
1733	};
1734	ADC0_SE6b_PTD5: adc0_se6b_ptd5 {
1735		/* < PIN PCR[MUX] > */
1736		nxp,kinetis-port-pins = < 5 0 >;
1737	};
1738	PTD5: GPIOD_PTD5: gpiod_ptd5 {
1739		/* < PIN PCR[MUX] > */
1740		nxp,kinetis-port-pins = < 5 1 >;
1741	};
1742	SPI0_PCS2_PTD5: spi0_pcs2_ptd5 {
1743		/* < PIN PCR[MUX] > */
1744		nxp,kinetis-port-pins = < 5 2 >;
1745	};
1746	UART0_CTS_b_PTD5: uart0_cts_b_ptd5 {
1747		/* < PIN PCR[MUX] > */
1748		nxp,kinetis-port-pins = < 5 3 >;
1749	};
1750	FTM0_CH5_PTD5: ftm0_ch5_ptd5 {
1751		/* < PIN PCR[MUX] > */
1752		nxp,kinetis-port-pins = < 5 4 >;
1753	};
1754	SDRAM_A9_PTD5: sdram_a9_ptd5 {
1755		/* < PIN PCR[MUX] > */
1756		nxp,kinetis-port-pins = < 5 5 >;
1757	};
1758	EWM_OUT_b_PTD5: ewm_out_b_ptd5 {
1759		/* < PIN PCR[MUX] > */
1760		nxp,kinetis-port-pins = < 5 6 >;
1761	};
1762	SPI1_SCK_PTD5: spi1_sck_ptd5 {
1763		/* < PIN PCR[MUX] > */
1764		nxp,kinetis-port-pins = < 5 7 >;
1765	};
1766	ADC0_SE7b_PTD6: adc0_se7b_ptd6 {
1767		/* < PIN PCR[MUX] > */
1768		nxp,kinetis-port-pins = < 6 0 >;
1769	};
1770	PTD6: GPIOD_PTD6: gpiod_ptd6 {
1771		/* < PIN PCR[MUX] > */
1772		nxp,kinetis-port-pins = < 6 1 >;
1773	};
1774	LLWU_P15_PTD6: llwu_p15_ptd6 {
1775		/* < PIN PCR[MUX] > */
1776		nxp,kinetis-port-pins = < 6 1 >;
1777	};
1778	SPI0_PCS3_PTD6: spi0_pcs3_ptd6 {
1779		/* < PIN PCR[MUX] > */
1780		nxp,kinetis-port-pins = < 6 2 >;
1781	};
1782	UART0_RX_PTD6: uart0_rx_ptd6 {
1783		/* < PIN PCR[MUX] > */
1784		nxp,kinetis-port-pins = < 6 3 >;
1785	};
1786	FTM0_CH6_PTD6: ftm0_ch6_ptd6 {
1787		/* < PIN PCR[MUX] > */
1788		nxp,kinetis-port-pins = < 6 4 >;
1789	};
1790	FTM0_FLT0_PTD6: ftm0_flt0_ptd6 {
1791		/* < PIN PCR[MUX] > */
1792		nxp,kinetis-port-pins = < 6 6 >;
1793	};
1794	SPI1_SOUT_PTD6: spi1_sout_ptd6 {
1795		/* < PIN PCR[MUX] > */
1796		nxp,kinetis-port-pins = < 6 7 >;
1797	};
1798	PTD7: GPIOD_PTD7: gpiod_ptd7 {
1799		/* < PIN PCR[MUX] > */
1800		nxp,kinetis-port-pins = < 7 1 >;
1801	};
1802	CMT_IRO_PTD7: cmt_iro_ptd7 {
1803		/* < PIN PCR[MUX] > */
1804		nxp,kinetis-port-pins = < 7 2 >;
1805	};
1806	UART0_TX_PTD7: uart0_tx_ptd7 {
1807		/* < PIN PCR[MUX] > */
1808		nxp,kinetis-port-pins = < 7 3 >;
1809	};
1810	FTM0_CH7_PTD7: ftm0_ch7_ptd7 {
1811		/* < PIN PCR[MUX] > */
1812		nxp,kinetis-port-pins = < 7 4 >;
1813	};
1814	SDRAM_CKE_PTD7: sdram_cke_ptd7 {
1815		/* < PIN PCR[MUX] > */
1816		nxp,kinetis-port-pins = < 7 5 >;
1817	};
1818	FTM0_FLT1_PTD7: ftm0_flt1_ptd7 {
1819		/* < PIN PCR[MUX] > */
1820		nxp,kinetis-port-pins = < 7 6 >;
1821	};
1822	SPI1_SIN_PTD7: spi1_sin_ptd7 {
1823		/* < PIN PCR[MUX] > */
1824		nxp,kinetis-port-pins = < 7 7 >;
1825	};
1826	PTD8: GPIOD_PTD8: gpiod_ptd8 {
1827		/* < PIN PCR[MUX] > */
1828		nxp,kinetis-port-pins = < 8 1 >;
1829	};
1830	LLWU_P24_PTD8: llwu_p24_ptd8 {
1831		/* < PIN PCR[MUX] > */
1832		nxp,kinetis-port-pins = < 8 1 >;
1833	};
1834	I2C0_SCL_PTD8: i2c0_scl_ptd8 {
1835		/* < PIN PCR[MUX] > */
1836		nxp,kinetis-port-pins = < 8 2 >;
1837	};
1838	LPUART0_RX_PTD8: lpuart0_rx_ptd8 {
1839		/* < PIN PCR[MUX] > */
1840		nxp,kinetis-port-pins = < 8 5 >;
1841	};
1842	PTD9: GPIOD_PTD9: gpiod_ptd9 {
1843		/* < PIN PCR[MUX] > */
1844		nxp,kinetis-port-pins = < 9 1 >;
1845	};
1846	I2C0_SDA_PTD9: i2c0_sda_ptd9 {
1847		/* < PIN PCR[MUX] > */
1848		nxp,kinetis-port-pins = < 9 2 >;
1849	};
1850	LPUART0_TX_PTD9: lpuart0_tx_ptd9 {
1851		/* < PIN PCR[MUX] > */
1852		nxp,kinetis-port-pins = < 9 5 >;
1853	};
1854	PTD10: GPIOD_PTD10: gpiod_ptd10 {
1855		/* < PIN PCR[MUX] > */
1856		nxp,kinetis-port-pins = < 10 1 >;
1857	};
1858	LPUART0_RTS_b_PTD10: lpuart0_rts_b_ptd10 {
1859		/* < PIN PCR[MUX] > */
1860		nxp,kinetis-port-pins = < 10 5 >;
1861	};
1862	PTD11: GPIOD_PTD11: gpiod_ptd11 {
1863		/* < PIN PCR[MUX] > */
1864		nxp,kinetis-port-pins = < 11 1 >;
1865	};
1866	LLWU_P25_PTD11: llwu_p25_ptd11 {
1867		/* < PIN PCR[MUX] > */
1868		nxp,kinetis-port-pins = < 11 1 >;
1869	};
1870	SPI2_PCS0_PTD11: spi2_pcs0_ptd11 {
1871		/* < PIN PCR[MUX] > */
1872		nxp,kinetis-port-pins = < 11 2 >;
1873	};
1874	SDHC0_CLKIN_PTD11: sdhc0_clkin_ptd11 {
1875		/* < PIN PCR[MUX] > */
1876		nxp,kinetis-port-pins = < 11 4 >;
1877	};
1878	LPUART0_CTS_b_PTD11: lpuart0_cts_b_ptd11 {
1879		/* < PIN PCR[MUX] > */
1880		nxp,kinetis-port-pins = < 11 5 >;
1881	};
1882	PTD12: GPIOD_PTD12: gpiod_ptd12 {
1883		/* < PIN PCR[MUX] > */
1884		nxp,kinetis-port-pins = < 12 1 >;
1885	};
1886	SPI2_SCK_PTD12: spi2_sck_ptd12 {
1887		/* < PIN PCR[MUX] > */
1888		nxp,kinetis-port-pins = < 12 2 >;
1889	};
1890	FTM3_FLT0_PTD12: ftm3_flt0_ptd12 {
1891		/* < PIN PCR[MUX] > */
1892		nxp,kinetis-port-pins = < 12 3 >;
1893	};
1894	SDHC0_D4_PTD12: sdhc0_d4_ptd12 {
1895		/* < PIN PCR[MUX] > */
1896		nxp,kinetis-port-pins = < 12 4 >;
1897	};
1898	PTD13: GPIOD_PTD13: gpiod_ptd13 {
1899		/* < PIN PCR[MUX] > */
1900		nxp,kinetis-port-pins = < 13 1 >;
1901	};
1902	SPI2_SOUT_PTD13: spi2_sout_ptd13 {
1903		/* < PIN PCR[MUX] > */
1904		nxp,kinetis-port-pins = < 13 2 >;
1905	};
1906	SDHC0_D5_PTD13: sdhc0_d5_ptd13 {
1907		/* < PIN PCR[MUX] > */
1908		nxp,kinetis-port-pins = < 13 4 >;
1909	};
1910	PTD14: GPIOD_PTD14: gpiod_ptd14 {
1911		/* < PIN PCR[MUX] > */
1912		nxp,kinetis-port-pins = < 14 1 >;
1913	};
1914	SPI2_SIN_PTD14: spi2_sin_ptd14 {
1915		/* < PIN PCR[MUX] > */
1916		nxp,kinetis-port-pins = < 14 2 >;
1917	};
1918	SDHC0_D6_PTD14: sdhc0_d6_ptd14 {
1919		/* < PIN PCR[MUX] > */
1920		nxp,kinetis-port-pins = < 14 4 >;
1921	};
1922	PTD15: GPIOD_PTD15: gpiod_ptd15 {
1923		/* < PIN PCR[MUX] > */
1924		nxp,kinetis-port-pins = < 15 1 >;
1925	};
1926	SPI2_PCS1_PTD15: spi2_pcs1_ptd15 {
1927		/* < PIN PCR[MUX] > */
1928		nxp,kinetis-port-pins = < 15 2 >;
1929	};
1930	SDHC0_D7_PTD15: sdhc0_d7_ptd15 {
1931		/* < PIN PCR[MUX] > */
1932		nxp,kinetis-port-pins = < 15 4 >;
1933	};
1934};
1935
1936&porte {
1937	ADC1_SE4a_PTE0: adc1_se4a_pte0 {
1938		/* < PIN PCR[MUX] > */
1939		nxp,kinetis-port-pins = < 0 0 >;
1940	};
1941	PTE0: GPIOE_PTE0: gpioe_pte0 {
1942		/* < PIN PCR[MUX] > */
1943		nxp,kinetis-port-pins = < 0 1 >;
1944	};
1945	SPI1_PCS1_PTE0: spi1_pcs1_pte0 {
1946		/* < PIN PCR[MUX] > */
1947		nxp,kinetis-port-pins = < 0 2 >;
1948	};
1949	UART1_TX_PTE0: uart1_tx_pte0 {
1950		/* < PIN PCR[MUX] > */
1951		nxp,kinetis-port-pins = < 0 3 >;
1952	};
1953	SDHC0_D1_PTE0: sdhc0_d1_pte0 {
1954		/* < PIN PCR[MUX] > */
1955		nxp,kinetis-port-pins = < 0 4 >;
1956	};
1957	TRACE_CLKOUT_PTE0: trace_clkout_pte0 {
1958		/* < PIN PCR[MUX] > */
1959		nxp,kinetis-port-pins = < 0 5 >;
1960	};
1961	I2C1_SDA_PTE0: i2c1_sda_pte0 {
1962		/* < PIN PCR[MUX] > */
1963		nxp,kinetis-port-pins = < 0 6 >;
1964	};
1965	RTC_CLKOUT_PTE0: rtc_clkout_pte0 {
1966		/* < PIN PCR[MUX] > */
1967		nxp,kinetis-port-pins = < 0 7 >;
1968	};
1969	ADC1_SE5a_PTE1: adc1_se5a_pte1 {
1970		/* < PIN PCR[MUX] > */
1971		nxp,kinetis-port-pins = < 1 0 >;
1972	};
1973	PTE1: GPIOE_PTE1: gpioe_pte1 {
1974		/* < PIN PCR[MUX] > */
1975		nxp,kinetis-port-pins = < 1 1 >;
1976	};
1977	LLWU_P0_PTE1: llwu_p0_pte1 {
1978		/* < PIN PCR[MUX] > */
1979		nxp,kinetis-port-pins = < 1 1 >;
1980	};
1981	SPI1_SOUT_PTE1: spi1_sout_pte1 {
1982		/* < PIN PCR[MUX] > */
1983		nxp,kinetis-port-pins = < 1 2 >;
1984	};
1985	UART1_RX_PTE1: uart1_rx_pte1 {
1986		/* < PIN PCR[MUX] > */
1987		nxp,kinetis-port-pins = < 1 3 >;
1988	};
1989	SDHC0_D0_PTE1: sdhc0_d0_pte1 {
1990		/* < PIN PCR[MUX] > */
1991		nxp,kinetis-port-pins = < 1 4 >;
1992	};
1993	TRACE_D3_PTE1: trace_d3_pte1 {
1994		/* < PIN PCR[MUX] > */
1995		nxp,kinetis-port-pins = < 1 5 >;
1996	};
1997	I2C1_SCL_PTE1: i2c1_scl_pte1 {
1998		/* < PIN PCR[MUX] > */
1999		nxp,kinetis-port-pins = < 1 6 >;
2000	};
2001	SPI1_SIN_PTE1: spi1_sin_pte1 {
2002		/* < PIN PCR[MUX] > */
2003		nxp,kinetis-port-pins = < 1 7 >;
2004	};
2005	ADC1_SE6a_PTE2: adc1_se6a_pte2 {
2006		/* < PIN PCR[MUX] > */
2007		nxp,kinetis-port-pins = < 2 0 >;
2008	};
2009	PTE2: GPIOE_PTE2: gpioe_pte2 {
2010		/* < PIN PCR[MUX] > */
2011		nxp,kinetis-port-pins = < 2 1 >;
2012	};
2013	LLWU_P1_PTE2: llwu_p1_pte2 {
2014		/* < PIN PCR[MUX] > */
2015		nxp,kinetis-port-pins = < 2 1 >;
2016	};
2017	SPI1_SCK_PTE2: spi1_sck_pte2 {
2018		/* < PIN PCR[MUX] > */
2019		nxp,kinetis-port-pins = < 2 2 >;
2020	};
2021	UART1_CTS_b_PTE2: uart1_cts_b_pte2 {
2022		/* < PIN PCR[MUX] > */
2023		nxp,kinetis-port-pins = < 2 3 >;
2024	};
2025	SDHC0_DCLK_PTE2: sdhc0_dclk_pte2 {
2026		/* < PIN PCR[MUX] > */
2027		nxp,kinetis-port-pins = < 2 4 >;
2028	};
2029	TRACE_D2_PTE2: trace_d2_pte2 {
2030		/* < PIN PCR[MUX] > */
2031		nxp,kinetis-port-pins = < 2 5 >;
2032	};
2033	ADC1_SE7a_PTE3: adc1_se7a_pte3 {
2034		/* < PIN PCR[MUX] > */
2035		nxp,kinetis-port-pins = < 3 0 >;
2036	};
2037	PTE3: GPIOE_PTE3: gpioe_pte3 {
2038		/* < PIN PCR[MUX] > */
2039		nxp,kinetis-port-pins = < 3 1 >;
2040	};
2041	SPI1_SIN_PTE3: spi1_sin_pte3 {
2042		/* < PIN PCR[MUX] > */
2043		nxp,kinetis-port-pins = < 3 2 >;
2044	};
2045	UART1_RTS_b_PTE3: uart1_rts_b_pte3 {
2046		/* < PIN PCR[MUX] > */
2047		nxp,kinetis-port-pins = < 3 3 >;
2048	};
2049	SDHC0_CMD_PTE3: sdhc0_cmd_pte3 {
2050		/* < PIN PCR[MUX] > */
2051		nxp,kinetis-port-pins = < 3 4 >;
2052	};
2053	TRACE_D1_PTE3: trace_d1_pte3 {
2054		/* < PIN PCR[MUX] > */
2055		nxp,kinetis-port-pins = < 3 5 >;
2056	};
2057	SPI1_SOUT_PTE3: spi1_sout_pte3 {
2058		/* < PIN PCR[MUX] > */
2059		nxp,kinetis-port-pins = < 3 7 >;
2060	};
2061	PTE4: GPIOE_PTE4: gpioe_pte4 {
2062		/* < PIN PCR[MUX] > */
2063		nxp,kinetis-port-pins = < 4 1 >;
2064	};
2065	LLWU_P2_PTE4: llwu_p2_pte4 {
2066		/* < PIN PCR[MUX] > */
2067		nxp,kinetis-port-pins = < 4 1 >;
2068	};
2069	SPI1_PCS0_PTE4: spi1_pcs0_pte4 {
2070		/* < PIN PCR[MUX] > */
2071		nxp,kinetis-port-pins = < 4 2 >;
2072	};
2073	UART3_TX_PTE4: uart3_tx_pte4 {
2074		/* < PIN PCR[MUX] > */
2075		nxp,kinetis-port-pins = < 4 3 >;
2076	};
2077	SDHC0_D3_PTE4: sdhc0_d3_pte4 {
2078		/* < PIN PCR[MUX] > */
2079		nxp,kinetis-port-pins = < 4 4 >;
2080	};
2081	TRACE_D0_PTE4: trace_d0_pte4 {
2082		/* < PIN PCR[MUX] > */
2083		nxp,kinetis-port-pins = < 4 5 >;
2084	};
2085	PTE5: GPIOE_PTE5: gpioe_pte5 {
2086		/* < PIN PCR[MUX] > */
2087		nxp,kinetis-port-pins = < 5 1 >;
2088	};
2089	SPI1_PCS2_PTE5: spi1_pcs2_pte5 {
2090		/* < PIN PCR[MUX] > */
2091		nxp,kinetis-port-pins = < 5 2 >;
2092	};
2093	UART3_RX_PTE5: uart3_rx_pte5 {
2094		/* < PIN PCR[MUX] > */
2095		nxp,kinetis-port-pins = < 5 3 >;
2096	};
2097	SDHC0_D2_PTE5: sdhc0_d2_pte5 {
2098		/* < PIN PCR[MUX] > */
2099		nxp,kinetis-port-pins = < 5 4 >;
2100	};
2101	FTM3_CH0_PTE5: ftm3_ch0_pte5 {
2102		/* < PIN PCR[MUX] > */
2103		nxp,kinetis-port-pins = < 5 6 >;
2104	};
2105	PTE6: GPIOE_PTE6: gpioe_pte6 {
2106		/* < PIN PCR[MUX] > */
2107		nxp,kinetis-port-pins = < 6 1 >;
2108	};
2109	LLWU_P16_PTE6: llwu_p16_pte6 {
2110		/* < PIN PCR[MUX] > */
2111		nxp,kinetis-port-pins = < 6 1 >;
2112	};
2113	SPI1_PCS3_PTE6: spi1_pcs3_pte6 {
2114		/* < PIN PCR[MUX] > */
2115		nxp,kinetis-port-pins = < 6 2 >;
2116	};
2117	UART3_CTS_b_PTE6: uart3_cts_b_pte6 {
2118		/* < PIN PCR[MUX] > */
2119		nxp,kinetis-port-pins = < 6 3 >;
2120	};
2121	I2S0_MCLK_PTE6: i2s0_mclk_pte6 {
2122		/* < PIN PCR[MUX] > */
2123		nxp,kinetis-port-pins = < 6 4 >;
2124	};
2125	FTM3_CH1_PTE6: ftm3_ch1_pte6 {
2126		/* < PIN PCR[MUX] > */
2127		nxp,kinetis-port-pins = < 6 6 >;
2128	};
2129	USB0_SOF_OUT_PTE6: usb0_sof_out_pte6 {
2130		/* < PIN PCR[MUX] > */
2131		nxp,kinetis-port-pins = < 6 7 >;
2132	};
2133	PTE7: GPIOE_PTE7: gpioe_pte7 {
2134		/* < PIN PCR[MUX] > */
2135		nxp,kinetis-port-pins = < 7 1 >;
2136	};
2137	UART3_RTS_b_PTE7: uart3_rts_b_pte7 {
2138		/* < PIN PCR[MUX] > */
2139		nxp,kinetis-port-pins = < 7 3 >;
2140	};
2141	I2S0_RXD0_PTE7: i2s0_rxd0_pte7 {
2142		/* < PIN PCR[MUX] > */
2143		nxp,kinetis-port-pins = < 7 4 >;
2144	};
2145	FTM3_CH2_PTE7: ftm3_ch2_pte7 {
2146		/* < PIN PCR[MUX] > */
2147		nxp,kinetis-port-pins = < 7 6 >;
2148	};
2149	PTE8: GPIOE_PTE8: gpioe_pte8 {
2150		/* < PIN PCR[MUX] > */
2151		nxp,kinetis-port-pins = < 8 1 >;
2152	};
2153	I2S0_RXD1_PTE8: i2s0_rxd1_pte8 {
2154		/* < PIN PCR[MUX] > */
2155		nxp,kinetis-port-pins = < 8 2 >;
2156	};
2157	I2S0_RX_FS_PTE8: i2s0_rx_fs_pte8 {
2158		/* < PIN PCR[MUX] > */
2159		nxp,kinetis-port-pins = < 8 4 >;
2160	};
2161	LPUART0_TX_PTE8: lpuart0_tx_pte8 {
2162		/* < PIN PCR[MUX] > */
2163		nxp,kinetis-port-pins = < 8 5 >;
2164	};
2165	FTM3_CH3_PTE8: ftm3_ch3_pte8 {
2166		/* < PIN PCR[MUX] > */
2167		nxp,kinetis-port-pins = < 8 6 >;
2168	};
2169	PTE9: GPIOE_PTE9: gpioe_pte9 {
2170		/* < PIN PCR[MUX] > */
2171		nxp,kinetis-port-pins = < 9 1 >;
2172	};
2173	LLWU_P17_PTE9: llwu_p17_pte9 {
2174		/* < PIN PCR[MUX] > */
2175		nxp,kinetis-port-pins = < 9 1 >;
2176	};
2177	I2S0_TXD1_PTE9: i2s0_txd1_pte9 {
2178		/* < PIN PCR[MUX] > */
2179		nxp,kinetis-port-pins = < 9 2 >;
2180	};
2181	I2S0_RX_BCLK_PTE9: i2s0_rx_bclk_pte9 {
2182		/* < PIN PCR[MUX] > */
2183		nxp,kinetis-port-pins = < 9 4 >;
2184	};
2185	LPUART0_RX_PTE9: lpuart0_rx_pte9 {
2186		/* < PIN PCR[MUX] > */
2187		nxp,kinetis-port-pins = < 9 5 >;
2188	};
2189	FTM3_CH4_PTE9: ftm3_ch4_pte9 {
2190		/* < PIN PCR[MUX] > */
2191		nxp,kinetis-port-pins = < 9 6 >;
2192	};
2193	PTE10: GPIOE_PTE10: gpioe_pte10 {
2194		/* < PIN PCR[MUX] > */
2195		nxp,kinetis-port-pins = < 10 1 >;
2196	};
2197	LLWU_P18_PTE10: llwu_p18_pte10 {
2198		/* < PIN PCR[MUX] > */
2199		nxp,kinetis-port-pins = < 10 1 >;
2200	};
2201	I2C3_SDA_PTE10: i2c3_sda_pte10 {
2202		/* < PIN PCR[MUX] > */
2203		nxp,kinetis-port-pins = < 10 2 >;
2204	};
2205	I2S0_TXD0_PTE10: i2s0_txd0_pte10 {
2206		/* < PIN PCR[MUX] > */
2207		nxp,kinetis-port-pins = < 10 4 >;
2208	};
2209	LPUART0_CTS_b_PTE10: lpuart0_cts_b_pte10 {
2210		/* < PIN PCR[MUX] > */
2211		nxp,kinetis-port-pins = < 10 5 >;
2212	};
2213	FTM3_CH5_PTE10: ftm3_ch5_pte10 {
2214		/* < PIN PCR[MUX] > */
2215		nxp,kinetis-port-pins = < 10 6 >;
2216	};
2217	USB1_ID_PTE10: usb1_id_pte10 {
2218		/* < PIN PCR[MUX] > */
2219		nxp,kinetis-port-pins = < 10 7 >;
2220	};
2221	PTE11: GPIOE_PTE11: gpioe_pte11 {
2222		/* < PIN PCR[MUX] > */
2223		nxp,kinetis-port-pins = < 11 1 >;
2224	};
2225	I2C3_SCL_PTE11: i2c3_scl_pte11 {
2226		/* < PIN PCR[MUX] > */
2227		nxp,kinetis-port-pins = < 11 2 >;
2228	};
2229	I2S0_TX_FS_PTE11: i2s0_tx_fs_pte11 {
2230		/* < PIN PCR[MUX] > */
2231		nxp,kinetis-port-pins = < 11 4 >;
2232	};
2233	LPUART0_RTS_b_PTE11: lpuart0_rts_b_pte11 {
2234		/* < PIN PCR[MUX] > */
2235		nxp,kinetis-port-pins = < 11 5 >;
2236	};
2237	FTM3_CH6_PTE11: ftm3_ch6_pte11 {
2238		/* < PIN PCR[MUX] > */
2239		nxp,kinetis-port-pins = < 11 6 >;
2240	};
2241	PTE12: GPIOE_PTE12: gpioe_pte12 {
2242		/* < PIN PCR[MUX] > */
2243		nxp,kinetis-port-pins = < 12 1 >;
2244	};
2245	I2S0_TX_BCLK_PTE12: i2s0_tx_bclk_pte12 {
2246		/* < PIN PCR[MUX] > */
2247		nxp,kinetis-port-pins = < 12 4 >;
2248	};
2249	FTM3_CH7_PTE12: ftm3_ch7_pte12 {
2250		/* < PIN PCR[MUX] > */
2251		nxp,kinetis-port-pins = < 12 6 >;
2252	};
2253	ADC0_SE17_PTE24: adc0_se17_pte24 {
2254		/* < PIN PCR[MUX] > */
2255		nxp,kinetis-port-pins = < 24 0 >;
2256	};
2257	PTE24: GPIOE_PTE24: gpioe_pte24 {
2258		/* < PIN PCR[MUX] > */
2259		nxp,kinetis-port-pins = < 24 1 >;
2260	};
2261	CAN1_TX_PTE24: can1_tx_pte24 {
2262		/* < PIN PCR[MUX] > */
2263		nxp,kinetis-port-pins = < 24 2 >;
2264	};
2265	UART4_TX_PTE24: uart4_tx_pte24 {
2266		/* < PIN PCR[MUX] > */
2267		nxp,kinetis-port-pins = < 24 3 >;
2268	};
2269	I2C0_SCL_PTE24: i2c0_scl_pte24 {
2270		/* < PIN PCR[MUX] > */
2271		nxp,kinetis-port-pins = < 24 5 >;
2272	};
2273	EWM_OUT_b_PTE24: ewm_out_b_pte24 {
2274		/* < PIN PCR[MUX] > */
2275		nxp,kinetis-port-pins = < 24 6 >;
2276	};
2277	ADC0_SE18_PTE25: adc0_se18_pte25 {
2278		/* < PIN PCR[MUX] > */
2279		nxp,kinetis-port-pins = < 25 0 >;
2280	};
2281	PTE25: GPIOE_PTE25: gpioe_pte25 {
2282		/* < PIN PCR[MUX] > */
2283		nxp,kinetis-port-pins = < 25 1 >;
2284	};
2285	LLWU_P21_PTE25: llwu_p21_pte25 {
2286		/* < PIN PCR[MUX] > */
2287		nxp,kinetis-port-pins = < 25 1 >;
2288	};
2289	CAN1_RX_PTE25: can1_rx_pte25 {
2290		/* < PIN PCR[MUX] > */
2291		nxp,kinetis-port-pins = < 25 2 >;
2292	};
2293	UART4_RX_PTE25: uart4_rx_pte25 {
2294		/* < PIN PCR[MUX] > */
2295		nxp,kinetis-port-pins = < 25 3 >;
2296	};
2297	I2C0_SDA_PTE25: i2c0_sda_pte25 {
2298		/* < PIN PCR[MUX] > */
2299		nxp,kinetis-port-pins = < 25 5 >;
2300	};
2301	EWM_IN_PTE25: ewm_in_pte25 {
2302		/* < PIN PCR[MUX] > */
2303		nxp,kinetis-port-pins = < 25 6 >;
2304	};
2305	PTE26: GPIOE_PTE26: gpioe_pte26 {
2306		/* < PIN PCR[MUX] > */
2307		nxp,kinetis-port-pins = < 26 1 >;
2308	};
2309	ENET_1588_CLKIN_PTE26: enet_1588_clkin_pte26 {
2310		/* < PIN PCR[MUX] > */
2311		nxp,kinetis-port-pins = < 26 2 >;
2312	};
2313	UART4_CTS_b_PTE26: uart4_cts_b_pte26 {
2314		/* < PIN PCR[MUX] > */
2315		nxp,kinetis-port-pins = < 26 3 >;
2316	};
2317	RTC_CLKOUT_PTE26: rtc_clkout_pte26 {
2318		/* < PIN PCR[MUX] > */
2319		nxp,kinetis-port-pins = < 26 6 >;
2320	};
2321	USB0_CLKIN_PTE26: usb0_clkin_pte26 {
2322		/* < PIN PCR[MUX] > */
2323		nxp,kinetis-port-pins = < 26 7 >;
2324	};
2325	PTE27: GPIOE_PTE27: gpioe_pte27 {
2326		/* < PIN PCR[MUX] > */
2327		nxp,kinetis-port-pins = < 27 1 >;
2328	};
2329	UART4_RTS_b_PTE27: uart4_rts_b_pte27 {
2330		/* < PIN PCR[MUX] > */
2331		nxp,kinetis-port-pins = < 27 3 >;
2332	};
2333	PTE28: GPIOE_PTE28: gpioe_pte28 {
2334		/* < PIN PCR[MUX] > */
2335		nxp,kinetis-port-pins = < 28 1 >;
2336	};
2337};
2338
2339