1/*
2 * NOTE: Autogenerated file by kinetis_signal2dts.py
3 *       for MK64FN1M0VDC12/signal_configuration.xml
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8/*
9 * Pin nodes are of the form:
10 *
11 *	<SIGNAL[0..n]>: <signal[0]> {
12 *		nxp,kinetis-port-pins = < PIN PCR[MUX] >;
13 *	};
14 */
15
16&porta {
17	PTA0: GPIOA_PTA0: gpioa_pta0 {
18		nxp,kinetis-port-pins = < 0 1 >;
19	};
20	UART0_CTS_b_PTA0: UART0_COL_b_PTA0: uart0_cts_b_pta0 {
21		nxp,kinetis-port-pins = < 0 2 >;
22	};
23	FTM0_CH5_PTA0: ftm0_ch5_pta0 {
24		nxp,kinetis-port-pins = < 0 3 >;
25	};
26	JTAG_TCLK_PTA0: jtag_tclk_pta0 {
27		nxp,kinetis-port-pins = < 0 7 >;
28	};
29	PTA1: GPIOA_PTA1: gpioa_pta1 {
30		nxp,kinetis-port-pins = < 1 1 >;
31	};
32	UART0_RX_PTA1: uart0_rx_pta1 {
33		nxp,kinetis-port-pins = < 1 2 >;
34	};
35	FTM0_CH6_PTA1: ftm0_ch6_pta1 {
36		nxp,kinetis-port-pins = < 1 3 >;
37	};
38	JTAG_TDI_PTA1: jtag_tdi_pta1 {
39		nxp,kinetis-port-pins = < 1 7 >;
40	};
41	PTA2: GPIOA_PTA2: gpioa_pta2 {
42		nxp,kinetis-port-pins = < 2 1 >;
43	};
44	UART0_TX_PTA2: uart0_tx_pta2 {
45		nxp,kinetis-port-pins = < 2 2 >;
46	};
47	FTM0_CH7_PTA2: ftm0_ch7_pta2 {
48		nxp,kinetis-port-pins = < 2 3 >;
49	};
50	JTAG_TDO_PTA2: TRACE_SWO_PTA2: jtag_tdo_pta2 {
51		nxp,kinetis-port-pins = < 2 7 >;
52	};
53	PTA3: GPIOA_PTA3: gpioa_pta3 {
54		nxp,kinetis-port-pins = < 3 1 >;
55	};
56	UART0_RTS_b_PTA3: uart0_rts_b_pta3 {
57		nxp,kinetis-port-pins = < 3 2 >;
58	};
59	FTM0_CH0_PTA3: ftm0_ch0_pta3 {
60		nxp,kinetis-port-pins = < 3 3 >;
61	};
62	JTAG_TMS_PTA3: jtag_tms_pta3 {
63		nxp,kinetis-port-pins = < 3 7 >;
64	};
65	PTA4: GPIOA_PTA4: LLWU_P3_PTA4: gpioa_pta4 {
66		nxp,kinetis-port-pins = < 4 1 >;
67	};
68	FTM0_CH1_PTA4: ftm0_ch1_pta4 {
69		nxp,kinetis-port-pins = < 4 3 >;
70	};
71	NMI_b_PTA4: nmi_b_pta4 {
72		nxp,kinetis-port-pins = < 4 7 >;
73	};
74	PTA5: GPIOA_PTA5: gpioa_pta5 {
75		nxp,kinetis-port-pins = < 5 1 >;
76	};
77	USB_CLKIN_PTA5: usb_clkin_pta5 {
78		nxp,kinetis-port-pins = < 5 2 >;
79	};
80	FTM0_CH2_PTA5: ftm0_ch2_pta5 {
81		nxp,kinetis-port-pins = < 5 3 >;
82	};
83	RMII0_RXER_PTA5: MII0_RXER_PTA5: rmii0_rxer_pta5 {
84		nxp,kinetis-port-pins = < 5 4 >;
85	};
86	CMP2_OUT_PTA5: cmp2_out_pta5 {
87		nxp,kinetis-port-pins = < 5 5 >;
88	};
89	I2S0_TX_BCLK_PTA5: i2s0_tx_bclk_pta5 {
90		nxp,kinetis-port-pins = < 5 6 >;
91	};
92	JTAG_TRST_b_PTA5: jtag_trst_b_pta5 {
93		nxp,kinetis-port-pins = < 5 7 >;
94	};
95	PTA10: GPIOA_PTA10: gpioa_pta10 {
96		nxp,kinetis-port-pins = < 10 1 >;
97	};
98	FTM2_CH0_PTA10: ftm2_ch0_pta10 {
99		nxp,kinetis-port-pins = < 10 3 >;
100	};
101	MII0_RXD2_PTA10: mii0_rxd2_pta10 {
102		nxp,kinetis-port-pins = < 10 4 >;
103	};
104	FTM2_QD_PHA_PTA10: ftm2_qd_pha_pta10 {
105		nxp,kinetis-port-pins = < 10 6 >;
106	};
107	TRACE_D0_PTA10: trace_d0_pta10 {
108		nxp,kinetis-port-pins = < 10 7 >;
109	};
110	PTA11: GPIOA_PTA11: gpioa_pta11 {
111		nxp,kinetis-port-pins = < 11 1 >;
112	};
113	FTM2_CH1_PTA11: ftm2_ch1_pta11 {
114		nxp,kinetis-port-pins = < 11 3 >;
115	};
116	MII0_RXCLK_PTA11: mii0_rxclk_pta11 {
117		nxp,kinetis-port-pins = < 11 4 >;
118	};
119	I2C2_SDA_PTA11: i2c2_sda_pta11 {
120		nxp,kinetis-port-pins = < 11 5 >;
121	};
122	FTM2_QD_PHB_PTA11: ftm2_qd_phb_pta11 {
123		nxp,kinetis-port-pins = < 11 6 >;
124	};
125	CMP2_IN0_PTA12: cmp2_in0_pta12 {
126		nxp,kinetis-port-pins = < 12 0 >;
127	};
128	PTA12: GPIOA_PTA12: gpioa_pta12 {
129		nxp,kinetis-port-pins = < 12 1 >;
130	};
131	CAN0_TX_PTA12: can0_tx_pta12 {
132		nxp,kinetis-port-pins = < 12 2 >;
133	};
134	FTM1_CH0_PTA12: ftm1_ch0_pta12 {
135		nxp,kinetis-port-pins = < 12 3 >;
136	};
137	RMII0_RXD1_PTA12: MII0_RXD1_PTA12: rmii0_rxd1_pta12 {
138		nxp,kinetis-port-pins = < 12 4 >;
139	};
140	I2C2_SCL_PTA12: i2c2_scl_pta12 {
141		nxp,kinetis-port-pins = < 12 5 >;
142	};
143	I2S0_TXD0_PTA12: i2s0_txd0_pta12 {
144		nxp,kinetis-port-pins = < 12 6 >;
145	};
146	FTM1_QD_PHA_PTA12: ftm1_qd_pha_pta12 {
147		nxp,kinetis-port-pins = < 12 7 >;
148	};
149	CMP2_IN1_PTA13: cmp2_in1_pta13 {
150		nxp,kinetis-port-pins = < 13 0 >;
151	};
152	PTA13: GPIOA_PTA13: LLWU_P4_PTA13: gpioa_pta13 {
153		nxp,kinetis-port-pins = < 13 1 >;
154	};
155	CAN0_RX_PTA13: can0_rx_pta13 {
156		nxp,kinetis-port-pins = < 13 2 >;
157	};
158	FTM1_CH1_PTA13: ftm1_ch1_pta13 {
159		nxp,kinetis-port-pins = < 13 3 >;
160	};
161	RMII0_RXD0_PTA13: MII0_RXD0_PTA13: rmii0_rxd0_pta13 {
162		nxp,kinetis-port-pins = < 13 4 >;
163	};
164	I2C2_SDA_PTA13: i2c2_sda_pta13 {
165		nxp,kinetis-port-pins = < 13 5 >;
166	};
167	I2S0_TX_FS_PTA13: i2s0_tx_fs_pta13 {
168		nxp,kinetis-port-pins = < 13 6 >;
169	};
170	FTM1_QD_PHB_PTA13: ftm1_qd_phb_pta13 {
171		nxp,kinetis-port-pins = < 13 7 >;
172	};
173	PTA14: GPIOA_PTA14: gpioa_pta14 {
174		nxp,kinetis-port-pins = < 14 1 >;
175	};
176	SPI0_PCS0_PTA14: spi0_pcs0_pta14 {
177		nxp,kinetis-port-pins = < 14 2 >;
178	};
179	UART0_TX_PTA14: uart0_tx_pta14 {
180		nxp,kinetis-port-pins = < 14 3 >;
181	};
182	RMII0_CRS_DV_PTA14: MII0_RXDV_PTA14: rmii0_crs_dv_pta14 {
183		nxp,kinetis-port-pins = < 14 4 >;
184	};
185	I2C2_SCL_PTA14: i2c2_scl_pta14 {
186		nxp,kinetis-port-pins = < 14 5 >;
187	};
188	I2S0_RX_BCLK_PTA14: i2s0_rx_bclk_pta14 {
189		nxp,kinetis-port-pins = < 14 6 >;
190	};
191	I2S0_TXD1_PTA14: i2s0_txd1_pta14 {
192		nxp,kinetis-port-pins = < 14 7 >;
193	};
194	PTA15: GPIOA_PTA15: gpioa_pta15 {
195		nxp,kinetis-port-pins = < 15 1 >;
196	};
197	SPI0_SCK_PTA15: spi0_sck_pta15 {
198		nxp,kinetis-port-pins = < 15 2 >;
199	};
200	UART0_RX_PTA15: uart0_rx_pta15 {
201		nxp,kinetis-port-pins = < 15 3 >;
202	};
203	RMII0_TXEN_PTA15: MII0_TXEN_PTA15: rmii0_txen_pta15 {
204		nxp,kinetis-port-pins = < 15 4 >;
205	};
206	I2S0_RXD0_PTA15: i2s0_rxd0_pta15 {
207		nxp,kinetis-port-pins = < 15 6 >;
208	};
209	PTA16: GPIOA_PTA16: gpioa_pta16 {
210		nxp,kinetis-port-pins = < 16 1 >;
211	};
212	SPI0_SOUT_PTA16: spi0_sout_pta16 {
213		nxp,kinetis-port-pins = < 16 2 >;
214	};
215	UART0_CTS_b_PTA16: UART0_COL_b_PTA16: uart0_cts_b_pta16 {
216		nxp,kinetis-port-pins = < 16 3 >;
217	};
218	RMII0_TXD0_PTA16: MII0_TXD0_PTA16: rmii0_txd0_pta16 {
219		nxp,kinetis-port-pins = < 16 4 >;
220	};
221	I2S0_RX_FS_PTA16: i2s0_rx_fs_pta16 {
222		nxp,kinetis-port-pins = < 16 6 >;
223	};
224	I2S0_RXD1_PTA16: i2s0_rxd1_pta16 {
225		nxp,kinetis-port-pins = < 16 7 >;
226	};
227	ADC1_SE17_PTA17: adc1_se17_pta17 {
228		nxp,kinetis-port-pins = < 17 0 >;
229	};
230	PTA17: GPIOA_PTA17: gpioa_pta17 {
231		nxp,kinetis-port-pins = < 17 1 >;
232	};
233	SPI0_SIN_PTA17: spi0_sin_pta17 {
234		nxp,kinetis-port-pins = < 17 2 >;
235	};
236	UART0_RTS_b_PTA17: uart0_rts_b_pta17 {
237		nxp,kinetis-port-pins = < 17 3 >;
238	};
239	RMII0_TXD1_PTA17: MII0_TXD1_PTA17: rmii0_txd1_pta17 {
240		nxp,kinetis-port-pins = < 17 4 >;
241	};
242	I2S0_MCLK_PTA17: i2s0_mclk_pta17 {
243		nxp,kinetis-port-pins = < 17 6 >;
244	};
245	EXTAL0_PTA18: extal0_pta18 {
246		nxp,kinetis-port-pins = < 18 0 >;
247	};
248	PTA18: GPIOA_PTA18: gpioa_pta18 {
249		nxp,kinetis-port-pins = < 18 1 >;
250	};
251	FTM0_FLT2_PTA18: ftm0_flt2_pta18 {
252		nxp,kinetis-port-pins = < 18 3 >;
253	};
254	FTM_CLKIN0_PTA18: ftm_clkin0_pta18 {
255		nxp,kinetis-port-pins = < 18 4 >;
256	};
257	XTAL0_PTA19: xtal0_pta19 {
258		nxp,kinetis-port-pins = < 19 0 >;
259	};
260	PTA19: GPIOA_PTA19: gpioa_pta19 {
261		nxp,kinetis-port-pins = < 19 1 >;
262	};
263	FTM1_FLT0_PTA19: ftm1_flt0_pta19 {
264		nxp,kinetis-port-pins = < 19 3 >;
265	};
266	FTM_CLKIN1_PTA19: ftm_clkin1_pta19 {
267		nxp,kinetis-port-pins = < 19 4 >;
268	};
269	LPTMR0_ALT1_PTA19: lptmr0_alt1_pta19 {
270		nxp,kinetis-port-pins = < 19 6 >;
271	};
272	PTA29: GPIOA_PTA29: gpioa_pta29 {
273		nxp,kinetis-port-pins = < 29 1 >;
274	};
275	MII0_COL_PTA29: mii0_col_pta29 {
276		nxp,kinetis-port-pins = < 29 4 >;
277	};
278};
279
280&portb {
281	ADC0_SE8_PTB0: ADC1_SE8_PTB0: adc0_se8_ptb0 {
282		nxp,kinetis-port-pins = < 0 0 >;
283	};
284	PTB0: GPIOB_PTB0: LLWU_P5_PTB0: gpiob_ptb0 {
285		nxp,kinetis-port-pins = < 0 1 >;
286	};
287	I2C0_SCL_PTB0: i2c0_scl_ptb0 {
288		nxp,kinetis-port-pins = < 0 2 >;
289	};
290	FTM1_CH0_PTB0: ftm1_ch0_ptb0 {
291		nxp,kinetis-port-pins = < 0 3 >;
292	};
293	RMII0_MDIO_PTB0: MII0_MDIO_PTB0: rmii0_mdio_ptb0 {
294		nxp,kinetis-port-pins = < 0 4 >;
295	};
296	FTM1_QD_PHA_PTB0: ftm1_qd_pha_ptb0 {
297		nxp,kinetis-port-pins = < 0 6 >;
298	};
299	ADC0_SE9_PTB1: ADC1_SE9_PTB1: adc0_se9_ptb1 {
300		nxp,kinetis-port-pins = < 1 0 >;
301	};
302	PTB1: GPIOB_PTB1: gpiob_ptb1 {
303		nxp,kinetis-port-pins = < 1 1 >;
304	};
305	I2C0_SDA_PTB1: i2c0_sda_ptb1 {
306		nxp,kinetis-port-pins = < 1 2 >;
307	};
308	FTM1_CH1_PTB1: ftm1_ch1_ptb1 {
309		nxp,kinetis-port-pins = < 1 3 >;
310	};
311	RMII0_MDC_PTB1: MII0_MDC_PTB1: rmii0_mdc_ptb1 {
312		nxp,kinetis-port-pins = < 1 4 >;
313	};
314	FTM1_QD_PHB_PTB1: ftm1_qd_phb_ptb1 {
315		nxp,kinetis-port-pins = < 1 6 >;
316	};
317	ADC0_SE12_PTB2: adc0_se12_ptb2 {
318		nxp,kinetis-port-pins = < 2 0 >;
319	};
320	PTB2: GPIOB_PTB2: gpiob_ptb2 {
321		nxp,kinetis-port-pins = < 2 1 >;
322	};
323	I2C0_SCL_PTB2: i2c0_scl_ptb2 {
324		nxp,kinetis-port-pins = < 2 2 >;
325	};
326	UART0_RTS_b_PTB2: uart0_rts_b_ptb2 {
327		nxp,kinetis-port-pins = < 2 3 >;
328	};
329	ENET0_1588_TMR0_PTB2: enet0_1588_tmr0_ptb2 {
330		nxp,kinetis-port-pins = < 2 4 >;
331	};
332	FTM0_FLT3_PTB2: ftm0_flt3_ptb2 {
333		nxp,kinetis-port-pins = < 2 6 >;
334	};
335	ADC0_SE13_PTB3: adc0_se13_ptb3 {
336		nxp,kinetis-port-pins = < 3 0 >;
337	};
338	PTB3: GPIOB_PTB3: gpiob_ptb3 {
339		nxp,kinetis-port-pins = < 3 1 >;
340	};
341	I2C0_SDA_PTB3: i2c0_sda_ptb3 {
342		nxp,kinetis-port-pins = < 3 2 >;
343	};
344	UART0_CTS_b_PTB3: UART0_COL_b_PTB3: uart0_cts_b_ptb3 {
345		nxp,kinetis-port-pins = < 3 3 >;
346	};
347	ENET0_1588_TMR1_PTB3: enet0_1588_tmr1_ptb3 {
348		nxp,kinetis-port-pins = < 3 4 >;
349	};
350	FTM0_FLT0_PTB3: ftm0_flt0_ptb3 {
351		nxp,kinetis-port-pins = < 3 6 >;
352	};
353	ADC1_SE12_PTB6: adc1_se12_ptb6 {
354		nxp,kinetis-port-pins = < 6 0 >;
355	};
356	PTB6: GPIOB_PTB6: gpiob_ptb6 {
357		nxp,kinetis-port-pins = < 6 1 >;
358	};
359	ADC1_SE13_PTB7: adc1_se13_ptb7 {
360		nxp,kinetis-port-pins = < 7 0 >;
361	};
362	PTB7: GPIOB_PTB7: gpiob_ptb7 {
363		nxp,kinetis-port-pins = < 7 1 >;
364	};
365	PTB8: GPIOB_PTB8: gpiob_ptb8 {
366		nxp,kinetis-port-pins = < 8 1 >;
367	};
368	UART3_RTS_b_PTB8: uart3_rts_b_ptb8 {
369		nxp,kinetis-port-pins = < 8 3 >;
370	};
371	PTB9: GPIOB_PTB9: gpiob_ptb9 {
372		nxp,kinetis-port-pins = < 9 1 >;
373	};
374	SPI1_PCS1_PTB9: spi1_pcs1_ptb9 {
375		nxp,kinetis-port-pins = < 9 2 >;
376	};
377	UART3_CTS_b_PTB9: uart3_cts_b_ptb9 {
378		nxp,kinetis-port-pins = < 9 3 >;
379	};
380	ADC1_SE14_PTB10: adc1_se14_ptb10 {
381		nxp,kinetis-port-pins = < 10 0 >;
382	};
383	PTB10: GPIOB_PTB10: gpiob_ptb10 {
384		nxp,kinetis-port-pins = < 10 1 >;
385	};
386	SPI1_PCS0_PTB10: spi1_pcs0_ptb10 {
387		nxp,kinetis-port-pins = < 10 2 >;
388	};
389	UART3_RX_PTB10: uart3_rx_ptb10 {
390		nxp,kinetis-port-pins = < 10 3 >;
391	};
392	FTM0_FLT1_PTB10: ftm0_flt1_ptb10 {
393		nxp,kinetis-port-pins = < 10 6 >;
394	};
395	ADC1_SE15_PTB11: adc1_se15_ptb11 {
396		nxp,kinetis-port-pins = < 11 0 >;
397	};
398	PTB11: GPIOB_PTB11: gpiob_ptb11 {
399		nxp,kinetis-port-pins = < 11 1 >;
400	};
401	SPI1_SCK_PTB11: spi1_sck_ptb11 {
402		nxp,kinetis-port-pins = < 11 2 >;
403	};
404	UART3_TX_PTB11: uart3_tx_ptb11 {
405		nxp,kinetis-port-pins = < 11 3 >;
406	};
407	FTM0_FLT2_PTB11: ftm0_flt2_ptb11 {
408		nxp,kinetis-port-pins = < 11 6 >;
409	};
410	PTB12: GPIOB_PTB12: gpiob_ptb12 {
411		nxp,kinetis-port-pins = < 12 1 >;
412	};
413	UART3_RTS_b_PTB12: uart3_rts_b_ptb12 {
414		nxp,kinetis-port-pins = < 12 2 >;
415	};
416	FTM1_CH0_PTB12: ftm1_ch0_ptb12 {
417		nxp,kinetis-port-pins = < 12 3 >;
418	};
419	FTM0_CH4_PTB12: ftm0_ch4_ptb12 {
420		nxp,kinetis-port-pins = < 12 4 >;
421	};
422	FTM1_QD_PHA_PTB12: ftm1_qd_pha_ptb12 {
423		nxp,kinetis-port-pins = < 12 6 >;
424	};
425	PTB13: GPIOB_PTB13: gpiob_ptb13 {
426		nxp,kinetis-port-pins = < 13 1 >;
427	};
428	UART3_CTS_b_PTB13: uart3_cts_b_ptb13 {
429		nxp,kinetis-port-pins = < 13 2 >;
430	};
431	FTM1_CH1_PTB13: ftm1_ch1_ptb13 {
432		nxp,kinetis-port-pins = < 13 3 >;
433	};
434	FTM0_CH5_PTB13: ftm0_ch5_ptb13 {
435		nxp,kinetis-port-pins = < 13 4 >;
436	};
437	FTM1_QD_PHB_PTB13: ftm1_qd_phb_ptb13 {
438		nxp,kinetis-port-pins = < 13 6 >;
439	};
440	PTB16: GPIOB_PTB16: gpiob_ptb16 {
441		nxp,kinetis-port-pins = < 16 1 >;
442	};
443	SPI1_SOUT_PTB16: spi1_sout_ptb16 {
444		nxp,kinetis-port-pins = < 16 2 >;
445	};
446	UART0_RX_PTB16: uart0_rx_ptb16 {
447		nxp,kinetis-port-pins = < 16 3 >;
448	};
449	FTM_CLKIN0_PTB16: ftm_clkin0_ptb16 {
450		nxp,kinetis-port-pins = < 16 4 >;
451	};
452	EWM_IN_PTB16: ewm_in_ptb16 {
453		nxp,kinetis-port-pins = < 16 6 >;
454	};
455	PTB17: GPIOB_PTB17: gpiob_ptb17 {
456		nxp,kinetis-port-pins = < 17 1 >;
457	};
458	SPI1_SIN_PTB17: spi1_sin_ptb17 {
459		nxp,kinetis-port-pins = < 17 2 >;
460	};
461	UART0_TX_PTB17: uart0_tx_ptb17 {
462		nxp,kinetis-port-pins = < 17 3 >;
463	};
464	FTM_CLKIN1_PTB17: ftm_clkin1_ptb17 {
465		nxp,kinetis-port-pins = < 17 4 >;
466	};
467	EWM_OUT_b_PTB17: ewm_out_b_ptb17 {
468		nxp,kinetis-port-pins = < 17 6 >;
469	};
470	PTB18: GPIOB_PTB18: gpiob_ptb18 {
471		nxp,kinetis-port-pins = < 18 1 >;
472	};
473	CAN0_TX_PTB18: can0_tx_ptb18 {
474		nxp,kinetis-port-pins = < 18 2 >;
475	};
476	FTM2_CH0_PTB18: ftm2_ch0_ptb18 {
477		nxp,kinetis-port-pins = < 18 3 >;
478	};
479	I2S0_TX_BCLK_PTB18: i2s0_tx_bclk_ptb18 {
480		nxp,kinetis-port-pins = < 18 4 >;
481	};
482	FTM2_QD_PHA_PTB18: ftm2_qd_pha_ptb18 {
483		nxp,kinetis-port-pins = < 18 6 >;
484	};
485	PTB19: GPIOB_PTB19: gpiob_ptb19 {
486		nxp,kinetis-port-pins = < 19 1 >;
487	};
488	CAN0_RX_PTB19: can0_rx_ptb19 {
489		nxp,kinetis-port-pins = < 19 2 >;
490	};
491	FTM2_CH1_PTB19: ftm2_ch1_ptb19 {
492		nxp,kinetis-port-pins = < 19 3 >;
493	};
494	I2S0_TX_FS_PTB19: i2s0_tx_fs_ptb19 {
495		nxp,kinetis-port-pins = < 19 4 >;
496	};
497	FTM2_QD_PHB_PTB19: ftm2_qd_phb_ptb19 {
498		nxp,kinetis-port-pins = < 19 6 >;
499	};
500	PTB20: GPIOB_PTB20: gpiob_ptb20 {
501		nxp,kinetis-port-pins = < 20 1 >;
502	};
503	SPI2_PCS0_PTB20: spi2_pcs0_ptb20 {
504		nxp,kinetis-port-pins = < 20 2 >;
505	};
506	CMP0_OUT_PTB20: cmp0_out_ptb20 {
507		nxp,kinetis-port-pins = < 20 6 >;
508	};
509	PTB21: GPIOB_PTB21: gpiob_ptb21 {
510		nxp,kinetis-port-pins = < 21 1 >;
511	};
512	SPI2_SCK_PTB21: spi2_sck_ptb21 {
513		nxp,kinetis-port-pins = < 21 2 >;
514	};
515	CMP1_OUT_PTB21: cmp1_out_ptb21 {
516		nxp,kinetis-port-pins = < 21 6 >;
517	};
518	PTB22: GPIOB_PTB22: gpiob_ptb22 {
519		nxp,kinetis-port-pins = < 22 1 >;
520	};
521	SPI2_SOUT_PTB22: spi2_sout_ptb22 {
522		nxp,kinetis-port-pins = < 22 2 >;
523	};
524	CMP2_OUT_PTB22: cmp2_out_ptb22 {
525		nxp,kinetis-port-pins = < 22 6 >;
526	};
527	PTB23: GPIOB_PTB23: gpiob_ptb23 {
528		nxp,kinetis-port-pins = < 23 1 >;
529	};
530	SPI2_SIN_PTB23: spi2_sin_ptb23 {
531		nxp,kinetis-port-pins = < 23 2 >;
532	};
533	SPI0_PCS5_PTB23: spi0_pcs5_ptb23 {
534		nxp,kinetis-port-pins = < 23 3 >;
535	};
536};
537
538&portc {
539	ADC0_SE14_PTC0: adc0_se14_ptc0 {
540		nxp,kinetis-port-pins = < 0 0 >;
541	};
542	PTC0: GPIOC_PTC0: gpioc_ptc0 {
543		nxp,kinetis-port-pins = < 0 1 >;
544	};
545	SPI0_PCS4_PTC0: spi0_pcs4_ptc0 {
546		nxp,kinetis-port-pins = < 0 2 >;
547	};
548	PDB0_EXTRG_PTC0: pdb0_extrg_ptc0 {
549		nxp,kinetis-port-pins = < 0 3 >;
550	};
551	USB_SOF_OUT_PTC0: usb_sof_out_ptc0 {
552		nxp,kinetis-port-pins = < 0 4 >;
553	};
554	I2S0_TXD1_PTC0: i2s0_txd1_ptc0 {
555		nxp,kinetis-port-pins = < 0 6 >;
556	};
557	ADC0_SE15_PTC1: adc0_se15_ptc1 {
558		nxp,kinetis-port-pins = < 1 0 >;
559	};
560	PTC1: GPIOC_PTC1: LLWU_P6_PTC1: gpioc_ptc1 {
561		nxp,kinetis-port-pins = < 1 1 >;
562	};
563	SPI0_PCS3_PTC1: spi0_pcs3_ptc1 {
564		nxp,kinetis-port-pins = < 1 2 >;
565	};
566	UART1_RTS_b_PTC1: uart1_rts_b_ptc1 {
567		nxp,kinetis-port-pins = < 1 3 >;
568	};
569	FTM0_CH0_PTC1: ftm0_ch0_ptc1 {
570		nxp,kinetis-port-pins = < 1 4 >;
571	};
572	I2S0_TXD0_PTC1: i2s0_txd0_ptc1 {
573		nxp,kinetis-port-pins = < 1 6 >;
574	};
575	ADC0_SE4b_PTC2: CMP1_IN0_PTC2: adc0_se4b_ptc2 {
576		nxp,kinetis-port-pins = < 2 0 >;
577	};
578	PTC2: GPIOC_PTC2: gpioc_ptc2 {
579		nxp,kinetis-port-pins = < 2 1 >;
580	};
581	SPI0_PCS2_PTC2: spi0_pcs2_ptc2 {
582		nxp,kinetis-port-pins = < 2 2 >;
583	};
584	UART1_CTS_b_PTC2: uart1_cts_b_ptc2 {
585		nxp,kinetis-port-pins = < 2 3 >;
586	};
587	FTM0_CH1_PTC2: ftm0_ch1_ptc2 {
588		nxp,kinetis-port-pins = < 2 4 >;
589	};
590	I2S0_TX_FS_PTC2: i2s0_tx_fs_ptc2 {
591		nxp,kinetis-port-pins = < 2 6 >;
592	};
593	CMP1_IN1_PTC3: cmp1_in1_ptc3 {
594		nxp,kinetis-port-pins = < 3 0 >;
595	};
596	PTC3: GPIOC_PTC3: LLWU_P7_PTC3: gpioc_ptc3 {
597		nxp,kinetis-port-pins = < 3 1 >;
598	};
599	SPI0_PCS1_PTC3: spi0_pcs1_ptc3 {
600		nxp,kinetis-port-pins = < 3 2 >;
601	};
602	UART1_RX_PTC3: uart1_rx_ptc3 {
603		nxp,kinetis-port-pins = < 3 3 >;
604	};
605	FTM0_CH2_PTC3: ftm0_ch2_ptc3 {
606		nxp,kinetis-port-pins = < 3 4 >;
607	};
608	CLKOUT_PTC3: clkout_ptc3 {
609		nxp,kinetis-port-pins = < 3 5 >;
610	};
611	I2S0_TX_BCLK_PTC3: i2s0_tx_bclk_ptc3 {
612		nxp,kinetis-port-pins = < 3 6 >;
613	};
614	PTC4: GPIOC_PTC4: LLWU_P8_PTC4: gpioc_ptc4 {
615		nxp,kinetis-port-pins = < 4 1 >;
616	};
617	SPI0_PCS0_PTC4: spi0_pcs0_ptc4 {
618		nxp,kinetis-port-pins = < 4 2 >;
619	};
620	UART1_TX_PTC4: uart1_tx_ptc4 {
621		nxp,kinetis-port-pins = < 4 3 >;
622	};
623	FTM0_CH3_PTC4: ftm0_ch3_ptc4 {
624		nxp,kinetis-port-pins = < 4 4 >;
625	};
626	CMP1_OUT_PTC4: cmp1_out_ptc4 {
627		nxp,kinetis-port-pins = < 4 6 >;
628	};
629	PTC5: GPIOC_PTC5: LLWU_P9_PTC5: gpioc_ptc5 {
630		nxp,kinetis-port-pins = < 5 1 >;
631	};
632	SPI0_SCK_PTC5: spi0_sck_ptc5 {
633		nxp,kinetis-port-pins = < 5 2 >;
634	};
635	LPTMR0_ALT2_PTC5: lptmr0_alt2_ptc5 {
636		nxp,kinetis-port-pins = < 5 3 >;
637	};
638	I2S0_RXD0_PTC5: i2s0_rxd0_ptc5 {
639		nxp,kinetis-port-pins = < 5 4 >;
640	};
641	CMP0_OUT_PTC5: cmp0_out_ptc5 {
642		nxp,kinetis-port-pins = < 5 6 >;
643	};
644	FTM0_CH2_PTC5: ftm0_ch2_ptc5 {
645		nxp,kinetis-port-pins = < 5 7 >;
646	};
647	CMP0_IN0_PTC6: cmp0_in0_ptc6 {
648		nxp,kinetis-port-pins = < 6 0 >;
649	};
650	PTC6: GPIOC_PTC6: LLWU_P10_PTC6: gpioc_ptc6 {
651		nxp,kinetis-port-pins = < 6 1 >;
652	};
653	SPI0_SOUT_PTC6: spi0_sout_ptc6 {
654		nxp,kinetis-port-pins = < 6 2 >;
655	};
656	PDB0_EXTRG_PTC6: pdb0_extrg_ptc6 {
657		nxp,kinetis-port-pins = < 6 3 >;
658	};
659	I2S0_RX_BCLK_PTC6: i2s0_rx_bclk_ptc6 {
660		nxp,kinetis-port-pins = < 6 4 >;
661	};
662	I2S0_MCLK_PTC6: i2s0_mclk_ptc6 {
663		nxp,kinetis-port-pins = < 6 6 >;
664	};
665	CMP0_IN1_PTC7: cmp0_in1_ptc7 {
666		nxp,kinetis-port-pins = < 7 0 >;
667	};
668	PTC7: GPIOC_PTC7: gpioc_ptc7 {
669		nxp,kinetis-port-pins = < 7 1 >;
670	};
671	SPI0_SIN_PTC7: spi0_sin_ptc7 {
672		nxp,kinetis-port-pins = < 7 2 >;
673	};
674	USB_SOF_OUT_PTC7: usb_sof_out_ptc7 {
675		nxp,kinetis-port-pins = < 7 3 >;
676	};
677	I2S0_RX_FS_PTC7: i2s0_rx_fs_ptc7 {
678		nxp,kinetis-port-pins = < 7 4 >;
679	};
680	ADC1_SE4b_PTC8: CMP0_IN2_PTC8: adc1_se4b_ptc8 {
681		nxp,kinetis-port-pins = < 8 0 >;
682	};
683	PTC8: GPIOC_PTC8: gpioc_ptc8 {
684		nxp,kinetis-port-pins = < 8 1 >;
685	};
686	FTM3_CH4_PTC8: ftm3_ch4_ptc8 {
687		nxp,kinetis-port-pins = < 8 3 >;
688	};
689	I2S0_MCLK_PTC8: i2s0_mclk_ptc8 {
690		nxp,kinetis-port-pins = < 8 4 >;
691	};
692	ADC1_SE5b_PTC9: CMP0_IN3_PTC9: adc1_se5b_ptc9 {
693		nxp,kinetis-port-pins = < 9 0 >;
694	};
695	PTC9: GPIOC_PTC9: gpioc_ptc9 {
696		nxp,kinetis-port-pins = < 9 1 >;
697	};
698	FTM3_CH5_PTC9: ftm3_ch5_ptc9 {
699		nxp,kinetis-port-pins = < 9 3 >;
700	};
701	I2S0_RX_BCLK_PTC9: i2s0_rx_bclk_ptc9 {
702		nxp,kinetis-port-pins = < 9 4 >;
703	};
704	FTM2_FLT0_PTC9: ftm2_flt0_ptc9 {
705		nxp,kinetis-port-pins = < 9 6 >;
706	};
707	ADC1_SE6b_PTC10: adc1_se6b_ptc10 {
708		nxp,kinetis-port-pins = < 10 0 >;
709	};
710	PTC10: GPIOC_PTC10: gpioc_ptc10 {
711		nxp,kinetis-port-pins = < 10 1 >;
712	};
713	I2C1_SCL_PTC10: i2c1_scl_ptc10 {
714		nxp,kinetis-port-pins = < 10 2 >;
715	};
716	FTM3_CH6_PTC10: ftm3_ch6_ptc10 {
717		nxp,kinetis-port-pins = < 10 3 >;
718	};
719	I2S0_RX_FS_PTC10: i2s0_rx_fs_ptc10 {
720		nxp,kinetis-port-pins = < 10 4 >;
721	};
722	ADC1_SE7b_PTC11: adc1_se7b_ptc11 {
723		nxp,kinetis-port-pins = < 11 0 >;
724	};
725	PTC11: GPIOC_PTC11: LLWU_P11_PTC11: gpioc_ptc11 {
726		nxp,kinetis-port-pins = < 11 1 >;
727	};
728	I2C1_SDA_PTC11: i2c1_sda_ptc11 {
729		nxp,kinetis-port-pins = < 11 2 >;
730	};
731	FTM3_CH7_PTC11: ftm3_ch7_ptc11 {
732		nxp,kinetis-port-pins = < 11 3 >;
733	};
734	I2S0_RXD1_PTC11: i2s0_rxd1_ptc11 {
735		nxp,kinetis-port-pins = < 11 4 >;
736	};
737	PTC12: GPIOC_PTC12: gpioc_ptc12 {
738		nxp,kinetis-port-pins = < 12 1 >;
739	};
740	UART4_RTS_b_PTC12: uart4_rts_b_ptc12 {
741		nxp,kinetis-port-pins = < 12 3 >;
742	};
743	FTM3_FLT0_PTC12: ftm3_flt0_ptc12 {
744		nxp,kinetis-port-pins = < 12 6 >;
745	};
746	PTC13: GPIOC_PTC13: gpioc_ptc13 {
747		nxp,kinetis-port-pins = < 13 1 >;
748	};
749	UART4_CTS_b_PTC13: uart4_cts_b_ptc13 {
750		nxp,kinetis-port-pins = < 13 3 >;
751	};
752	PTC14: GPIOC_PTC14: gpioc_ptc14 {
753		nxp,kinetis-port-pins = < 14 1 >;
754	};
755	UART4_RX_PTC14: uart4_rx_ptc14 {
756		nxp,kinetis-port-pins = < 14 3 >;
757	};
758	PTC15: GPIOC_PTC15: gpioc_ptc15 {
759		nxp,kinetis-port-pins = < 15 1 >;
760	};
761	UART4_TX_PTC15: uart4_tx_ptc15 {
762		nxp,kinetis-port-pins = < 15 3 >;
763	};
764	PTC16: GPIOC_PTC16: gpioc_ptc16 {
765		nxp,kinetis-port-pins = < 16 1 >;
766	};
767	UART3_RX_PTC16: uart3_rx_ptc16 {
768		nxp,kinetis-port-pins = < 16 3 >;
769	};
770	ENET0_1588_TMR0_PTC16: enet0_1588_tmr0_ptc16 {
771		nxp,kinetis-port-pins = < 16 4 >;
772	};
773	PTC17: GPIOC_PTC17: gpioc_ptc17 {
774		nxp,kinetis-port-pins = < 17 1 >;
775	};
776	UART3_TX_PTC17: uart3_tx_ptc17 {
777		nxp,kinetis-port-pins = < 17 3 >;
778	};
779	ENET0_1588_TMR1_PTC17: enet0_1588_tmr1_ptc17 {
780		nxp,kinetis-port-pins = < 17 4 >;
781	};
782	PTC18: GPIOC_PTC18: gpioc_ptc18 {
783		nxp,kinetis-port-pins = < 18 1 >;
784	};
785	UART3_RTS_b_PTC18: uart3_rts_b_ptc18 {
786		nxp,kinetis-port-pins = < 18 3 >;
787	};
788	ENET0_1588_TMR2_PTC18: enet0_1588_tmr2_ptc18 {
789		nxp,kinetis-port-pins = < 18 4 >;
790	};
791	PTC19: GPIOC_PTC19: gpioc_ptc19 {
792		nxp,kinetis-port-pins = < 19 1 >;
793	};
794	UART3_CTS_b_PTC19: uart3_cts_b_ptc19 {
795		nxp,kinetis-port-pins = < 19 3 >;
796	};
797	ENET0_1588_TMR3_PTC19: enet0_1588_tmr3_ptc19 {
798		nxp,kinetis-port-pins = < 19 4 >;
799	};
800};
801
802&portd {
803	PTD0: GPIOD_PTD0: LLWU_P12_PTD0: gpiod_ptd0 {
804		nxp,kinetis-port-pins = < 0 1 >;
805	};
806	SPI0_PCS0_PTD0: spi0_pcs0_ptd0 {
807		nxp,kinetis-port-pins = < 0 2 >;
808	};
809	UART2_RTS_b_PTD0: uart2_rts_b_ptd0 {
810		nxp,kinetis-port-pins = < 0 3 >;
811	};
812	FTM3_CH0_PTD0: ftm3_ch0_ptd0 {
813		nxp,kinetis-port-pins = < 0 4 >;
814	};
815	ADC0_SE5b_PTD1: adc0_se5b_ptd1 {
816		nxp,kinetis-port-pins = < 1 0 >;
817	};
818	PTD1: GPIOD_PTD1: gpiod_ptd1 {
819		nxp,kinetis-port-pins = < 1 1 >;
820	};
821	SPI0_SCK_PTD1: spi0_sck_ptd1 {
822		nxp,kinetis-port-pins = < 1 2 >;
823	};
824	UART2_CTS_b_PTD1: uart2_cts_b_ptd1 {
825		nxp,kinetis-port-pins = < 1 3 >;
826	};
827	FTM3_CH1_PTD1: ftm3_ch1_ptd1 {
828		nxp,kinetis-port-pins = < 1 4 >;
829	};
830	PTD2: GPIOD_PTD2: LLWU_P13_PTD2: gpiod_ptd2 {
831		nxp,kinetis-port-pins = < 2 1 >;
832	};
833	SPI0_SOUT_PTD2: spi0_sout_ptd2 {
834		nxp,kinetis-port-pins = < 2 2 >;
835	};
836	UART2_RX_PTD2: uart2_rx_ptd2 {
837		nxp,kinetis-port-pins = < 2 3 >;
838	};
839	FTM3_CH2_PTD2: ftm3_ch2_ptd2 {
840		nxp,kinetis-port-pins = < 2 4 >;
841	};
842	I2C0_SCL_PTD2: i2c0_scl_ptd2 {
843		nxp,kinetis-port-pins = < 2 7 >;
844	};
845	PTD3: GPIOD_PTD3: gpiod_ptd3 {
846		nxp,kinetis-port-pins = < 3 1 >;
847	};
848	SPI0_SIN_PTD3: spi0_sin_ptd3 {
849		nxp,kinetis-port-pins = < 3 2 >;
850	};
851	UART2_TX_PTD3: uart2_tx_ptd3 {
852		nxp,kinetis-port-pins = < 3 3 >;
853	};
854	FTM3_CH3_PTD3: ftm3_ch3_ptd3 {
855		nxp,kinetis-port-pins = < 3 4 >;
856	};
857	I2C0_SDA_PTD3: i2c0_sda_ptd3 {
858		nxp,kinetis-port-pins = < 3 7 >;
859	};
860	PTD4: GPIOD_PTD4: LLWU_P14_PTD4: gpiod_ptd4 {
861		nxp,kinetis-port-pins = < 4 1 >;
862	};
863	SPI0_PCS1_PTD4: spi0_pcs1_ptd4 {
864		nxp,kinetis-port-pins = < 4 2 >;
865	};
866	UART0_RTS_b_PTD4: uart0_rts_b_ptd4 {
867		nxp,kinetis-port-pins = < 4 3 >;
868	};
869	FTM0_CH4_PTD4: ftm0_ch4_ptd4 {
870		nxp,kinetis-port-pins = < 4 4 >;
871	};
872	EWM_IN_PTD4: ewm_in_ptd4 {
873		nxp,kinetis-port-pins = < 4 6 >;
874	};
875	SPI1_PCS0_PTD4: spi1_pcs0_ptd4 {
876		nxp,kinetis-port-pins = < 4 7 >;
877	};
878	ADC0_SE6b_PTD5: adc0_se6b_ptd5 {
879		nxp,kinetis-port-pins = < 5 0 >;
880	};
881	PTD5: GPIOD_PTD5: gpiod_ptd5 {
882		nxp,kinetis-port-pins = < 5 1 >;
883	};
884	SPI0_PCS2_PTD5: spi0_pcs2_ptd5 {
885		nxp,kinetis-port-pins = < 5 2 >;
886	};
887	UART0_CTS_b_PTD5: UART0_COL_b_PTD5: uart0_cts_b_ptd5 {
888		nxp,kinetis-port-pins = < 5 3 >;
889	};
890	FTM0_CH5_PTD5: ftm0_ch5_ptd5 {
891		nxp,kinetis-port-pins = < 5 4 >;
892	};
893	EWM_OUT_b_PTD5: ewm_out_b_ptd5 {
894		nxp,kinetis-port-pins = < 5 6 >;
895	};
896	SPI1_SCK_PTD5: spi1_sck_ptd5 {
897		nxp,kinetis-port-pins = < 5 7 >;
898	};
899	ADC0_SE7b_PTD6: adc0_se7b_ptd6 {
900		nxp,kinetis-port-pins = < 6 0 >;
901	};
902	PTD6: GPIOD_PTD6: LLWU_P15_PTD6: gpiod_ptd6 {
903		nxp,kinetis-port-pins = < 6 1 >;
904	};
905	SPI0_PCS3_PTD6: spi0_pcs3_ptd6 {
906		nxp,kinetis-port-pins = < 6 2 >;
907	};
908	UART0_RX_PTD6: uart0_rx_ptd6 {
909		nxp,kinetis-port-pins = < 6 3 >;
910	};
911	FTM0_CH6_PTD6: ftm0_ch6_ptd6 {
912		nxp,kinetis-port-pins = < 6 4 >;
913	};
914	FTM0_FLT0_PTD6: ftm0_flt0_ptd6 {
915		nxp,kinetis-port-pins = < 6 6 >;
916	};
917	SPI1_SOUT_PTD6: spi1_sout_ptd6 {
918		nxp,kinetis-port-pins = < 6 7 >;
919	};
920	PTD7: GPIOD_PTD7: gpiod_ptd7 {
921		nxp,kinetis-port-pins = < 7 1 >;
922	};
923	CMT_IRO_PTD7: cmt_iro_ptd7 {
924		nxp,kinetis-port-pins = < 7 2 >;
925	};
926	UART0_TX_PTD7: uart0_tx_ptd7 {
927		nxp,kinetis-port-pins = < 7 3 >;
928	};
929	FTM0_CH7_PTD7: ftm0_ch7_ptd7 {
930		nxp,kinetis-port-pins = < 7 4 >;
931	};
932	FTM0_FLT1_PTD7: ftm0_flt1_ptd7 {
933		nxp,kinetis-port-pins = < 7 6 >;
934	};
935	SPI1_SIN_PTD7: spi1_sin_ptd7 {
936		nxp,kinetis-port-pins = < 7 7 >;
937	};
938	PTD8: GPIOD_PTD8: gpiod_ptd8 {
939		nxp,kinetis-port-pins = < 8 1 >;
940	};
941	I2C0_SCL_PTD8: i2c0_scl_ptd8 {
942		nxp,kinetis-port-pins = < 8 2 >;
943	};
944	UART5_RX_PTD8: uart5_rx_ptd8 {
945		nxp,kinetis-port-pins = < 8 3 >;
946	};
947	PTD9: GPIOD_PTD9: gpiod_ptd9 {
948		nxp,kinetis-port-pins = < 9 1 >;
949	};
950	I2C0_SDA_PTD9: i2c0_sda_ptd9 {
951		nxp,kinetis-port-pins = < 9 2 >;
952	};
953	UART5_TX_PTD9: uart5_tx_ptd9 {
954		nxp,kinetis-port-pins = < 9 3 >;
955	};
956	PTD10: GPIOD_PTD10: gpiod_ptd10 {
957		nxp,kinetis-port-pins = < 10 1 >;
958	};
959	UART5_RTS_b_PTD10: uart5_rts_b_ptd10 {
960		nxp,kinetis-port-pins = < 10 3 >;
961	};
962	PTD11: GPIOD_PTD11: gpiod_ptd11 {
963		nxp,kinetis-port-pins = < 11 1 >;
964	};
965	SPI2_PCS0_PTD11: spi2_pcs0_ptd11 {
966		nxp,kinetis-port-pins = < 11 2 >;
967	};
968	UART5_CTS_b_PTD11: uart5_cts_b_ptd11 {
969		nxp,kinetis-port-pins = < 11 3 >;
970	};
971	SDHC0_CLKIN_PTD11: sdhc0_clkin_ptd11 {
972		nxp,kinetis-port-pins = < 11 4 >;
973	};
974	PTD12: GPIOD_PTD12: gpiod_ptd12 {
975		nxp,kinetis-port-pins = < 12 1 >;
976	};
977	SPI2_SCK_PTD12: spi2_sck_ptd12 {
978		nxp,kinetis-port-pins = < 12 2 >;
979	};
980	FTM3_FLT0_PTD12: ftm3_flt0_ptd12 {
981		nxp,kinetis-port-pins = < 12 3 >;
982	};
983	SDHC0_D4_PTD12: sdhc0_d4_ptd12 {
984		nxp,kinetis-port-pins = < 12 4 >;
985	};
986	PTD13: GPIOD_PTD13: gpiod_ptd13 {
987		nxp,kinetis-port-pins = < 13 1 >;
988	};
989	SPI2_SOUT_PTD13: spi2_sout_ptd13 {
990		nxp,kinetis-port-pins = < 13 2 >;
991	};
992	SDHC0_D5_PTD13: sdhc0_d5_ptd13 {
993		nxp,kinetis-port-pins = < 13 4 >;
994	};
995	PTD14: GPIOD_PTD14: gpiod_ptd14 {
996		nxp,kinetis-port-pins = < 14 1 >;
997	};
998	SPI2_SIN_PTD14: spi2_sin_ptd14 {
999		nxp,kinetis-port-pins = < 14 2 >;
1000	};
1001	SDHC0_D6_PTD14: sdhc0_d6_ptd14 {
1002		nxp,kinetis-port-pins = < 14 4 >;
1003	};
1004	PTD15: GPIOD_PTD15: gpiod_ptd15 {
1005		nxp,kinetis-port-pins = < 15 1 >;
1006	};
1007	SPI2_PCS1_PTD15: spi2_pcs1_ptd15 {
1008		nxp,kinetis-port-pins = < 15 2 >;
1009	};
1010	SDHC0_D7_PTD15: sdhc0_d7_ptd15 {
1011		nxp,kinetis-port-pins = < 15 4 >;
1012	};
1013};
1014
1015&porte {
1016	ADC1_SE4a_PTE0: adc1_se4a_pte0 {
1017		nxp,kinetis-port-pins = < 0 0 >;
1018	};
1019	PTE0: GPIOE_PTE0: gpioe_pte0 {
1020		nxp,kinetis-port-pins = < 0 1 >;
1021	};
1022	SPI1_PCS1_PTE0: spi1_pcs1_pte0 {
1023		nxp,kinetis-port-pins = < 0 2 >;
1024	};
1025	UART1_TX_PTE0: uart1_tx_pte0 {
1026		nxp,kinetis-port-pins = < 0 3 >;
1027	};
1028	SDHC0_D1_PTE0: sdhc0_d1_pte0 {
1029		nxp,kinetis-port-pins = < 0 4 >;
1030	};
1031	TRACE_CLKOUT_PTE0: trace_clkout_pte0 {
1032		nxp,kinetis-port-pins = < 0 5 >;
1033	};
1034	I2C1_SDA_PTE0: i2c1_sda_pte0 {
1035		nxp,kinetis-port-pins = < 0 6 >;
1036	};
1037	RTC_CLKOUT_PTE0: rtc_clkout_pte0 {
1038		nxp,kinetis-port-pins = < 0 7 >;
1039	};
1040	ADC1_SE5a_PTE1: adc1_se5a_pte1 {
1041		nxp,kinetis-port-pins = < 1 0 >;
1042	};
1043	PTE1: GPIOE_PTE1: LLWU_P0_PTE1: gpioe_pte1 {
1044		nxp,kinetis-port-pins = < 1 1 >;
1045	};
1046	SPI1_SOUT_PTE1: spi1_sout_pte1 {
1047		nxp,kinetis-port-pins = < 1 2 >;
1048	};
1049	UART1_RX_PTE1: uart1_rx_pte1 {
1050		nxp,kinetis-port-pins = < 1 3 >;
1051	};
1052	SDHC0_D0_PTE1: sdhc0_d0_pte1 {
1053		nxp,kinetis-port-pins = < 1 4 >;
1054	};
1055	TRACE_D3_PTE1: trace_d3_pte1 {
1056		nxp,kinetis-port-pins = < 1 5 >;
1057	};
1058	I2C1_SCL_PTE1: i2c1_scl_pte1 {
1059		nxp,kinetis-port-pins = < 1 6 >;
1060	};
1061	SPI1_SIN_PTE1: spi1_sin_pte1 {
1062		nxp,kinetis-port-pins = < 1 7 >;
1063	};
1064	ADC0_DP2_PTE2: ADC1_SE6a_PTE2: adc0_dp2_pte2 {
1065		nxp,kinetis-port-pins = < 2 0 >;
1066	};
1067	PTE2: GPIOE_PTE2: LLWU_P1_PTE2: gpioe_pte2 {
1068		nxp,kinetis-port-pins = < 2 1 >;
1069	};
1070	SPI1_SCK_PTE2: spi1_sck_pte2 {
1071		nxp,kinetis-port-pins = < 2 2 >;
1072	};
1073	UART1_CTS_b_PTE2: uart1_cts_b_pte2 {
1074		nxp,kinetis-port-pins = < 2 3 >;
1075	};
1076	SDHC0_DCLK_PTE2: sdhc0_dclk_pte2 {
1077		nxp,kinetis-port-pins = < 2 4 >;
1078	};
1079	TRACE_D2_PTE2: trace_d2_pte2 {
1080		nxp,kinetis-port-pins = < 2 5 >;
1081	};
1082	ADC0_DM2_PTE3: ADC1_SE7a_PTE3: adc0_dm2_pte3 {
1083		nxp,kinetis-port-pins = < 3 0 >;
1084	};
1085	PTE3: GPIOE_PTE3: gpioe_pte3 {
1086		nxp,kinetis-port-pins = < 3 1 >;
1087	};
1088	SPI1_SIN_PTE3: spi1_sin_pte3 {
1089		nxp,kinetis-port-pins = < 3 2 >;
1090	};
1091	UART1_RTS_b_PTE3: uart1_rts_b_pte3 {
1092		nxp,kinetis-port-pins = < 3 3 >;
1093	};
1094	SDHC0_CMD_PTE3: sdhc0_cmd_pte3 {
1095		nxp,kinetis-port-pins = < 3 4 >;
1096	};
1097	TRACE_D1_PTE3: trace_d1_pte3 {
1098		nxp,kinetis-port-pins = < 3 5 >;
1099	};
1100	SPI1_SOUT_PTE3: spi1_sout_pte3 {
1101		nxp,kinetis-port-pins = < 3 7 >;
1102	};
1103	PTE4: GPIOE_PTE4: LLWU_P2_PTE4: gpioe_pte4 {
1104		nxp,kinetis-port-pins = < 4 1 >;
1105	};
1106	SPI1_PCS0_PTE4: spi1_pcs0_pte4 {
1107		nxp,kinetis-port-pins = < 4 2 >;
1108	};
1109	UART3_TX_PTE4: uart3_tx_pte4 {
1110		nxp,kinetis-port-pins = < 4 3 >;
1111	};
1112	SDHC0_D3_PTE4: sdhc0_d3_pte4 {
1113		nxp,kinetis-port-pins = < 4 4 >;
1114	};
1115	TRACE_D0_PTE4: trace_d0_pte4 {
1116		nxp,kinetis-port-pins = < 4 5 >;
1117	};
1118	PTE5: GPIOE_PTE5: gpioe_pte5 {
1119		nxp,kinetis-port-pins = < 5 1 >;
1120	};
1121	SPI1_PCS2_PTE5: spi1_pcs2_pte5 {
1122		nxp,kinetis-port-pins = < 5 2 >;
1123	};
1124	UART3_RX_PTE5: uart3_rx_pte5 {
1125		nxp,kinetis-port-pins = < 5 3 >;
1126	};
1127	SDHC0_D2_PTE5: sdhc0_d2_pte5 {
1128		nxp,kinetis-port-pins = < 5 4 >;
1129	};
1130	FTM3_CH0_PTE5: ftm3_ch0_pte5 {
1131		nxp,kinetis-port-pins = < 5 6 >;
1132	};
1133	PTE6: GPIOE_PTE6: gpioe_pte6 {
1134		nxp,kinetis-port-pins = < 6 1 >;
1135	};
1136	SPI1_PCS3_PTE6: spi1_pcs3_pte6 {
1137		nxp,kinetis-port-pins = < 6 2 >;
1138	};
1139	UART3_CTS_b_PTE6: uart3_cts_b_pte6 {
1140		nxp,kinetis-port-pins = < 6 3 >;
1141	};
1142	I2S0_MCLK_PTE6: i2s0_mclk_pte6 {
1143		nxp,kinetis-port-pins = < 6 4 >;
1144	};
1145	FTM3_CH1_PTE6: ftm3_ch1_pte6 {
1146		nxp,kinetis-port-pins = < 6 6 >;
1147	};
1148	USB_SOF_OUT_PTE6: usb_sof_out_pte6 {
1149		nxp,kinetis-port-pins = < 6 7 >;
1150	};
1151	ADC0_SE17_PTE24: adc0_se17_pte24 {
1152		nxp,kinetis-port-pins = < 24 0 >;
1153	};
1154	PTE24: GPIOE_PTE24: gpioe_pte24 {
1155		nxp,kinetis-port-pins = < 24 1 >;
1156	};
1157	UART4_TX_PTE24: uart4_tx_pte24 {
1158		nxp,kinetis-port-pins = < 24 3 >;
1159	};
1160	I2C0_SCL_PTE24: i2c0_scl_pte24 {
1161		nxp,kinetis-port-pins = < 24 5 >;
1162	};
1163	EWM_OUT_b_PTE24: ewm_out_b_pte24 {
1164		nxp,kinetis-port-pins = < 24 6 >;
1165	};
1166	ADC0_SE18_PTE25: adc0_se18_pte25 {
1167		nxp,kinetis-port-pins = < 25 0 >;
1168	};
1169	PTE25: GPIOE_PTE25: gpioe_pte25 {
1170		nxp,kinetis-port-pins = < 25 1 >;
1171	};
1172	UART4_RX_PTE25: uart4_rx_pte25 {
1173		nxp,kinetis-port-pins = < 25 3 >;
1174	};
1175	I2C0_SDA_PTE25: i2c0_sda_pte25 {
1176		nxp,kinetis-port-pins = < 25 5 >;
1177	};
1178	EWM_IN_PTE25: ewm_in_pte25 {
1179		nxp,kinetis-port-pins = < 25 6 >;
1180	};
1181	PTE26: GPIOE_PTE26: gpioe_pte26 {
1182		nxp,kinetis-port-pins = < 26 1 >;
1183	};
1184	ENET_1588_CLKIN_PTE26: enet_1588_clkin_pte26 {
1185		nxp,kinetis-port-pins = < 26 2 >;
1186	};
1187	UART4_CTS_b_PTE26: uart4_cts_b_pte26 {
1188		nxp,kinetis-port-pins = < 26 3 >;
1189	};
1190	RTC_CLKOUT_PTE26: rtc_clkout_pte26 {
1191		nxp,kinetis-port-pins = < 26 6 >;
1192	};
1193	USB_CLKIN_PTE26: usb_clkin_pte26 {
1194		nxp,kinetis-port-pins = < 26 7 >;
1195	};
1196};
1197
1198