1/*
2 * NOTE: Autogenerated file by kinetis_signal2dts.py
3 *       for MK22FN512VLH12/signal_configuration.xml
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8/*
9 * Pin nodes are of the form:
10 *
11 *	<SIGNAL[0..n]>: <signal[0]> {
12 *		nxp,kinetis-port-pins = < PIN PCR[MUX] >;
13 *	};
14 */
15
16&porta {
17	PTA0: GPIOA_PTA0: gpioa_pta0 {
18		nxp,kinetis-port-pins = < 0 1 >;
19	};
20	UART0_CTS_b_PTA0: uart0_cts_b_pta0 {
21		nxp,kinetis-port-pins = < 0 2 >;
22	};
23	FTM0_CH5_PTA0: ftm0_ch5_pta0 {
24		nxp,kinetis-port-pins = < 0 3 >;
25	};
26	JTAG_TCLK_PTA0: jtag_tclk_pta0 {
27		nxp,kinetis-port-pins = < 0 7 >;
28	};
29	PTA1: GPIOA_PTA1: gpioa_pta1 {
30		nxp,kinetis-port-pins = < 1 1 >;
31	};
32	UART0_RX_PTA1: uart0_rx_pta1 {
33		nxp,kinetis-port-pins = < 1 2 >;
34	};
35	FTM0_CH6_PTA1: ftm0_ch6_pta1 {
36		nxp,kinetis-port-pins = < 1 3 >;
37	};
38	JTAG_TDI_PTA1: jtag_tdi_pta1 {
39		nxp,kinetis-port-pins = < 1 7 >;
40	};
41	PTA2: GPIOA_PTA2: gpioa_pta2 {
42		nxp,kinetis-port-pins = < 2 1 >;
43	};
44	UART0_TX_PTA2: uart0_tx_pta2 {
45		nxp,kinetis-port-pins = < 2 2 >;
46	};
47	FTM0_CH7_PTA2: ftm0_ch7_pta2 {
48		nxp,kinetis-port-pins = < 2 3 >;
49	};
50	JTAG_TDO_PTA2: TRACE_SWO_PTA2: jtag_tdo_pta2 {
51		nxp,kinetis-port-pins = < 2 7 >;
52	};
53	PTA3: GPIOA_PTA3: gpioa_pta3 {
54		nxp,kinetis-port-pins = < 3 1 >;
55	};
56	UART0_RTS_b_PTA3: uart0_rts_b_pta3 {
57		nxp,kinetis-port-pins = < 3 2 >;
58	};
59	FTM0_CH0_PTA3: ftm0_ch0_pta3 {
60		nxp,kinetis-port-pins = < 3 3 >;
61	};
62	JTAG_TMS_PTA3: jtag_tms_pta3 {
63		nxp,kinetis-port-pins = < 3 7 >;
64	};
65	PTA4: GPIOA_PTA4: LLWU_P3_PTA4: gpioa_pta4 {
66		nxp,kinetis-port-pins = < 4 1 >;
67	};
68	FTM0_CH1_PTA4: ftm0_ch1_pta4 {
69		nxp,kinetis-port-pins = < 4 3 >;
70	};
71	NMI_b_PTA4: nmi_b_pta4 {
72		nxp,kinetis-port-pins = < 4 7 >;
73	};
74	PTA5: GPIOA_PTA5: gpioa_pta5 {
75		nxp,kinetis-port-pins = < 5 1 >;
76	};
77	USB_CLKIN_PTA5: usb_clkin_pta5 {
78		nxp,kinetis-port-pins = < 5 2 >;
79	};
80	FTM0_CH2_PTA5: ftm0_ch2_pta5 {
81		nxp,kinetis-port-pins = < 5 3 >;
82	};
83	I2S0_TX_BCLK_PTA5: i2s0_tx_bclk_pta5 {
84		nxp,kinetis-port-pins = < 5 6 >;
85	};
86	JTAG_TRST_b_PTA5: jtag_trst_b_pta5 {
87		nxp,kinetis-port-pins = < 5 7 >;
88	};
89	PTA12: GPIOA_PTA12: gpioa_pta12 {
90		nxp,kinetis-port-pins = < 12 1 >;
91	};
92	FTM1_CH0_PTA12: ftm1_ch0_pta12 {
93		nxp,kinetis-port-pins = < 12 3 >;
94	};
95	I2S0_TXD0_PTA12: i2s0_txd0_pta12 {
96		nxp,kinetis-port-pins = < 12 6 >;
97	};
98	FTM1_QD_PHA_PTA12: ftm1_qd_pha_pta12 {
99		nxp,kinetis-port-pins = < 12 7 >;
100	};
101	PTA13: GPIOA_PTA13: LLWU_P4_PTA13: gpioa_pta13 {
102		nxp,kinetis-port-pins = < 13 1 >;
103	};
104	FTM1_CH1_PTA13: ftm1_ch1_pta13 {
105		nxp,kinetis-port-pins = < 13 3 >;
106	};
107	I2S0_TX_FS_PTA13: i2s0_tx_fs_pta13 {
108		nxp,kinetis-port-pins = < 13 6 >;
109	};
110	FTM1_QD_PHB_PTA13: ftm1_qd_phb_pta13 {
111		nxp,kinetis-port-pins = < 13 7 >;
112	};
113	EXTAL0_PTA18: extal0_pta18 {
114		nxp,kinetis-port-pins = < 18 0 >;
115	};
116	PTA18: GPIOA_PTA18: gpioa_pta18 {
117		nxp,kinetis-port-pins = < 18 1 >;
118	};
119	FTM0_FLT2_PTA18: ftm0_flt2_pta18 {
120		nxp,kinetis-port-pins = < 18 3 >;
121	};
122	FTM_CLKIN0_PTA18: ftm_clkin0_pta18 {
123		nxp,kinetis-port-pins = < 18 4 >;
124	};
125	XTAL0_PTA19: xtal0_pta19 {
126		nxp,kinetis-port-pins = < 19 0 >;
127	};
128	PTA19: GPIOA_PTA19: gpioa_pta19 {
129		nxp,kinetis-port-pins = < 19 1 >;
130	};
131	FTM1_FLT0_PTA19: ftm1_flt0_pta19 {
132		nxp,kinetis-port-pins = < 19 3 >;
133	};
134	FTM_CLKIN1_PTA19: ftm_clkin1_pta19 {
135		nxp,kinetis-port-pins = < 19 4 >;
136	};
137	LPTMR0_ALT1_PTA19: lptmr0_alt1_pta19 {
138		nxp,kinetis-port-pins = < 19 6 >;
139	};
140};
141
142&portb {
143	ADC0_SE8_PTB0: ADC1_SE8_PTB0: adc0_se8_ptb0 {
144		nxp,kinetis-port-pins = < 0 0 >;
145	};
146	PTB0: GPIOB_PTB0: LLWU_P5_PTB0: gpiob_ptb0 {
147		nxp,kinetis-port-pins = < 0 1 >;
148	};
149	I2C0_SCL_PTB0: i2c0_scl_ptb0 {
150		nxp,kinetis-port-pins = < 0 2 >;
151	};
152	FTM1_CH0_PTB0: ftm1_ch0_ptb0 {
153		nxp,kinetis-port-pins = < 0 3 >;
154	};
155	FTM1_QD_PHA_PTB0: ftm1_qd_pha_ptb0 {
156		nxp,kinetis-port-pins = < 0 6 >;
157	};
158	ADC0_SE9_PTB1: ADC1_SE9_PTB1: adc0_se9_ptb1 {
159		nxp,kinetis-port-pins = < 1 0 >;
160	};
161	PTB1: GPIOB_PTB1: gpiob_ptb1 {
162		nxp,kinetis-port-pins = < 1 1 >;
163	};
164	I2C0_SDA_PTB1: i2c0_sda_ptb1 {
165		nxp,kinetis-port-pins = < 1 2 >;
166	};
167	FTM1_CH1_PTB1: ftm1_ch1_ptb1 {
168		nxp,kinetis-port-pins = < 1 3 >;
169	};
170	FTM1_QD_PHB_PTB1: ftm1_qd_phb_ptb1 {
171		nxp,kinetis-port-pins = < 1 6 >;
172	};
173	ADC0_SE12_PTB2: adc0_se12_ptb2 {
174		nxp,kinetis-port-pins = < 2 0 >;
175	};
176	PTB2: GPIOB_PTB2: gpiob_ptb2 {
177		nxp,kinetis-port-pins = < 2 1 >;
178	};
179	I2C0_SCL_PTB2: i2c0_scl_ptb2 {
180		nxp,kinetis-port-pins = < 2 2 >;
181	};
182	UART0_RTS_b_PTB2: uart0_rts_b_ptb2 {
183		nxp,kinetis-port-pins = < 2 3 >;
184	};
185	FTM0_FLT3_PTB2: ftm0_flt3_ptb2 {
186		nxp,kinetis-port-pins = < 2 6 >;
187	};
188	ADC0_SE13_PTB3: adc0_se13_ptb3 {
189		nxp,kinetis-port-pins = < 3 0 >;
190	};
191	PTB3: GPIOB_PTB3: gpiob_ptb3 {
192		nxp,kinetis-port-pins = < 3 1 >;
193	};
194	I2C0_SDA_PTB3: i2c0_sda_ptb3 {
195		nxp,kinetis-port-pins = < 3 2 >;
196	};
197	UART0_CTS_b_PTB3: uart0_cts_b_ptb3 {
198		nxp,kinetis-port-pins = < 3 3 >;
199	};
200	FTM0_FLT0_PTB3: ftm0_flt0_ptb3 {
201		nxp,kinetis-port-pins = < 3 6 >;
202	};
203	PTB16: GPIOB_PTB16: gpiob_ptb16 {
204		nxp,kinetis-port-pins = < 16 1 >;
205	};
206	SPI1_SOUT_PTB16: spi1_sout_ptb16 {
207		nxp,kinetis-port-pins = < 16 2 >;
208	};
209	UART0_RX_PTB16: uart0_rx_ptb16 {
210		nxp,kinetis-port-pins = < 16 3 >;
211	};
212	FTM_CLKIN0_PTB16: ftm_clkin0_ptb16 {
213		nxp,kinetis-port-pins = < 16 4 >;
214	};
215	EWM_IN_PTB16: ewm_in_ptb16 {
216		nxp,kinetis-port-pins = < 16 6 >;
217	};
218	PTB17: GPIOB_PTB17: gpiob_ptb17 {
219		nxp,kinetis-port-pins = < 17 1 >;
220	};
221	SPI1_SIN_PTB17: spi1_sin_ptb17 {
222		nxp,kinetis-port-pins = < 17 2 >;
223	};
224	UART0_TX_PTB17: uart0_tx_ptb17 {
225		nxp,kinetis-port-pins = < 17 3 >;
226	};
227	FTM_CLKIN1_PTB17: ftm_clkin1_ptb17 {
228		nxp,kinetis-port-pins = < 17 4 >;
229	};
230	EWM_OUT_b_PTB17: ewm_out_b_ptb17 {
231		nxp,kinetis-port-pins = < 17 6 >;
232	};
233	PTB18: GPIOB_PTB18: gpiob_ptb18 {
234		nxp,kinetis-port-pins = < 18 1 >;
235	};
236	FTM2_CH0_PTB18: ftm2_ch0_ptb18 {
237		nxp,kinetis-port-pins = < 18 3 >;
238	};
239	I2S0_TX_BCLK_PTB18: i2s0_tx_bclk_ptb18 {
240		nxp,kinetis-port-pins = < 18 4 >;
241	};
242	FTM2_QD_PHA_PTB18: ftm2_qd_pha_ptb18 {
243		nxp,kinetis-port-pins = < 18 6 >;
244	};
245	PTB19: GPIOB_PTB19: gpiob_ptb19 {
246		nxp,kinetis-port-pins = < 19 1 >;
247	};
248	FTM2_CH1_PTB19: ftm2_ch1_ptb19 {
249		nxp,kinetis-port-pins = < 19 3 >;
250	};
251	I2S0_TX_FS_PTB19: i2s0_tx_fs_ptb19 {
252		nxp,kinetis-port-pins = < 19 4 >;
253	};
254	FTM2_QD_PHB_PTB19: ftm2_qd_phb_ptb19 {
255		nxp,kinetis-port-pins = < 19 6 >;
256	};
257};
258
259&portc {
260	ADC0_SE14_PTC0: adc0_se14_ptc0 {
261		nxp,kinetis-port-pins = < 0 0 >;
262	};
263	PTC0: GPIOC_PTC0: gpioc_ptc0 {
264		nxp,kinetis-port-pins = < 0 1 >;
265	};
266	SPI0_PCS4_PTC0: spi0_pcs4_ptc0 {
267		nxp,kinetis-port-pins = < 0 2 >;
268	};
269	PDB0_EXTRG_PTC0: pdb0_extrg_ptc0 {
270		nxp,kinetis-port-pins = < 0 3 >;
271	};
272	USB_SOF_OUT_PTC0: usb_sof_out_ptc0 {
273		nxp,kinetis-port-pins = < 0 4 >;
274	};
275	ADC0_SE15_PTC1: adc0_se15_ptc1 {
276		nxp,kinetis-port-pins = < 1 0 >;
277	};
278	PTC1: GPIOC_PTC1: LLWU_P6_PTC1: gpioc_ptc1 {
279		nxp,kinetis-port-pins = < 1 1 >;
280	};
281	SPI0_PCS3_PTC1: spi0_pcs3_ptc1 {
282		nxp,kinetis-port-pins = < 1 2 >;
283	};
284	UART1_RTS_b_PTC1: uart1_rts_b_ptc1 {
285		nxp,kinetis-port-pins = < 1 3 >;
286	};
287	FTM0_CH0_PTC1: ftm0_ch0_ptc1 {
288		nxp,kinetis-port-pins = < 1 4 >;
289	};
290	I2S0_TXD0_PTC1: i2s0_txd0_ptc1 {
291		nxp,kinetis-port-pins = < 1 6 >;
292	};
293	LPUART0_RTS_b_PTC1: lpuart0_rts_b_ptc1 {
294		nxp,kinetis-port-pins = < 1 7 >;
295	};
296	ADC0_SE4b_PTC2: CMP1_IN0_PTC2: adc0_se4b_ptc2 {
297		nxp,kinetis-port-pins = < 2 0 >;
298	};
299	PTC2: GPIOC_PTC2: gpioc_ptc2 {
300		nxp,kinetis-port-pins = < 2 1 >;
301	};
302	SPI0_PCS2_PTC2: spi0_pcs2_ptc2 {
303		nxp,kinetis-port-pins = < 2 2 >;
304	};
305	UART1_CTS_b_PTC2: uart1_cts_b_ptc2 {
306		nxp,kinetis-port-pins = < 2 3 >;
307	};
308	FTM0_CH1_PTC2: ftm0_ch1_ptc2 {
309		nxp,kinetis-port-pins = < 2 4 >;
310	};
311	I2S0_TX_FS_PTC2: i2s0_tx_fs_ptc2 {
312		nxp,kinetis-port-pins = < 2 6 >;
313	};
314	LPUART0_CTS_b_PTC2: lpuart0_cts_b_ptc2 {
315		nxp,kinetis-port-pins = < 2 7 >;
316	};
317	CMP1_IN1_PTC3: cmp1_in1_ptc3 {
318		nxp,kinetis-port-pins = < 3 0 >;
319	};
320	PTC3: GPIOC_PTC3: LLWU_P7_PTC3: gpioc_ptc3 {
321		nxp,kinetis-port-pins = < 3 1 >;
322	};
323	SPI0_PCS1_PTC3: spi0_pcs1_ptc3 {
324		nxp,kinetis-port-pins = < 3 2 >;
325	};
326	UART1_RX_PTC3: uart1_rx_ptc3 {
327		nxp,kinetis-port-pins = < 3 3 >;
328	};
329	FTM0_CH2_PTC3: ftm0_ch2_ptc3 {
330		nxp,kinetis-port-pins = < 3 4 >;
331	};
332	CLKOUT_PTC3: clkout_ptc3 {
333		nxp,kinetis-port-pins = < 3 5 >;
334	};
335	I2S0_TX_BCLK_PTC3: i2s0_tx_bclk_ptc3 {
336		nxp,kinetis-port-pins = < 3 6 >;
337	};
338	LPUART0_RX_PTC3: lpuart0_rx_ptc3 {
339		nxp,kinetis-port-pins = < 3 7 >;
340	};
341	PTC4: GPIOC_PTC4: LLWU_P8_PTC4: gpioc_ptc4 {
342		nxp,kinetis-port-pins = < 4 1 >;
343	};
344	SPI0_PCS0_PTC4: spi0_pcs0_ptc4 {
345		nxp,kinetis-port-pins = < 4 2 >;
346	};
347	UART1_TX_PTC4: uart1_tx_ptc4 {
348		nxp,kinetis-port-pins = < 4 3 >;
349	};
350	FTM0_CH3_PTC4: ftm0_ch3_ptc4 {
351		nxp,kinetis-port-pins = < 4 4 >;
352	};
353	CMP1_OUT_PTC4: cmp1_out_ptc4 {
354		nxp,kinetis-port-pins = < 4 6 >;
355	};
356	LPUART0_TX_PTC4: lpuart0_tx_ptc4 {
357		nxp,kinetis-port-pins = < 4 7 >;
358	};
359	PTC5: GPIOC_PTC5: LLWU_P9_PTC5: gpioc_ptc5 {
360		nxp,kinetis-port-pins = < 5 1 >;
361	};
362	SPI0_SCK_PTC5: spi0_sck_ptc5 {
363		nxp,kinetis-port-pins = < 5 2 >;
364	};
365	LPTMR0_ALT2_PTC5: lptmr0_alt2_ptc5 {
366		nxp,kinetis-port-pins = < 5 3 >;
367	};
368	I2S0_RXD0_PTC5: i2s0_rxd0_ptc5 {
369		nxp,kinetis-port-pins = < 5 4 >;
370	};
371	CMP0_OUT_PTC5: cmp0_out_ptc5 {
372		nxp,kinetis-port-pins = < 5 6 >;
373	};
374	FTM0_CH2_PTC5: ftm0_ch2_ptc5 {
375		nxp,kinetis-port-pins = < 5 7 >;
376	};
377	CMP0_IN0_PTC6: cmp0_in0_ptc6 {
378		nxp,kinetis-port-pins = < 6 0 >;
379	};
380	PTC6: GPIOC_PTC6: LLWU_P10_PTC6: gpioc_ptc6 {
381		nxp,kinetis-port-pins = < 6 1 >;
382	};
383	SPI0_SOUT_PTC6: spi0_sout_ptc6 {
384		nxp,kinetis-port-pins = < 6 2 >;
385	};
386	PDB0_EXTRG_PTC6: pdb0_extrg_ptc6 {
387		nxp,kinetis-port-pins = < 6 3 >;
388	};
389	I2S0_RX_BCLK_PTC6: i2s0_rx_bclk_ptc6 {
390		nxp,kinetis-port-pins = < 6 4 >;
391	};
392	I2S0_MCLK_PTC6: i2s0_mclk_ptc6 {
393		nxp,kinetis-port-pins = < 6 6 >;
394	};
395	CMP0_IN1_PTC7: cmp0_in1_ptc7 {
396		nxp,kinetis-port-pins = < 7 0 >;
397	};
398	PTC7: GPIOC_PTC7: gpioc_ptc7 {
399		nxp,kinetis-port-pins = < 7 1 >;
400	};
401	SPI0_SIN_PTC7: spi0_sin_ptc7 {
402		nxp,kinetis-port-pins = < 7 2 >;
403	};
404	USB_SOF_OUT_PTC7: usb_sof_out_ptc7 {
405		nxp,kinetis-port-pins = < 7 3 >;
406	};
407	I2S0_RX_FS_PTC7: i2s0_rx_fs_ptc7 {
408		nxp,kinetis-port-pins = < 7 4 >;
409	};
410	ADC1_SE4b_PTC8: CMP0_IN2_PTC8: adc1_se4b_ptc8 {
411		nxp,kinetis-port-pins = < 8 0 >;
412	};
413	PTC8: GPIOC_PTC8: gpioc_ptc8 {
414		nxp,kinetis-port-pins = < 8 1 >;
415	};
416	FTM3_CH4_PTC8: ftm3_ch4_ptc8 {
417		nxp,kinetis-port-pins = < 8 3 >;
418	};
419	I2S0_MCLK_PTC8: i2s0_mclk_ptc8 {
420		nxp,kinetis-port-pins = < 8 4 >;
421	};
422	ADC1_SE5b_PTC9: CMP0_IN3_PTC9: adc1_se5b_ptc9 {
423		nxp,kinetis-port-pins = < 9 0 >;
424	};
425	PTC9: GPIOC_PTC9: gpioc_ptc9 {
426		nxp,kinetis-port-pins = < 9 1 >;
427	};
428	FTM3_CH5_PTC9: ftm3_ch5_ptc9 {
429		nxp,kinetis-port-pins = < 9 3 >;
430	};
431	I2S0_RX_BCLK_PTC9: i2s0_rx_bclk_ptc9 {
432		nxp,kinetis-port-pins = < 9 4 >;
433	};
434	FTM2_FLT0_PTC9: ftm2_flt0_ptc9 {
435		nxp,kinetis-port-pins = < 9 6 >;
436	};
437	ADC1_SE6b_PTC10: adc1_se6b_ptc10 {
438		nxp,kinetis-port-pins = < 10 0 >;
439	};
440	PTC10: GPIOC_PTC10: gpioc_ptc10 {
441		nxp,kinetis-port-pins = < 10 1 >;
442	};
443	I2C1_SCL_PTC10: i2c1_scl_ptc10 {
444		nxp,kinetis-port-pins = < 10 2 >;
445	};
446	FTM3_CH6_PTC10: ftm3_ch6_ptc10 {
447		nxp,kinetis-port-pins = < 10 3 >;
448	};
449	I2S0_RX_FS_PTC10: i2s0_rx_fs_ptc10 {
450		nxp,kinetis-port-pins = < 10 4 >;
451	};
452	ADC1_SE7b_PTC11: adc1_se7b_ptc11 {
453		nxp,kinetis-port-pins = < 11 0 >;
454	};
455	PTC11: GPIOC_PTC11: LLWU_P11_PTC11: gpioc_ptc11 {
456		nxp,kinetis-port-pins = < 11 1 >;
457	};
458	I2C1_SDA_PTC11: i2c1_sda_ptc11 {
459		nxp,kinetis-port-pins = < 11 2 >;
460	};
461	FTM3_CH7_PTC11: ftm3_ch7_ptc11 {
462		nxp,kinetis-port-pins = < 11 3 >;
463	};
464};
465
466&portd {
467	PTD0: GPIOD_PTD0: LLWU_P12_PTD0: gpiod_ptd0 {
468		nxp,kinetis-port-pins = < 0 1 >;
469	};
470	SPI0_PCS0_PTD0: spi0_pcs0_ptd0 {
471		nxp,kinetis-port-pins = < 0 2 >;
472	};
473	UART2_RTS_b_PTD0: uart2_rts_b_ptd0 {
474		nxp,kinetis-port-pins = < 0 3 >;
475	};
476	FTM3_CH0_PTD0: ftm3_ch0_ptd0 {
477		nxp,kinetis-port-pins = < 0 4 >;
478	};
479	LPUART0_RTS_b_PTD0: lpuart0_rts_b_ptd0 {
480		nxp,kinetis-port-pins = < 0 6 >;
481	};
482	ADC0_SE5b_PTD1: adc0_se5b_ptd1 {
483		nxp,kinetis-port-pins = < 1 0 >;
484	};
485	PTD1: GPIOD_PTD1: gpiod_ptd1 {
486		nxp,kinetis-port-pins = < 1 1 >;
487	};
488	SPI0_SCK_PTD1: spi0_sck_ptd1 {
489		nxp,kinetis-port-pins = < 1 2 >;
490	};
491	UART2_CTS_b_PTD1: uart2_cts_b_ptd1 {
492		nxp,kinetis-port-pins = < 1 3 >;
493	};
494	FTM3_CH1_PTD1: ftm3_ch1_ptd1 {
495		nxp,kinetis-port-pins = < 1 4 >;
496	};
497	LPUART0_CTS_b_PTD1: lpuart0_cts_b_ptd1 {
498		nxp,kinetis-port-pins = < 1 6 >;
499	};
500	PTD2: GPIOD_PTD2: LLWU_P13_PTD2: gpiod_ptd2 {
501		nxp,kinetis-port-pins = < 2 1 >;
502	};
503	SPI0_SOUT_PTD2: spi0_sout_ptd2 {
504		nxp,kinetis-port-pins = < 2 2 >;
505	};
506	UART2_RX_PTD2: uart2_rx_ptd2 {
507		nxp,kinetis-port-pins = < 2 3 >;
508	};
509	FTM3_CH2_PTD2: ftm3_ch2_ptd2 {
510		nxp,kinetis-port-pins = < 2 4 >;
511	};
512	LPUART0_RX_PTD2: lpuart0_rx_ptd2 {
513		nxp,kinetis-port-pins = < 2 6 >;
514	};
515	I2C0_SCL_PTD2: i2c0_scl_ptd2 {
516		nxp,kinetis-port-pins = < 2 7 >;
517	};
518	PTD3: GPIOD_PTD3: gpiod_ptd3 {
519		nxp,kinetis-port-pins = < 3 1 >;
520	};
521	SPI0_SIN_PTD3: spi0_sin_ptd3 {
522		nxp,kinetis-port-pins = < 3 2 >;
523	};
524	UART2_TX_PTD3: uart2_tx_ptd3 {
525		nxp,kinetis-port-pins = < 3 3 >;
526	};
527	FTM3_CH3_PTD3: ftm3_ch3_ptd3 {
528		nxp,kinetis-port-pins = < 3 4 >;
529	};
530	LPUART0_TX_PTD3: lpuart0_tx_ptd3 {
531		nxp,kinetis-port-pins = < 3 6 >;
532	};
533	I2C0_SDA_PTD3: i2c0_sda_ptd3 {
534		nxp,kinetis-port-pins = < 3 7 >;
535	};
536	PTD4: GPIOD_PTD4: LLWU_P14_PTD4: gpiod_ptd4 {
537		nxp,kinetis-port-pins = < 4 1 >;
538	};
539	SPI0_PCS1_PTD4: spi0_pcs1_ptd4 {
540		nxp,kinetis-port-pins = < 4 2 >;
541	};
542	UART0_RTS_b_PTD4: uart0_rts_b_ptd4 {
543		nxp,kinetis-port-pins = < 4 3 >;
544	};
545	FTM0_CH4_PTD4: ftm0_ch4_ptd4 {
546		nxp,kinetis-port-pins = < 4 4 >;
547	};
548	EWM_IN_PTD4: ewm_in_ptd4 {
549		nxp,kinetis-port-pins = < 4 6 >;
550	};
551	SPI1_PCS0_PTD4: spi1_pcs0_ptd4 {
552		nxp,kinetis-port-pins = < 4 7 >;
553	};
554	ADC0_SE6b_PTD5: adc0_se6b_ptd5 {
555		nxp,kinetis-port-pins = < 5 0 >;
556	};
557	PTD5: GPIOD_PTD5: gpiod_ptd5 {
558		nxp,kinetis-port-pins = < 5 1 >;
559	};
560	SPI0_PCS2_PTD5: spi0_pcs2_ptd5 {
561		nxp,kinetis-port-pins = < 5 2 >;
562	};
563	UART0_CTS_b_PTD5: uart0_cts_b_ptd5 {
564		nxp,kinetis-port-pins = < 5 3 >;
565	};
566	FTM0_CH5_PTD5: ftm0_ch5_ptd5 {
567		nxp,kinetis-port-pins = < 5 4 >;
568	};
569	EWM_OUT_b_PTD5: ewm_out_b_ptd5 {
570		nxp,kinetis-port-pins = < 5 6 >;
571	};
572	SPI1_SCK_PTD5: spi1_sck_ptd5 {
573		nxp,kinetis-port-pins = < 5 7 >;
574	};
575	ADC0_SE7b_PTD6: adc0_se7b_ptd6 {
576		nxp,kinetis-port-pins = < 6 0 >;
577	};
578	PTD6: GPIOD_PTD6: LLWU_P15_PTD6: gpiod_ptd6 {
579		nxp,kinetis-port-pins = < 6 1 >;
580	};
581	SPI0_PCS3_PTD6: spi0_pcs3_ptd6 {
582		nxp,kinetis-port-pins = < 6 2 >;
583	};
584	UART0_RX_PTD6: uart0_rx_ptd6 {
585		nxp,kinetis-port-pins = < 6 3 >;
586	};
587	FTM0_CH6_PTD6: ftm0_ch6_ptd6 {
588		nxp,kinetis-port-pins = < 6 4 >;
589	};
590	FTM0_FLT0_PTD6: ftm0_flt0_ptd6 {
591		nxp,kinetis-port-pins = < 6 6 >;
592	};
593	SPI1_SOUT_PTD6: spi1_sout_ptd6 {
594		nxp,kinetis-port-pins = < 6 7 >;
595	};
596	PTD7: GPIOD_PTD7: gpiod_ptd7 {
597		nxp,kinetis-port-pins = < 7 1 >;
598	};
599	UART0_TX_PTD7: uart0_tx_ptd7 {
600		nxp,kinetis-port-pins = < 7 3 >;
601	};
602	FTM0_CH7_PTD7: ftm0_ch7_ptd7 {
603		nxp,kinetis-port-pins = < 7 4 >;
604	};
605	FTM0_FLT1_PTD7: ftm0_flt1_ptd7 {
606		nxp,kinetis-port-pins = < 7 6 >;
607	};
608	SPI1_SIN_PTD7: spi1_sin_ptd7 {
609		nxp,kinetis-port-pins = < 7 7 >;
610	};
611};
612
613&porte {
614	ADC1_SE4a_PTE0: adc1_se4a_pte0 {
615		nxp,kinetis-port-pins = < 0 0 >;
616	};
617	PTE0: GPIOE_PTE0: CLKOUT32K_PTE0: gpioe_pte0 {
618		nxp,kinetis-port-pins = < 0 1 >;
619	};
620	SPI1_PCS1_PTE0: spi1_pcs1_pte0 {
621		nxp,kinetis-port-pins = < 0 2 >;
622	};
623	UART1_TX_PTE0: uart1_tx_pte0 {
624		nxp,kinetis-port-pins = < 0 3 >;
625	};
626	I2C1_SDA_PTE0: i2c1_sda_pte0 {
627		nxp,kinetis-port-pins = < 0 6 >;
628	};
629	RTC_CLKOUT_PTE0: rtc_clkout_pte0 {
630		nxp,kinetis-port-pins = < 0 7 >;
631	};
632	ADC1_SE5a_PTE1: adc1_se5a_pte1 {
633		nxp,kinetis-port-pins = < 1 0 >;
634	};
635	PTE1: GPIOE_PTE1: LLWU_P0_PTE1: gpioe_pte1 {
636		nxp,kinetis-port-pins = < 1 1 >;
637	};
638	SPI1_SOUT_PTE1: spi1_sout_pte1 {
639		nxp,kinetis-port-pins = < 1 2 >;
640	};
641	UART1_RX_PTE1: uart1_rx_pte1 {
642		nxp,kinetis-port-pins = < 1 3 >;
643	};
644	I2C1_SCL_PTE1: i2c1_scl_pte1 {
645		nxp,kinetis-port-pins = < 1 6 >;
646	};
647	SPI1_SIN_PTE1: spi1_sin_pte1 {
648		nxp,kinetis-port-pins = < 1 7 >;
649	};
650};
651
652