1 /**************************************************************************//** 2 * @file epwm.h 3 * @version V3.00 4 * @brief M480 series EPWM driver header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __EPWM_H__ 10 #define __EPWM_H__ 11 12 #ifdef __cplusplus 13 extern "C" 14 { 15 #endif 16 17 18 /** @addtogroup Standard_Driver Standard Driver 19 @{ 20 */ 21 22 /** @addtogroup EPWM_Driver EPWM Driver 23 @{ 24 */ 25 26 /** @addtogroup EPWM_EXPORTED_CONSTANTS EPWM Exported Constants 27 @{ 28 */ 29 #define EPWM_CHANNEL_NUM (6U) /*!< EPWM channel number \hideinitializer */ 30 #define EPWM_CH_0_MASK (0x1U) /*!< EPWM channel 0 mask \hideinitializer */ 31 #define EPWM_CH_1_MASK (0x2U) /*!< EPWM channel 1 mask \hideinitializer */ 32 #define EPWM_CH_2_MASK (0x4U) /*!< EPWM channel 2 mask \hideinitializer */ 33 #define EPWM_CH_3_MASK (0x8U) /*!< EPWM channel 3 mask \hideinitializer */ 34 #define EPWM_CH_4_MASK (0x10U) /*!< EPWM channel 4 mask \hideinitializer */ 35 #define EPWM_CH_5_MASK (0x20U) /*!< EPWM channel 5 mask \hideinitializer */ 36 37 /*---------------------------------------------------------------------------------------------------------*/ 38 /* Counter Type Constant Definitions */ 39 /*---------------------------------------------------------------------------------------------------------*/ 40 #define EPWM_UP_COUNTER (0U) /*!< Up counter type \hideinitializer */ 41 #define EPWM_DOWN_COUNTER (1U) /*!< Down counter type \hideinitializer */ 42 #define EPWM_UP_DOWN_COUNTER (2U) /*!< Up-Down counter type \hideinitializer */ 43 44 /*---------------------------------------------------------------------------------------------------------*/ 45 /* Aligned Type Constant Definitions */ 46 /*---------------------------------------------------------------------------------------------------------*/ 47 #define EPWM_EDGE_ALIGNED (1U) /*!< EPWM working in edge aligned type(down count) \hideinitializer */ 48 #define EPWM_CENTER_ALIGNED (2U) /*!< EPWM working in center aligned type \hideinitializer */ 49 50 /*---------------------------------------------------------------------------------------------------------*/ 51 /* Output Level Constant Definitions */ 52 /*---------------------------------------------------------------------------------------------------------*/ 53 #define EPWM_OUTPUT_NOTHING (0U) /*!< EPWM output nothing \hideinitializer */ 54 #define EPWM_OUTPUT_LOW (1U) /*!< EPWM output low \hideinitializer */ 55 #define EPWM_OUTPUT_HIGH (2U) /*!< EPWM output high \hideinitializer */ 56 #define EPWM_OUTPUT_TOGGLE (3U) /*!< EPWM output toggle \hideinitializer */ 57 58 /*---------------------------------------------------------------------------------------------------------*/ 59 /* Synchronous Start Function Control Constant Definitions */ 60 /*---------------------------------------------------------------------------------------------------------*/ 61 #define EPWM_SSCTL_SSRC_EPWM0 (0U<<EPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from EPWM0 \hideinitializer */ 62 #define EPWM_SSCTL_SSRC_EPWM1 (1U<<EPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from EPWM0 \hideinitializer */ 63 #define EPWM_SSCTL_SSRC_BPWM0 (2UL<<EPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM0 \hideinitializer */ 64 #define EPWM_SSCTL_SSRC_BPWM1 (3UL<<EPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM1 \hideinitializer */ 65 66 /*---------------------------------------------------------------------------------------------------------*/ 67 /* Trigger Source Select Constant Definitions */ 68 /*---------------------------------------------------------------------------------------------------------*/ 69 #define EPWM_TRG_ADC_EVEN_ZERO (0U) /*!< EPWM trigger ADC while counter of even channel matches zero point \hideinitializer */ 70 #define EPWM_TRG_ADC_EVEN_PERIOD (1U) /*!< EPWM trigger ADC while counter of even channel matches period point \hideinitializer */ 71 #define EPWM_TRG_ADC_EVEN_ZERO_PERIOD (2U) /*!< EPWM trigger ADC while counter of even channel matches zero or period point \hideinitializer */ 72 #define EPWM_TRG_ADC_EVEN_COMPARE_UP (3U) /*!< EPWM trigger ADC while counter of even channel matches up count to comparator point \hideinitializer */ 73 #define EPWM_TRG_ADC_EVEN_COMPARE_DOWN (4U) /*!< EPWM trigger ADC while counter of even channel matches down count to comparator point \hideinitializer */ 74 #define EPWM_TRG_ADC_ODD_ZERO (5U) /*!< EPWM trigger ADC while counter of odd channel matches zero point \hideinitializer */ 75 #define EPWM_TRG_ADC_ODD_PERIOD (6U) /*!< EPWM trigger ADC while counter of odd channel matches period point \hideinitializer */ 76 #define EPWM_TRG_ADC_ODD_ZERO_PERIOD (7U) /*!< EPWM trigger ADC while counter of odd channel matches zero or period point \hideinitializer */ 77 #define EPWM_TRG_ADC_ODD_COMPARE_UP (8U) /*!< EPWM trigger ADC while counter of odd channel matches up count to comparator point \hideinitializer */ 78 #define EPWM_TRG_ADC_ODD_COMPARE_DOWN (9U) /*!< EPWM trigger ADC while counter of odd channel matches down count to comparator point \hideinitializer */ 79 #define EPWM_TRG_ADC_CH_0_FREE_CMP_UP (10U) /*!< EPWM trigger ADC while counter of channel 0 matches up count to free comparator point \hideinitializer */ 80 #define EPWM_TRG_ADC_CH_0_FREE_CMP_DOWN (11U) /*!< EPWM trigger ADC while counter of channel 0 matches down count to free comparator point \hideinitializer */ 81 #define EPWM_TRG_ADC_CH_2_FREE_CMP_UP (12U) /*!< EPWM trigger ADC while counter of channel 2 matches up count to free comparator point \hideinitializer */ 82 #define EPWM_TRG_ADC_CH_2_FREE_CMP_DOWN (13U) /*!< EPWM trigger ADC while counter of channel 2 matches down count to free comparator point \hideinitializer */ 83 #define EPWM_TRG_ADC_CH_4_FREE_CMP_UP (14U) /*!< EPWM trigger ADC while counter of channel 4 matches up count to free comparator point \hideinitializer */ 84 #define EPWM_TRG_ADC_CH_4_FREE_CMP_DOWN (15U) /*!< EPWM trigger ADC while counter of channel 4 matches down count to free comparator point \hideinitializer */ 85 86 #define EPWM_TRIGGER_DAC_ZERO (0x1U) /*!< EPWM trigger DAC while counter down count to 0 \hideinitializer */ 87 #define EPWM_TRIGGER_DAC_PERIOD (0x100U) /*!< EPWM trigger DAC while counter matches (PERIOD + 1) \hideinitializer */ 88 #define EPWM_TRIGGER_DAC_COMPARE_UP (0x10000U) /*!< EPWM trigger DAC while counter up count to CMPDAT \hideinitializer */ 89 #define EPWM_TRIGGER_DAC_COMPARE_DOWN (0x1000000U) /*!< EPWM trigger DAC while counter down count to CMPDAT \hideinitializer */ 90 91 /*---------------------------------------------------------------------------------------------------------*/ 92 /* Fail brake Control Constant Definitions */ 93 /*---------------------------------------------------------------------------------------------------------*/ 94 #define EPWM_FB_EDGE_ACMP0 (EPWM_BRKCTL0_1_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source \hideinitializer */ 95 #define EPWM_FB_EDGE_ACMP1 (EPWM_BRKCTL0_1_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source \hideinitializer */ 96 #define EPWM_FB_EDGE_BKP0 (EPWM_BRKCTL0_1_BRKP0EEN_Msk) /*!< BKP0 pin as edge-detect fault brake source \hideinitializer */ 97 #define EPWM_FB_EDGE_BKP1 (EPWM_BRKCTL0_1_BRKP1EEN_Msk) /*!< BKP1 pin as edge-detect fault brake source \hideinitializer */ 98 #define EPWM_FB_EDGE_ADCRM (EPWM_BRKCTL0_1_EADCEBEN_Msk) /*!< ADC Result Monitor (ADCRM) as edge-detect fault brake source \hideinitializer */ 99 #define EPWM_FB_EDGE_SYS_CSS (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as edge-detect fault brake source \hideinitializer */ 100 #define EPWM_FB_EDGE_SYS_BOD (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as edge-detect fault brake source \hideinitializer */ 101 #define EPWM_FB_EDGE_SYS_RAM (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source \hideinitializer */ 102 #define EPWM_FB_EDGE_SYS_COR (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as edge-detect fault brake source \hideinitializer */ 103 104 #define EPWM_FB_LEVEL_ACMP0 (EPWM_BRKCTL0_1_CPO0LBEN_Msk) /*!< Comparator 0 as level-detect fault brake source \hideinitializer */ 105 #define EPWM_FB_LEVEL_ACMP1 (EPWM_BRKCTL0_1_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source \hideinitializer */ 106 #define EPWM_FB_LEVEL_BKP0 (EPWM_BRKCTL0_1_BRKP0LEN_Msk) /*!< BKP0 pin as level-detect fault brake source \hideinitializer */ 107 #define EPWM_FB_LEVEL_BKP1 (EPWM_BRKCTL0_1_BRKP1LEN_Msk) /*!< BKP1 pin as level-detect fault brake source \hideinitializer */ 108 #define EPWM_FB_LEVEL_ADCRM (EPWM_BRKCTL0_1_EADCLBEN_Msk) /*!< ADC Result Monitor (ADCRM) as level-detect fault brake source \hideinitializer */ 109 #define EPWM_FB_LEVEL_SYS_CSS (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as level-detect fault brake source \hideinitializer */ 110 #define EPWM_FB_LEVEL_SYS_BOD (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as level-detect fault brake source \hideinitializer */ 111 #define EPWM_FB_LEVEL_SYS_RAM (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as level-detect fault brake source \hideinitializer */ 112 #define EPWM_FB_LEVEL_SYS_COR (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as level-detect fault brake source \hideinitializer */ 113 114 #define EPWM_FB_EDGE (0U) /*!< edge-detect fault brake \hideinitializer */ 115 #define EPWM_FB_LEVEL (8U) /*!< level-detect fault brake \hideinitializer */ 116 117 /*---------------------------------------------------------------------------------------------------------*/ 118 /* Leading Edge Blanking Control Constant Definitions */ 119 /*---------------------------------------------------------------------------------------------------------*/ 120 #define EPWM_LEBCTL_TRGTYPE_RISING (0U<<EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM Leading Edge Blanking Trigger Type Is Rising Edge \hideinitializer */ 121 #define EPWM_LEBCTL_TRGTYPE_FALLING (1U<<EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM Leading Edge Blanking Trigger Type Is Falling Edge \hideinitializer */ 122 #define EPWM_LEBCTL_TRGTYPE_RISING_OR_FALLING (2U<<EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM Leading Edge Blanking Trigger Type Is Rising or Falling Edge \hideinitializer */ 123 #define EPWM_LEBCTL_SRCEN0 (EPWM_LEBCTL_SRCEN0_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0 Enable \hideinitializer */ 124 #define EPWM_LEBCTL_SRCEN2 (EPWM_LEBCTL_SRCEN2_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH2 Enable \hideinitializer */ 125 #define EPWM_LEBCTL_SRCEN4 (EPWM_LEBCTL_SRCEN4_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH4 Enable \hideinitializer */ 126 #define EPWM_LEBCTL_SRCEN0_2 (EPWM_LEBCTL_SRCEN0_Msk|EPWM_LEBCTL_SRCEN2_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0 and EPWMx_CH2 Enable \hideinitializer */ 127 #define EPWM_LEBCTL_SRCEN0_4 (EPWM_LEBCTL_SRCEN0_Msk|EPWM_LEBCTL_SRCEN4_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0 and EPWMx_CH4 Enable \hideinitializer */ 128 #define EPWM_LEBCTL_SRCEN2_4 (EPWM_LEBCTL_SRCEN2_Msk|EPWM_LEBCTL_SRCEN4_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH2 and EPWMx_CH4 Enable \hideinitializer */ 129 #define EPWM_LEBCTL_SRCEN0_2_4 (EPWM_LEBCTL_SRCEN0_Msk|EPWM_LEBCTL_SRCEN2_Msk|EPWM_LEBCTL_SRCEN4_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0, EPWMx_CH2 and EPWMx_CH4 Enable \hideinitializer */ 130 131 /*---------------------------------------------------------------------------------------------------------*/ 132 /* Capture Control Constant Definitions */ 133 /*---------------------------------------------------------------------------------------------------------*/ 134 #define EPWM_CAPTURE_INT_RISING_LATCH (1U) /*!< EPWM capture interrupt if channel has rising transition \hideinitializer */ 135 #define EPWM_CAPTURE_INT_FALLING_LATCH (0x100U) /*!< EPWM capture interrupt if channel has falling transition \hideinitializer */ 136 137 #define EPWM_CAPTURE_PDMA_RISING_LATCH (0x2U) /*!< EPWM capture rising latched data transfer by PDMA \hideinitializer */ 138 #define EPWM_CAPTURE_PDMA_FALLING_LATCH (0x4U) /*!< EPWM capture falling latched data transfer by PDMA \hideinitializer */ 139 #define EPWM_CAPTURE_PDMA_RISING_FALLING_LATCH (0x6U) /*!< EPWM capture rising and falling latched data transfer by PDMA \hideinitializer */ 140 141 /*---------------------------------------------------------------------------------------------------------*/ 142 /* Duty Interrupt Type Constant Definitions */ 143 /*---------------------------------------------------------------------------------------------------------*/ 144 #define EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP (1U << EPWM_INTEN0_CMPDIEN0_Pos) /*!< EPWM duty interrupt triggered if down count match comparator \hideinitializer */ 145 #define EPWM_DUTY_INT_UP_COUNT_MATCH_CMP (1U << EPWM_INTEN0_CMPUIEN0_Pos) /*!< EPWM duty interrupt triggered if up down match comparator \hideinitializer */ 146 147 /*---------------------------------------------------------------------------------------------------------*/ 148 /* Interrupt Flag Accumulator Constant Definitions */ 149 /*---------------------------------------------------------------------------------------------------------*/ 150 #define EPWM_IFA_ZERO_POINT (0U) /*!< EPWM counter equal to zero \hideinitializer */ 151 #define EPWM_IFA_PERIOD_POINT (1U) /*!< EPWM counter equal to period \hideinitializer */ 152 #define EPWM_IFA_COMPARE_UP_COUNT_POINT (2U) /*!< EPWM counter up count to comparator value \hideinitializer */ 153 #define EPWM_IFA_COMPARE_DOWN_COUNT_POINT (3U) /*!< EPWM counter down count to comparator value \hideinitializer */ 154 155 /*---------------------------------------------------------------------------------------------------------*/ 156 /* Load Mode Constant Definitions */ 157 /*---------------------------------------------------------------------------------------------------------*/ 158 #define EPWM_LOAD_MODE_IMMEDIATE (1U << EPWM_CTL0_IMMLDEN0_Pos) /*!< EPWM immediately load mode \hideinitializer */ 159 #define EPWM_LOAD_MODE_WINDOW (1U << EPWM_CTL0_WINLDEN0_Pos) /*!< EPWM window load mode \hideinitializer */ 160 #define EPWM_LOAD_MODE_CENTER (1U << EPWM_CTL0_CTRLD0_Pos) /*!< EPWM center load mode \hideinitializer */ 161 162 /*---------------------------------------------------------------------------------------------------------*/ 163 /* Synchronize Control Constant Definitions */ 164 /*---------------------------------------------------------------------------------------------------------*/ 165 #define EPWM_SYNC_OUT_FROM_SYNCIN_SWSYNC (0U) /*!< Synchronize source from SYNC_IN or SWSYNC \hideinitializer */ 166 #define EPWM_SYNC_OUT_FROM_COUNT_TO_ZERO (1U) /*!< Synchronize source from counter equal to 0 \hideinitializer */ 167 #define EPWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR (2U) /*!< Synchronize source from counter equal to CMPDAT1, CMPDAT3, CMPDAT5 \hideinitializer */ 168 #define EPWM_SYNC_OUT_DISABLE (3U) /*!< SYNC_OUT will not be generated \hideinitializer */ 169 #define EPWM_PHS_DIR_DECREMENT (0U) /*!< EPWM counter count decrement \hideinitializer */ 170 #define EPWM_PHS_DIR_INCREMENT (1U) /*!< EPWM counter count increment \hideinitializer */ 171 172 /*---------------------------------------------------------------------------------------------------------*/ 173 /* Noise Filter Clock Divide Select Constant Definitions */ 174 /*---------------------------------------------------------------------------------------------------------*/ 175 #define EPWM_NF_CLK_DIV_1 (0U) /*!< Noise filter clock is HCLK divide by 1 \hideinitializer */ 176 #define EPWM_NF_CLK_DIV_2 (1U) /*!< Noise filter clock is HCLK divide by 2 \hideinitializer */ 177 #define EPWM_NF_CLK_DIV_4 (2U) /*!< Noise filter clock is HCLK divide by 4 \hideinitializer */ 178 #define EPWM_NF_CLK_DIV_8 (3U) /*!< Noise filter clock is HCLK divide by 8 \hideinitializer */ 179 #define EPWM_NF_CLK_DIV_16 (4U) /*!< Noise filter clock is HCLK divide by 16 \hideinitializer */ 180 #define EPWM_NF_CLK_DIV_32 (5U) /*!< Noise filter clock is HCLK divide by 32 \hideinitializer */ 181 #define EPWM_NF_CLK_DIV_64 (6U) /*!< Noise filter clock is HCLK divide by 64 \hideinitializer */ 182 #define EPWM_NF_CLK_DIV_128 (7U) /*!< Noise filter clock is HCLK divide by 128 \hideinitializer */ 183 184 /*---------------------------------------------------------------------------------------------------------*/ 185 /* Clock Source Select Constant Definitions */ 186 /*---------------------------------------------------------------------------------------------------------*/ 187 #define EPWM_CLKSRC_EPWM_CLK (0U) /*!< EPWM Clock source selects to EPWM0_CLK or EPWM1_CLK \hideinitializer */ 188 #define EPWM_CLKSRC_TIMER0 (1U) /*!< EPWM Clock source selects to TIMER0 overflow \hideinitializer */ 189 #define EPWM_CLKSRC_TIMER1 (2U) /*!< EPWM Clock source selects to TIMER1 overflow \hideinitializer */ 190 #define EPWM_CLKSRC_TIMER2 (3U) /*!< EPWM Clock source selects to TIMER2 overflow \hideinitializer */ 191 #define EPWM_CLKSRC_TIMER3 (4U) /*!< EPWM Clock source selects to TIMER3 overflow \hideinitializer */ 192 193 194 /*@}*/ /* end of group EPWM_EXPORTED_CONSTANTS */ 195 196 197 /** @addtogroup EPWM_EXPORTED_FUNCTIONS EPWM Exported Functions 198 @{ 199 */ 200 201 /** 202 * @brief This macro enable complementary mode 203 * @param[in] epwm The pointer of the specified EPWM module 204 * @return None 205 * @details This macro is used to enable complementary mode of EPWM module. 206 * \hideinitializer 207 */ 208 #define EPWM_ENABLE_COMPLEMENTARY_MODE(epwm) ((epwm)->CTL1 = (epwm)->CTL1 | (0x7ul<<EPWM_CTL1_OUTMODE0_Pos)) 209 210 /** 211 * @brief This macro disable complementary mode, and enable independent mode. 212 * @param[in] epwm The pointer of the specified EPWM module 213 * @return None 214 * @details This macro is used to disable complementary mode of EPWM module. 215 * \hideinitializer 216 */ 217 #define EPWM_DISABLE_COMPLEMENTARY_MODE(epwm) ((epwm)->CTL1 = (epwm)->CTL1 & ~(0x7ul<<EPWM_CTL1_OUTMODE0_Pos)) 218 219 /** 220 * @brief This macro enable group mode 221 * @param[in] epwm The pointer of the specified EPWM module 222 * @return None 223 * @details This macro is used to enable group mode of EPWM module. 224 * \hideinitializer 225 */ 226 #define EPWM_ENABLE_GROUP_MODE(epwm) ((epwm)->CTL0 = (epwm)->CTL0 | EPWM_CTL0_GROUPEN_Msk) 227 228 /** 229 * @brief This macro disable group mode 230 * @param[in] epwm The pointer of the specified EPWM module 231 * @return None 232 * @details This macro is used to disable group mode of EPWM module. 233 * \hideinitializer 234 */ 235 #define EPWM_DISABLE_GROUP_MODE(epwm) ((epwm)->CTL0 = (epwm)->CTL0 & ~EPWM_CTL0_GROUPEN_Msk) 236 237 /** 238 * @brief Enable timer synchronous start counting function of specified channel(s) 239 * @param[in] epwm The pointer of the specified EPWM module 240 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 241 * Bit 0 represents channel 0, bit 1 represents channel 1... 242 * @param[in] u32SyncSrc Synchronous start source selection, valid values are: 243 * - \ref EPWM_SSCTL_SSRC_EPWM0 244 * - \ref EPWM_SSCTL_SSRC_EPWM1 245 * - \ref EPWM_SSCTL_SSRC_BPWM0 246 * - \ref EPWM_SSCTL_SSRC_BPWM1 247 * @return None 248 * @details This macro is used to enable timer synchronous start counting function of specified channel(s). 249 * \hideinitializer 250 */ 251 #define EPWM_ENABLE_TIMER_SYNC(epwm, u32ChannelMask, u32SyncSrc) ((epwm)->SSCTL = ((epwm)->SSCTL & ~EPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | (u32ChannelMask)) 252 253 /** 254 * @brief Disable timer synchronous start counting function of specified channel(s) 255 * @param[in] epwm The pointer of the specified EPWM module 256 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 257 * Bit 0 represents channel 0, bit 1 represents channel 1... 258 * @return None 259 * @details This macro is used to disable timer synchronous start counting function of specified channel(s). 260 * \hideinitializer 261 */ 262 #define EPWM_DISABLE_TIMER_SYNC(epwm, u32ChannelMask) \ 263 do{ \ 264 int i;\ 265 for(i = 0; i < 6; i++) { \ 266 if((u32ChannelMask) & (1 << i)) \ 267 (epwm)->SSCTL &= ~(1UL << i); \ 268 } \ 269 }while(0) 270 271 /** 272 * @brief This macro enable EPWM counter synchronous start counting function. 273 * @param[in] epwm The pointer of the specified EPWM module 274 * @return None 275 * @details This macro is used to make selected EPWM0 and EPWM1 channel(s) start counting at the same time. 276 * To configure synchronous start counting channel(s) by EPWM_ENABLE_TIMER_SYNC() and EPWM_DISABLE_TIMER_SYNC(). 277 * \hideinitializer 278 */ 279 #define EPWM_TRIGGER_SYNC_START(epwm) ((epwm)->SSTRG = EPWM_SSTRG_CNTSEN_Msk) 280 281 /** 282 * @brief This macro enable output inverter of specified channel(s) 283 * @param[in] epwm The pointer of the specified EPWM module 284 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 285 * Bit 0 represents channel 0, bit 1 represents channel 1... 286 * @return None 287 * @details This macro is used to enable output inverter of specified channel(s). 288 * \hideinitializer 289 */ 290 #define EPWM_ENABLE_OUTPUT_INVERTER(epwm, u32ChannelMask) ((epwm)->POLCTL = (u32ChannelMask)) 291 292 /** 293 * @brief This macro get captured rising data 294 * @param[in] epwm The pointer of the specified EPWM module 295 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 296 * @return None 297 * @details This macro is used to get captured rising data of specified channel. 298 * \hideinitializer 299 */ 300 #define EPWM_GET_CAPTURE_RISING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].RCAPDAT) 301 302 /** 303 * @brief This macro get captured falling data 304 * @param[in] epwm The pointer of the specified EPWM module 305 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 306 * @return None 307 * @details This macro is used to get captured falling data of specified channel. 308 * \hideinitializer 309 */ 310 #define EPWM_GET_CAPTURE_FALLING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].FCAPDAT) 311 312 /** 313 * @brief This macro mask output logic to high or low 314 * @param[in] epwm The pointer of the specified EPWM module 315 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 316 * Bit 0 represents channel 0, bit 1 represents channel 1... 317 * @param[in] u32LevelMask Output logic to high or low 318 * @return None 319 * @details This macro is used to mask output logic to high or low of specified channel(s). 320 * @note If u32ChannelMask parameter is 0, then mask function will be disabled. 321 * \hideinitializer 322 */ 323 #define EPWM_MASK_OUTPUT(epwm, u32ChannelMask, u32LevelMask) \ 324 { \ 325 (epwm)->MSKEN = (u32ChannelMask); \ 326 (epwm)->MSK = (u32LevelMask); \ 327 } 328 329 /** 330 * @brief This macro set the prescaler of the selected channel 331 * @param[in] epwm The pointer of the specified EPWM module 332 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 333 * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF 334 * @return None 335 * @details This macro is used to set the prescaler of specified channel. 336 * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected. 337 * The clock of EPWM counter is divided by (u32Prescaler + 1). 338 * \hideinitializer 339 */ 340 #define EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescaler) ((epwm)->CLKPSC[(u32ChannelNum) >> 1] = (u32Prescaler)) 341 342 /** 343 * @brief This macro get the prescaler of the selected channel 344 * @param[in] epwm The pointer of the specified EPWM module 345 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 346 * @return Return Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF 347 * @details This macro is used to get the prescaler of specified channel. 348 * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected. 349 * The clock of EPWM counter is divided by (u32Prescaler + 1). 350 * \hideinitializer 351 */ 352 #define EPWM_GET_PRESCALER(epwm, u32ChannelNum) ((epwm)->CLKPSC[(u32ChannelNum) >> 1U]) 353 354 /** 355 * @brief This macro set the comparator of the selected channel 356 * @param[in] epwm The pointer of the specified EPWM module 357 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 358 * @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF 359 * @return None 360 * @details This macro is used to set the comparator of specified channel. 361 * @note This new setting will take effect on next EPWM period. 362 * \hideinitializer 363 */ 364 #define EPWM_SET_CMR(epwm, u32ChannelNum, u32CMR) ((epwm)->CMPDAT[(u32ChannelNum)]= (u32CMR)) 365 366 /** 367 * @brief This macro get the comparator of the selected channel 368 * @param[in] epwm The pointer of the specified EPWM module 369 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 370 * @return Return the comparator of specified channel. Valid values are between 0~0xFFFF 371 * @details This macro is used to get the comparator of specified channel. 372 * \hideinitializer 373 */ 374 #define EPWM_GET_CMR(epwm, u32ChannelNum) ((epwm)->CMPDAT[(u32ChannelNum)]) 375 376 /** 377 * @brief This macro set the free trigger comparator of the selected channel 378 * @param[in] epwm The pointer of the specified EPWM module 379 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 380 * @param[in] u32FTCMR Free trigger comparator of specified channel. Valid values are between 0~0xFFFF 381 * @return None 382 * @details This macro is used to set the free trigger comparator of specified channel. 383 * @note This new setting will take effect on next EPWM period. 384 * \hideinitializer 385 */ 386 #define EPWM_SET_FTCMR(epwm, u32ChannelNum, u32FTCMR) (((epwm)->FTCMPDAT[((u32ChannelNum) >> 1U)]) = (u32FTCMR)) 387 388 /** 389 * @brief This macro set the period of the selected channel 390 * @param[in] epwm The pointer of the specified EPWM module 391 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 392 * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF 393 * @return None 394 * @details This macro is used to set the period of specified channel. 395 * @note This new setting will take effect on next EPWM period. 396 * @note EPWM counter will stop if period length set to 0. 397 * \hideinitializer 398 */ 399 #define EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR) ((epwm)->PERIOD[(u32ChannelNum)] = (u32CNR)) 400 401 /** 402 * @brief This macro get the period of the selected channel 403 * @param[in] epwm The pointer of the specified EPWM module 404 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 405 * @return Return the period of specified channel. Valid values are between 0~0xFFFF 406 * @details This macro is used to get the period of specified channel. 407 * \hideinitializer 408 */ 409 #define EPWM_GET_CNR(epwm, u32ChannelNum) ((epwm)->PERIOD[(u32ChannelNum)]) 410 411 /** 412 * @brief This macro set the EPWM aligned type 413 * @param[in] epwm The pointer of the specified EPWM module 414 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 415 * Bit 0 represents channel 0, bit 1 represents channel 1... 416 * @param[in] u32AlignedType EPWM aligned type, valid values are: 417 * - \ref EPWM_EDGE_ALIGNED 418 * - \ref EPWM_CENTER_ALIGNED 419 * @return None 420 * @details This macro is used to set the EPWM aligned type of specified channel(s). 421 * \hideinitializer 422 */ 423 #define EPWM_SET_ALIGNED_TYPE(epwm, u32ChannelMask, u32AlignedType) \ 424 do{ \ 425 int i; \ 426 for(i = 0; i < 6; i++) { \ 427 if((u32ChannelMask) & (1 << i)) \ 428 (epwm)->CTL1 = (((epwm)->CTL1 & ~(3UL << (i << 1))) | ((u32AlignedType) << (i << 1))); \ 429 } \ 430 }while(0) 431 432 /** 433 * @brief Set load window of window loading mode for specified channel(s) 434 * @param[in] epwm The pointer of the specified EPWM module 435 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 436 * Bit 0 represents channel 0, bit 1 represents channel 1... 437 * @return None 438 * @details This macro is used to set load window of window loading mode for specified channel(s). 439 * \hideinitializer 440 */ 441 #define EPWM_SET_LOAD_WINDOW(epwm, u32ChannelMask) ((epwm)->LOAD |= (u32ChannelMask)) 442 443 /** 444 * @brief Trigger synchronous event from specified channel(s) 445 * @param[in] epwm The pointer of the specified EPWM module 446 * @param[in] u32ChannelNum EPWM channel number. Valid values are 0, 2, 4 447 * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 448 * @return None 449 * @details This macro is used to trigger synchronous event from specified channel(s). 450 * \hideinitializer 451 */ 452 #define EPWM_TRIGGER_SYNC(epwm, u32ChannelNum) ((epwm)->SWSYNC |= (1 << ((u32ChannelNum) >> 1))) 453 454 /** 455 * @brief Clear counter of specified channel(s) 456 * @param[in] epwm The pointer of the specified EPWM module 457 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 458 * Bit 0 represents channel 0, bit 1 represents channel 1... 459 * @return None 460 * @details This macro is used to clear counter of specified channel(s). 461 * \hideinitializer 462 */ 463 #define EPWM_CLR_COUNTER(epwm, u32ChannelMask) ((epwm)->CNTCLR |= (u32ChannelMask)) 464 465 /** 466 * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s) 467 * @param[in] epwm The pointer of the specified EPWM module 468 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 469 * Bit 0 represents channel 0, bit 1 represents channel 1... 470 * @param[in] u32ZeroLevel output level at zero point, valid values are: 471 * - \ref EPWM_OUTPUT_NOTHING 472 * - \ref EPWM_OUTPUT_LOW 473 * - \ref EPWM_OUTPUT_HIGH 474 * - \ref EPWM_OUTPUT_TOGGLE 475 * @param[in] u32CmpUpLevel output level at compare up point, valid values are: 476 * - \ref EPWM_OUTPUT_NOTHING 477 * - \ref EPWM_OUTPUT_LOW 478 * - \ref EPWM_OUTPUT_HIGH 479 * - \ref EPWM_OUTPUT_TOGGLE 480 * @param[in] u32PeriodLevel output level at period(center) point, valid values are: 481 * - \ref EPWM_OUTPUT_NOTHING 482 * - \ref EPWM_OUTPUT_LOW 483 * - \ref EPWM_OUTPUT_HIGH 484 * - \ref EPWM_OUTPUT_TOGGLE 485 * @param[in] u32CmpDownLevel output level at compare down point, valid values are: 486 * - \ref EPWM_OUTPUT_NOTHING 487 * - \ref EPWM_OUTPUT_LOW 488 * - \ref EPWM_OUTPUT_HIGH 489 * - \ref EPWM_OUTPUT_TOGGLE 490 * @return None 491 * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s). 492 * \hideinitializer 493 */ 494 #define EPWM_SET_OUTPUT_LEVEL(epwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \ 495 do{ \ 496 int i; \ 497 for(i = 0; i < 6; i++) { \ 498 if((u32ChannelMask) & (1 << i)) { \ 499 (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1))); \ 500 (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))) | ((u32PeriodLevel) << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))); \ 501 (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (i << 1))) | ((u32CmpUpLevel) << (i << 1))); \ 502 (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))) | ((u32CmpDownLevel) << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))); \ 503 } \ 504 } \ 505 }while(0) 506 507 /** 508 * @brief Trigger brake event from specified channel(s) 509 * @param[in] epwm The pointer of the specified EPWM module 510 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 511 * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 512 * @param[in] u32BrakeType Type of brake trigger. 513 * - \ref EPWM_FB_EDGE 514 * - \ref EPWM_FB_LEVEL 515 * @return None 516 * @details This macro is used to trigger brake event from specified channel(s). 517 * \hideinitializer 518 */ 519 #define EPWM_TRIGGER_BRAKE(epwm, u32ChannelMask, u32BrakeType) ((epwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType))) 520 521 /** 522 * @brief Set Dead zone clock source 523 * @param[in] epwm The pointer of the specified EPWM module 524 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 525 * @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler). 526 * @return None 527 * @details This macro is used to set Dead zone clock source. Every two channels share the same setting. 528 * @note The write-protection function should be disabled before using this function. 529 * \hideinitializer 530 */ 531 #define EPWM_SET_DEADZONE_CLK_SRC(epwm, u32ChannelNum, u32AfterPrescaler) \ 532 ((epwm)->DTCTL[(u32ChannelNum) >> 1] = (((epwm)->DTCTL[(u32ChannelNum) >> 1] & ~EPWM_DTCTL0_1_DTCKSEL_Msk) | \ 533 ((u32AfterPrescaler) << EPWM_DTCTL0_1_DTCKSEL_Pos))) 534 535 /*---------------------------------------------------------------------------------------------------------*/ 536 /* Define EPWM functions prototype */ 537 /*---------------------------------------------------------------------------------------------------------*/ 538 uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge); 539 uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle); 540 void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask); 541 void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask); 542 void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask); 543 void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); 544 void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum); 545 void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); 546 uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 547 void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); 548 void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum); 549 void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); 550 uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 551 void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource); 552 void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask); 553 void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask); 554 void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask); 555 void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask); 556 void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode); 557 void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum); 558 void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration); 559 void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum); 560 void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); 561 void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); 562 void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); 563 uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 564 void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType); 565 void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum); 566 void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 567 uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 568 void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource); 569 void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource); 570 void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource); 571 uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource); 572 void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType); 573 void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum); 574 void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 575 uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 576 void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum); 577 void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum); 578 void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 579 uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 580 void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc); 581 void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum); 582 void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); 583 void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); 584 void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); 585 uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); 586 void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum); 587 void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum); 588 void EPWM_EnableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum); 589 void EPWM_DisableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum); 590 void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 591 uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 592 void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); 593 void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); 594 void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase); 595 void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask); 596 void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask); 597 void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel); 598 void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm); 599 void EPWM_EnableSyncPinInverse(EPWM_T *epwm); 600 void EPWM_DisableSyncPinInverse(EPWM_T *epwm); 601 void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel); 602 void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel); 603 void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum); 604 void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum); 605 void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum); 606 void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule); 607 void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable); 608 uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 609 void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 610 611 /*@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */ 612 613 /*@}*/ /* end of group EPWM_Driver */ 614 615 /*@}*/ /* end of group Standard_Driver */ 616 617 #ifdef __cplusplus 618 } 619 #endif 620 621 #endif /* __EPWM_H__ */ 622 623 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ 624
