1 /**************************************************************************//** 2 * @file eadc.h 3 * @version V0.10 4 * @brief M480 series EADC driver header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __EADC_H__ 10 #define __EADC_H__ 11 12 #ifdef __cplusplus 13 extern "C" 14 { 15 #endif 16 17 18 /** @addtogroup Standard_Driver Standard Driver 19 @{ 20 */ 21 22 /** @addtogroup EADC_Driver EADC Driver 23 @{ 24 */ 25 26 /** @addtogroup EADC_EXPORTED_CONSTANTS EADC Exported Constants 27 @{ 28 */ 29 30 /*---------------------------------------------------------------------------------------------------------*/ 31 /* EADC_CTL Constant Definitions */ 32 /*---------------------------------------------------------------------------------------------------------*/ 33 #define EADC_CTL_DIFFEN_SINGLE_END (0UL<<EADC_CTL_DIFFEN_Pos) /*!< Single-end input mode \hideinitializer */ 34 #define EADC_CTL_DIFFEN_DIFFERENTIAL (1UL<<EADC_CTL_DIFFEN_Pos) /*!< Differential input mode \hideinitializer */ 35 36 #define EADC_CTL_DMOF_STRAIGHT_BINARY (0UL<<EADC_CTL_DMOF_Pos) /*!< Select the straight binary format as the output format of the conversion result \hideinitializer */ 37 #define EADC_CTL_DMOF_TWOS_COMPLEMENT (1UL<<EADC_CTL_DMOF_Pos) /*!< Select the 2's complement format as the output format of the conversion result \hideinitializer */ 38 39 /*---------------------------------------------------------------------------------------------------------*/ 40 /* EADC_SCTL Constant Definitions */ 41 /*---------------------------------------------------------------------------------------------------------*/ 42 #define EADC_SCTL_CHSEL(x) ((x) << EADC_SCTL_CHSEL_Pos) /*!< A/D sample module channel selection \hideinitializer */ 43 #define EADC_SCTL_TRGDLYDIV(x) ((x) << EADC_SCTL_TRGDLYDIV_Pos) /*!< A/D sample module start of conversion trigger delay clock divider selection \hideinitializer */ 44 #define EADC_SCTL_TRGDLYCNT(x) ((x) << EADC_SCTL_TRGDLYCNT_Pos) /*!< A/D sample module start of conversion trigger delay time \hideinitializer */ 45 46 #define EADC_SOFTWARE_TRIGGER (0UL<<EADC_SCTL_TRGSEL_Pos) /*!< Software trigger \hideinitializer */ 47 #define EADC_FALLING_EDGE_TRIGGER (EADC_SCTL_EXTFEN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin falling edge trigger \hideinitializer */ 48 #define EADC_RISING_EDGE_TRIGGER (EADC_SCTL_EXTREN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin rising edge trigger \hideinitializer */ 49 #define EADC_FALLING_RISING_EDGE_TRIGGER (EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin both falling and rising edge trigger \hideinitializer */ 50 #define EADC_ADINT0_TRIGGER (2UL<<EADC_SCTL_TRGSEL_Pos) /*!< ADC ADINT0 interrupt EOC pulse trigger \hideinitializer */ 51 #define EADC_ADINT1_TRIGGER (3UL<<EADC_SCTL_TRGSEL_Pos) /*!< ADC ADINT1 interrupt EOC pulse trigger \hideinitializer */ 52 #define EADC_TIMER0_TRIGGER (4UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer0 overflow pulse trigger \hideinitializer */ 53 #define EADC_TIMER1_TRIGGER (5UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer1 overflow pulse trigger \hideinitializer */ 54 #define EADC_TIMER2_TRIGGER (6UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer2 overflow pulse trigger \hideinitializer */ 55 #define EADC_TIMER3_TRIGGER (7UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer3 overflow pulse trigger \hideinitializer */ 56 #define EADC_EPWM0TG0_TRIGGER (8UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG0 trigger \hideinitializer */ 57 #define EADC_EPWM0TG1_TRIGGER (9UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG1 trigger \hideinitializer */ 58 #define EADC_EPWM0TG2_TRIGGER (0xAUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG2 trigger \hideinitializer */ 59 #define EADC_EPWM0TG3_TRIGGER (0xBUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG3 trigger \hideinitializer */ 60 #define EADC_EPWM0TG4_TRIGGER (0xCUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG4 trigger \hideinitializer */ 61 #define EADC_EPWM0TG5_TRIGGER (0xDUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG5 trigger \hideinitializer */ 62 #define EADC_EPWM1TG0_TRIGGER (0xEUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG0 trigger \hideinitializer */ 63 #define EADC_EPWM1TG1_TRIGGER (0xFUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG1 trigger \hideinitializer */ 64 #define EADC_EPWM1TG2_TRIGGER (0x10UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG2 trigger \hideinitializer */ 65 #define EADC_EPWM1TG3_TRIGGER (0x11UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG3 trigger \hideinitializer */ 66 #define EADC_EPWM1TG4_TRIGGER (0x12UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG4 trigger \hideinitializer */ 67 #define EADC_EPWM1TG5_TRIGGER (0x13UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG5 trigger \hideinitializer */ 68 #define EADC_BPWM0TG_TRIGGER (0x14UL<<EADC_SCTL_TRGSEL_Pos) /*!< BPWM0TG trigger \hideinitializer */ 69 #define EADC_BPWM1TG_TRIGGER (0x15UL<<EADC_SCTL_TRGSEL_Pos) /*!< BPWM1TG trigger \hideinitializer */ 70 71 #define EADC_SCTL_TRGDLYDIV_DIVIDER_1 (0<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/1 \hideinitializer */ 72 #define EADC_SCTL_TRGDLYDIV_DIVIDER_2 (0x1UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/2 \hideinitializer */ 73 #define EADC_SCTL_TRGDLYDIV_DIVIDER_4 (0x2UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/4 \hideinitializer */ 74 #define EADC_SCTL_TRGDLYDIV_DIVIDER_16 (0x3UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/16 \hideinitializer */ 75 76 77 /*---------------------------------------------------------------------------------------------------------*/ 78 /* EADC_CMP Constant Definitions */ 79 /*---------------------------------------------------------------------------------------------------------*/ 80 #define EADC_CMP_CMPCOND_LESS_THAN (0UL<<EADC_CMP_CMPCOND_Pos) /*!< The compare condition is "less than" \hideinitializer */ 81 #define EADC_CMP_CMPCOND_GREATER_OR_EQUAL (1UL<<EADC_CMP_CMPCOND_Pos) /*!< The compare condition is "greater than or equal to" \hideinitializer */ 82 #define EADC_CMP_CMPWEN_ENABLE (EADC_CMP_CMPWEN_Msk) /*!< Compare window mode enable \hideinitializer */ 83 #define EADC_CMP_CMPWEN_DISABLE (~EADC_CMP_CMPWEN_Msk) /*!< Compare window mode disable \hideinitializer */ 84 #define EADC_CMP_ADCMPIE_ENABLE (EADC_CMP_ADCMPIE_Msk) /*!< A/D result compare interrupt enable \hideinitializer */ 85 #define EADC_CMP_ADCMPIE_DISABLE (~EADC_CMP_ADCMPIE_Msk) /*!< A/D result compare interrupt disable \hideinitializer */ 86 87 /*@}*/ /* end of group EADC_EXPORTED_CONSTANTS */ 88 89 /** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions 90 @{ 91 */ 92 /*---------------------------------------------------------------------------------------------------------*/ 93 /* EADC Macro Definitions */ 94 /*---------------------------------------------------------------------------------------------------------*/ 95 96 /** 97 * @brief A/D Converter Control Circuits Reset. 98 * @param[in] eadc The pointer of the specified EADC module. 99 * @return None 100 * @details ADCRST bit (EADC_CT[1]) remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0. 101 * \hideinitializer 102 */ 103 #define EADC_CONV_RESET(eadc) ((eadc)->CTL |= EADC_CTL_ADCRST_Msk) 104 105 /** 106 * @brief Enable PDMA transfer. 107 * @param[in] eadc The pointer of the specified EADC module. 108 * @return None 109 * @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, 110 * user can enable this bit to generate a PDMA data transfer request. 111 * @note When set PDMAEN bit (EADC_CTL[11]), user must set ADINTENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt. 112 * \hideinitializer 113 */ 114 #define EADC_ENABLE_PDMA(eadc) ((eadc)->CTL |= EADC_CTL_PDMAEN_Msk) 115 116 /** 117 * @brief Disable PDMA transfer. 118 * @param[in] eadc The pointer of the specified EADC module. 119 * @return None 120 * @details This macro is used to disable PDMA transfer. 121 * \hideinitializer 122 */ 123 #define EADC_DISABLE_PDMA(eadc) ((eadc)->CTL &= (~EADC_CTL_PDMAEN_Msk)) 124 125 /** 126 * @brief Enable Sample Module PDMA transfer. 127 * @param[in] eadc The pointer of the specified EADC module. 128 * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. 129 * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. 130 * @return None 131 * @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, 132 * user can enable this bit to generate a PDMA data transfer request. 133 * \hideinitializer 134 */ 135 #define EADC_ENABLE_SAMPLE_MODULE_PDMA(eadc, u32ModuleMask) ((eadc)->PDMACTL |= u32ModuleMask) 136 137 /** 138 * @brief Disable Sample Module PDMA transfer. 139 * @param[in] eadc The pointer of the specified EADC module. 140 * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. 141 * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. 142 * @return None 143 * @details This macro is used to disable sample module PDMA transfer. 144 * \hideinitializer 145 */ 146 #define EADC_DISABLE_SAMPLE_MODULE_PDMA(eadc, u32ModuleMask) ((eadc)->PDMACTL &= (~u32ModuleMask)) 147 148 /** 149 * @brief Enable double buffer mode. 150 * @param[in] eadc The pointer of the specified EADC module. 151 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3. 152 * @return None 153 * @details The ADC controller supports a double buffer mode in sample module 0~3. 154 * If user enable DBMEN (EADC_SCTLn[23], n=0~3), the double buffer mode will enable. 155 * \hideinitializer 156 */ 157 #define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk) 158 159 /** 160 * @brief Disable double buffer mode. 161 * @param[in] eadc The pointer of the specified EADC module. 162 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3. 163 * @return None 164 * @details Sample has one sample result register. 165 * \hideinitializer 166 */ 167 #define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk) 168 169 /** 170 * @brief Set ADIFn at A/D end of conversion. 171 * @param[in] eadc The pointer of the specified EADC module. 172 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. 173 * @return None 174 * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the start of conversion. 175 * \hideinitializer 176 */ 177 #define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk) 178 179 /** 180 * @brief Set ADIFn at A/D start of conversion. 181 * @param[in] eadc The pointer of the specified EADC module. 182 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. 183 * @return None 184 * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the end of conversion. 185 * \hideinitializer 186 */ 187 #define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk) 188 189 /** 190 * @brief Enable the interrupt. 191 * @param[in] eadc The pointer of the specified EADC module. 192 * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. 193 * This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. 194 * @return None 195 * @details The A/D converter generates a conversion end ADIFn (EADC_STATUS2[n]) upon the end of specific sample module A/D conversion. 196 * If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3). 197 * \hideinitializer 198 */ 199 #define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos)) 200 201 /** 202 * @brief Disable the interrupt. 203 * @param[in] eadc The pointer of the specified EADC module. 204 * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. 205 * This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. 206 * @return None 207 * @details Specific sample module A/D ADINT0 interrupt function Disabled. 208 * \hideinitializer 209 */ 210 #define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos)) 211 212 /** 213 * @brief Enable the sample module interrupt. 214 * @param[in] eadc The pointer of the specified EADC module. 215 * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. 216 * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. 217 * This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFF. 218 * @return None 219 * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address. 220 * \hideinitializer 221 */ 222 #define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask)) 223 224 /** 225 * @brief Disable the sample module interrupt. 226 * @param[in] eadc The pointer of the specified EADC module. 227 * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. 228 * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. 229 * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. 230 * @return None 231 * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address. 232 * \hideinitializer 233 */ 234 #define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= ~(u32ModuleMask)) 235 236 /** 237 * @brief Set the input mode output format. 238 * @param[in] eadc The pointer of the specified EADC module. 239 * @param[in] u32Format Decides the output format. Valid values are: 240 * - EADC_CTL_DMOF_STRAIGHT_BINARY :Select the straight binary format as the output format of the conversion result. 241 * - EADC_CTL_DMOF_TWOS_COMPLEMENT :Select the 2's complement format as the output format of the conversion result. 242 * @return None 243 * @details The macro is used to set A/D input mode output format. 244 * \hideinitializer 245 */ 246 #define EADC_SET_DMOF(eadc, u32Format) ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format)) 247 248 /** 249 * @brief Start the A/D conversion. 250 * @param[in] eadc The pointer of the specified EADC module. 251 * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module. 252 * This parameter decides which sample module will be conversion, valid range are between 1~0x7FFFF. 253 * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18. 254 * @return None 255 * @details After write EADC_SWTRG register to start ADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion. 256 * \hideinitializer 257 */ 258 #define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask)) 259 260 /** 261 * @brief Cancel the conversion for sample module. 262 * @param[in] eadc The pointer of the specified EADC module. 263 * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module. 264 * This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFF. 265 * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module18. 266 * @return None 267 * @details If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. 268 * \hideinitializer 269 */ 270 #define EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask)) 271 272 /** 273 * @brief Get the conversion pending flag. 274 * @param[in] eadc The pointer of the specified EADC module. 275 * @return Return the conversion pending sample module. 276 * @details This STPFn(EADC_PENDSTS[18:0]) bit remains 1 during pending state, when the respective ADC conversion is end, 277 * the STPFn (n=0~18) bit is automatically cleared to 0. 278 * \hideinitializer 279 */ 280 #define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS) 281 282 /** 283 * @brief Get the conversion data of the user-specified sample module. 284 * @param[in] eadc The pointer of the specified EADC module. 285 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. 286 * @return Return the conversion data of the user-specified sample module. 287 * @details This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data. 288 * \hideinitializer 289 */ 290 #define EADC_GET_CONV_DATA(eadc, u32ModuleNum) ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk) 291 292 /** 293 * @brief Get the data overrun flag of the user-specified sample module. 294 * @param[in] eadc The pointer of the specified EADC module. 295 * @param[in] u32ModuleMask The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF. 296 * @return Return the data overrun flag of the user-specified sample module. 297 * @details This macro is used to read OV bit (EADC_STATUS0[31:16], EADC_STATUS1[18:16]) field to get data overrun status. 298 * \hideinitializer 299 */ 300 #define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask)) 301 302 /** 303 * @brief Get the data valid flag of the user-specified sample module. 304 * @param[in] eadc The pointer of the specified EADC module. 305 * @param[in] u32ModuleMask The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF. 306 * @return Return the data valid flag of the user-specified sample module. 307 * @details This macro is used to read VALID bit (EADC_STATUS0[15:0], EADC_STATUS1[2:0]) field to get data valid status. 308 * \hideinitializer 309 */ 310 #define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask)) 311 312 /** 313 * @brief Get the double data of the user-specified sample module. 314 * @param[in] eadc The pointer of the specified EADC module. 315 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. 316 * @return Return the double data of the user-specified sample module. 317 * @details This macro is used to read RESULT bit (EADC_DDATn[15:0], n=0~3) field to get conversion data. 318 * \hideinitializer 319 */ 320 #define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT0_RESULT_Msk) 321 322 /** 323 * @brief Get the user-specified interrupt flags. 324 * @param[in] eadc The pointer of the specified EADC module. 325 * @param[in] u32Mask The combination of interrupt status bits. Each bit corresponds to a interrupt status. 326 * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. 327 * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. 328 * @return Return the user-specified interrupt flags. 329 * @details This macro is used to get the user-specified interrupt flags. 330 * \hideinitializer 331 */ 332 #define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask)) 333 334 /** 335 * @brief Get the user-specified sample module overrun flags. 336 * @param[in] eadc The pointer of the specified EADC module. 337 * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFF. 338 * @return Return the user-specified sample module overrun flags. 339 * @details This macro is used to get the user-specified sample module overrun flags. 340 * \hideinitializer 341 */ 342 #define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask)) 343 344 /** 345 * @brief Clear the selected interrupt status bits. 346 * @param[in] eadc The pointer of the specified EADC module. 347 * @param[in] u32Mask The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status. 348 * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. 349 * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. 350 * @return None 351 * @details This macro is used to clear clear the selected interrupt status bits. 352 * \hideinitializer 353 */ 354 #define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask)) 355 356 /** 357 * @brief Clear the selected sample module overrun status bits. 358 * @param[in] eadc The pointer of the specified EADC module. 359 * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status. 360 * Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 18 is SPOVF18. 361 * @return None 362 * @details This macro is used to clear the selected sample module overrun status bits. 363 * \hideinitializer 364 */ 365 #define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask)) 366 367 /** 368 * @brief Check all sample module A/D result data register overrun flags. 369 * @param[in] eadc The pointer of the specified EADC module. 370 * @retval 0 None of sample module data register overrun flag is set to 1. 371 * @retval 1 Any one of sample module data register overrun flag is set to 1. 372 * @details The AOV bit (EADC_STATUS2[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. 373 * \hideinitializer 374 */ 375 #define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos) 376 377 /** 378 * @brief Check all sample module A/D result data register valid flags. 379 * @param[in] eadc The pointer of the specified EADC module. 380 * @retval 0 None of sample module data register valid flag is set to 1. 381 * @retval 1 Any one of sample module data register valid flag is set to 1. 382 * @details The AVALID bit (EADC_STATUS2[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. 383 * \hideinitializer 384 */ 385 #define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos) 386 387 /** 388 * @brief Check all A/D sample module start of conversion overrun flags. 389 * @param[in] eadc The pointer of the specified EADC module. 390 * @retval 0 None of sample module event overrun flag is set to 1. 391 * @retval 1 Any one of sample module event overrun flag is set to 1. 392 * @details The STOVF bit (EADC_STATUS2[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. 393 * \hideinitializer 394 */ 395 #define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos) 396 397 /** 398 * @brief Check all A/D interrupt flag overrun bits. 399 * @param[in] eadc The pointer of the specified EADC module. 400 * @retval 0 None of ADINT interrupt flag is overwritten to 1. 401 * @retval 1 Any one of ADINT interrupt flag is overwritten to 1. 402 * @details The ADOVIF bit (EADC_STATUS2[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. 403 * \hideinitializer 404 */ 405 #define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos) 406 407 /** 408 * @brief Get the busy state of EADC. 409 * @param[in] eadc The pointer of the specified EADC module. 410 * @retval 0 Idle state. 411 * @retval 1 Busy state. 412 * @details This macro is used to read BUSY bit (EADC_STATUS2[23]) to get busy state. 413 * \hideinitializer 414 */ 415 #define EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos) 416 417 /** 418 * @brief Configure the comparator 0 and enable it. 419 * @param[in] eadc The pointer of the specified EADC module. 420 * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. 421 * @param[in] u32Condition specifies the compare condition. Valid values are: 422 * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" 423 * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value 424 * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. 425 * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. 426 * @return None 427 * @details For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); 428 * Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or 429 * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. 430 * \hideinitializer 431 */ 432 #define EADC_ENABLE_CMP0(eadc,\ 433 u32ModuleNum,\ 434 u32Condition,\ 435 u16CMPData,\ 436 u32MatchCount) ((eadc)->CMP[0] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ 437 (u32Condition) |\ 438 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ 439 (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ 440 EADC_CMP_ADCMPEN_Msk)) 441 442 /** 443 * @brief Configure the comparator 1 and enable it. 444 * @param[in] eadc The pointer of the specified EADC module. 445 * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. 446 * @param[in] u32Condition specifies the compare condition. Valid values are: 447 * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" 448 * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value 449 * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. 450 * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. 451 * @return None 452 * @details For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); 453 * Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or 454 * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. 455 * \hideinitializer 456 */ 457 #define EADC_ENABLE_CMP1(eadc,\ 458 u32ModuleNum,\ 459 u32Condition,\ 460 u16CMPData,\ 461 u32MatchCount) ((eadc)->CMP[1] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ 462 (u32Condition) |\ 463 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ 464 (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ 465 EADC_CMP_ADCMPEN_Msk)) 466 467 /** 468 * @brief Configure the comparator 2 and enable it. 469 * @param[in] eadc The pointer of the specified EADC module. 470 * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. 471 * @param[in] u32Condition specifies the compare condition. Valid values are: 472 * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" 473 * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value 474 * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. 475 * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. 476 * @return None 477 * @details For example, ADC_ENABLE_CMP2(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); 478 * Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or 479 * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. 480 * \hideinitializer 481 */ 482 #define EADC_ENABLE_CMP2(eadc,\ 483 u32ModuleNum,\ 484 u32Condition,\ 485 u16CMPData,\ 486 u32MatchCount) ((eadc)->CMP[2] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ 487 (u32Condition) |\ 488 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ 489 (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ 490 EADC_CMP_ADCMPEN_Msk)) 491 492 /** 493 * @brief Configure the comparator 3 and enable it. 494 * @param[in] eadc The pointer of the specified EADC module. 495 * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. 496 * @param[in] u32Condition specifies the compare condition. Valid values are: 497 * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" 498 * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value 499 * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. 500 * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF. 501 * @return None 502 * @details For example, ADC_ENABLE_CMP3(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); 503 * Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or 504 * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. 505 * \hideinitializer 506 */ 507 #define EADC_ENABLE_CMP3(eadc,\ 508 u32ModuleNum,\ 509 u32Condition,\ 510 u16CMPData,\ 511 u32MatchCount) ((eadc)->CMP[3] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ 512 (u32Condition) |\ 513 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ 514 (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ 515 EADC_CMP_ADCMPEN_Msk)) 516 517 /** 518 * @brief Enable the compare window mode. 519 * @param[in] eadc The pointer of the specified EADC module. 520 * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2. 521 * @return None 522 * @details ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched. 523 * \hideinitializer 524 */ 525 #define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk) 526 527 /** 528 * @brief Disable the compare window mode. 529 * @param[in] eadc The pointer of the specified EADC module. 530 * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2. 531 * @return None 532 * @details ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. 533 * \hideinitializer 534 */ 535 #define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk) 536 537 /** 538 * @brief Enable the compare interrupt. 539 * @param[in] eadc The pointer of the specified EADC module. 540 * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3. 541 * @return None 542 * @details If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) 543 * and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, 544 * if ADCMPIE is set to 1, a compare interrupt request is generated. 545 * \hideinitializer 546 */ 547 #define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk) 548 549 /** 550 * @brief Disable the compare interrupt. 551 * @param[in] eadc The pointer of the specified EADC module. 552 * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3. 553 * @return None 554 * @details This macro is used to disable the compare interrupt. 555 * \hideinitializer 556 */ 557 #define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk) 558 559 /** 560 * @brief Disable comparator 0. 561 * @param[in] eadc The pointer of the specified EADC module. 562 * @return None 563 * @details This macro is used to disable comparator 0. 564 * \hideinitializer 565 */ 566 #define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0) 567 568 /** 569 * @brief Disable comparator 1. 570 * @param[in] eadc The pointer of the specified EADC module. 571 * @return None 572 * @details This macro is used to disable comparator 1. 573 * \hideinitializer 574 */ 575 #define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0) 576 577 /** 578 * @brief Disable comparator 2. 579 * @param[in] eadc The pointer of the specified EADC module. 580 * @return None 581 * @details This macro is used to disable comparator 2. 582 * \hideinitializer 583 */ 584 #define EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] = 0) 585 586 /** 587 * @brief Disable comparator 3. 588 * @param[in] eadc The pointer of the specified EADC module. 589 * @return None 590 * @details This macro is used to disable comparator 3. 591 * \hideinitializer 592 */ 593 #define EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] = 0) 594 595 /*---------------------------------------------------------------------------------------------------------*/ 596 /* Define EADC functions prototype */ 597 /*---------------------------------------------------------------------------------------------------------*/ 598 void EADC_Open(EADC_T *eadc, uint32_t u32InputMode); 599 void EADC_Close(EADC_T *eadc); 600 void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSrc, uint32_t u32Channel); 601 void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider); 602 void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime); 603 604 /*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */ 605 606 /*@}*/ /* end of group EADC_Driver */ 607 608 /*@}*/ /* end of group Standard_Driver */ 609 610 #ifdef __cplusplus 611 } 612 #endif 613 614 #endif /* __EADC_H__ */ 615 616 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ 617
