1 /**************************************************************************//** 2 * @file bpwm.h 3 * @version V1.00 4 * @brief M480 series PWM driver header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __BPWM_H__ 10 #define __BPWM_H__ 11 12 #ifdef __cplusplus 13 extern "C" 14 { 15 #endif 16 17 18 /** @addtogroup Standard_Driver Standard Driver 19 @{ 20 */ 21 22 /** @addtogroup BPWM_Driver BPWM Driver 23 @{ 24 */ 25 26 /** @addtogroup BPWM_EXPORTED_CONSTANTS BPWM Exported Constants 27 @{ 28 */ 29 #define BPWM_CHANNEL_NUM (6) /*!< BPWM channel number \hideinitializer */ 30 #define BPWM_CH_0_MASK (0x1UL) /*!< BPWM channel 0 mask \hideinitializer */ 31 #define BPWM_CH_1_MASK (0x2UL) /*!< BPWM channel 1 mask \hideinitializer */ 32 #define BPWM_CH_2_MASK (0x4UL) /*!< BPWM channel 2 mask \hideinitializer */ 33 #define BPWM_CH_3_MASK (0x8UL) /*!< BPWM channel 3 mask \hideinitializer */ 34 #define BPWM_CH_4_MASK (0x10UL) /*!< BPWM channel 4 mask \hideinitializer */ 35 #define BPWM_CH_5_MASK (0x20UL) /*!< BPWM channel 5 mask \hideinitializer */ 36 37 /*---------------------------------------------------------------------------------------------------------*/ 38 /* Counter Type Constant Definitions */ 39 /*---------------------------------------------------------------------------------------------------------*/ 40 #define BPWM_UP_COUNTER (0UL) /*!< Up counter type \hideinitializer */ 41 #define BPWM_DOWN_COUNTER (1UL) /*!< Down counter type \hideinitializer */ 42 #define BPWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type \hideinitializer */ 43 44 /*---------------------------------------------------------------------------------------------------------*/ 45 /* Aligned Type Constant Definitions */ 46 /*---------------------------------------------------------------------------------------------------------*/ 47 #define BPWM_EDGE_ALIGNED (1UL) /*!< BPWM working in edge aligned type(down count) \hideinitializer */ 48 #define BPWM_CENTER_ALIGNED (2UL) /*!< BPWM working in center aligned type \hideinitializer */ 49 50 /*---------------------------------------------------------------------------------------------------------*/ 51 /* Output Level Constant Definitions */ 52 /*---------------------------------------------------------------------------------------------------------*/ 53 #define BPWM_OUTPUT_NOTHING (0UL) /*!< BPWM output nothing \hideinitializer */ 54 #define BPWM_OUTPUT_LOW (1UL) /*!< BPWM output low \hideinitializer */ 55 #define BPWM_OUTPUT_HIGH (2UL) /*!< BPWM output high \hideinitializer */ 56 #define BPWM_OUTPUT_TOGGLE (3UL) /*!< BPWM output toggle \hideinitializer */ 57 58 /*---------------------------------------------------------------------------------------------------------*/ 59 /* Synchronous Start Function Control Constant Definitions */ 60 /*---------------------------------------------------------------------------------------------------------*/ 61 #define BPWM_SSCTL_SSRC_PWM0 (0UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from PWM0 */ 62 #define BPWM_SSCTL_SSRC_PWM1 (1UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from PWM1 */ 63 #define BPWM_SSCTL_SSRC_BPWM0 (2UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM0 */ 64 #define BPWM_SSCTL_SSRC_BPWM1 (3UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM1 */ 65 66 /*---------------------------------------------------------------------------------------------------------*/ 67 /* Trigger Source Select Constant Definitions */ 68 /*---------------------------------------------------------------------------------------------------------*/ 69 #define BPWM_TRIGGER_ADC_EVEN_ZERO_POINT (0UL) /*!< BPWM trigger ADC while counter of even channel matches zero point \hideinitializer */ 70 #define BPWM_TRIGGER_ADC_EVEN_PERIOD_POINT (1UL) /*!< BPWM trigger ADC while counter of even channel matches period point \hideinitializer */ 71 #define BPWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT (2UL) /*!< BPWM trigger ADC while counter of even channel matches zero or period point \hideinitializer */ 72 #define BPWM_TRIGGER_ADC_EVEN_CMP_UP_COUNT_POINT (3UL) /*!< BPWM trigger ADC while counter of even channel matches up count to comparator point \hideinitializer */ 73 #define BPWM_TRIGGER_ADC_EVEN_CMP_DOWN_COUNT_POINT (4UL) /*!< BPWM trigger ADC while counter of even channel matches down count to comparator point \hideinitializer */ 74 #define BPWM_TRIGGER_ADC_ODD_CMP_UP_COUNT_POINT (8UL) /*!< BPWM trigger ADC while counter of odd channel matches up count to comparator point \hideinitializer */ 75 #define BPWM_TRIGGER_ADC_ODD_CMP_DOWN_COUNT_POINT (9UL) /*!< BPWM trigger ADC while counter of odd channel matches down count to comparator point \hideinitializer */ 76 77 /*---------------------------------------------------------------------------------------------------------*/ 78 /* Capture Control Constant Definitions */ 79 /*---------------------------------------------------------------------------------------------------------*/ 80 #define BPWM_CAPTURE_INT_RISING_LATCH (1UL) /*!< BPWM capture interrupt if channel has rising transition \hideinitializer */ 81 #define BPWM_CAPTURE_INT_FALLING_LATCH (0x100UL) /*!< BPWM capture interrupt if channel has falling transition \hideinitializer */ 82 83 /*---------------------------------------------------------------------------------------------------------*/ 84 /* Duty Interrupt Type Constant Definitions */ 85 /*---------------------------------------------------------------------------------------------------------*/ 86 #define BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP (1 << BPWM_INTEN_CMPDIENn_Pos) /*!< BPWM duty interrupt triggered if down count match comparator \hideinitializer */ 87 #define BPWM_DUTY_INT_UP_COUNT_MATCH_CMP (1 << BPWM_INTEN_CMPUIENn_Pos) /*!< BPWM duty interrupt triggered if up down match comparator \hideinitializer */ 88 89 /*---------------------------------------------------------------------------------------------------------*/ 90 /* Load Mode Constant Definitions */ 91 /*---------------------------------------------------------------------------------------------------------*/ 92 #define BPWM_LOAD_MODE_IMMEDIATE (1 << BPWM_CTL0_IMMLDENn_Pos) /*!< BPWM immediately load mode \hideinitializer */ 93 #define BPWM_LOAD_MODE_CENTER (1 << BPWM_CTL0_CTRLDn_Pos) /*!< BPWM center load mode \hideinitializer */ 94 95 /*---------------------------------------------------------------------------------------------------------*/ 96 /* Clock Source Select Constant Definitions */ 97 /*---------------------------------------------------------------------------------------------------------*/ 98 #define BPWM_CLKSRC_BPWM_CLK (0UL) /*!< BPWM Clock source selects to BPWM0_CLK or BPWM1_CLK \hideinitializer */ 99 #define BPWM_CLKSRC_TIMER0 (1UL) /*!< BPWM Clock source selects to TIMER0 overflow \hideinitializer */ 100 #define BPWM_CLKSRC_TIMER1 (2UL) /*!< BPWM Clock source selects to TIMER1 overflow \hideinitializer */ 101 #define BPWM_CLKSRC_TIMER2 (3UL) /*!< BPWM Clock source selects to TIMER2 overflow \hideinitializer */ 102 #define BPWM_CLKSRC_TIMER3 (4UL) /*!< BPWM Clock source selects to TIMER3 overflow \hideinitializer */ 103 104 /*@}*/ /* end of group BPWM_EXPORTED_CONSTANTS */ 105 106 107 /** @addtogroup BPWM_EXPORTED_FUNCTIONS BPWM Exported Functions 108 @{ 109 */ 110 111 /** 112 * @brief Enable timer synchronous start counting function of specified channel(s) 113 * @param[in] bpwm The pointer of the specified BPWM module 114 * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. 115 * @param[in] u32SyncSrc Synchronous start source selection, valid values are: 116 * - \ref BPWM_SSCTL_SSRC_PWM0 117 * - \ref BPWM_SSCTL_SSRC_PWM1 118 * - \ref BPWM_SSCTL_SSRC_BPWM0 119 * - \ref BPWM_SSCTL_SSRC_BPWM1 120 * @return None 121 * @details This macro is used to enable timer synchronous start counting function of specified channel(s). 122 * @note All channels share channel 0's setting. 123 * \hideinitializer 124 */ 125 #define BPWM_ENABLE_TIMER_SYNC(bpwm, u32ChannelMask, u32SyncSrc) ((bpwm)->SSCTL = ((bpwm)->SSCTL & ~BPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | BPWM_SSCTL_SSEN0_Msk) 126 127 /** 128 * @brief Disable timer synchronous start counting function of specified channel(s) 129 * @param[in] bpwm The pointer of the specified BPWM module 130 * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. 131 * @return None 132 * @details This macro is used to disable timer synchronous start counting function of specified channel(s). 133 * @note All channels share channel 0's setting. 134 * \hideinitializer 135 */ 136 #define BPWM_DISABLE_TIMER_SYNC(bpwm, u32ChannelMask) ((bpwm)->SSCTL &= ~BPWM_SSCTL_SSEN0_Msk) 137 138 /** 139 * @brief This macro enable BPWM counter synchronous start counting function. 140 * @param[in] bpwm The pointer of the specified BPWM module 141 * @return None 142 * @details This macro is used to make selected BPWM0 and BPWM1 channel(s) start counting at the same time. 143 * To configure synchronous start counting channel(s) by BPWM_ENABLE_TIMER_SYNC() and BPWM_DISABLE_TIMER_SYNC(). 144 * \hideinitializer 145 */ 146 #define BPWM_TRIGGER_SYNC_START(bpwm) ((bpwm)->SSTRG = BPWM_SSTRG_CNTSEN_Msk) 147 148 /** 149 * @brief This macro enable output inverter of specified channel(s) 150 * @param[in] bpwm The pointer of the specified BPWM module 151 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 152 * Bit 0 represents channel 0, bit 1 represents channel 1... 153 * @return None 154 * \hideinitializer 155 */ 156 #define BPWM_ENABLE_OUTPUT_INVERTER(bpwm, u32ChannelMask) ((bpwm)->POLCTL = (u32ChannelMask)) 157 158 /** 159 * @brief This macro get captured rising data 160 * @param[in] bpwm The pointer of the specified BPWM module 161 * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 162 * @return None 163 * \hideinitializer 164 */ 165 #define BPWM_GET_CAPTURE_RISING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].RCAPDAT) 166 167 /** 168 * @brief This macro get captured falling data 169 * @param[in] bpwm The pointer of the specified BPWM module 170 * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 171 * @return None 172 * \hideinitializer 173 */ 174 #define BPWM_GET_CAPTURE_FALLING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].FCAPDAT) 175 176 /** 177 * @brief This macro mask output logic to high or low 178 * @param[in] bpwm The pointer of the specified BPWM module 179 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 180 * Bit 0 represents channel 0, bit 1 represents channel 1... 181 * @param[in] u32LevelMask Output logic to high or low 182 * @return None 183 * @details This macro is used to mask output logic to high or low of specified channel(s). 184 * @note If u32ChannelMask parameter is 0, then mask function will be disabled. 185 * \hideinitializer 186 */ 187 #define BPWM_MASK_OUTPUT(bpwm, u32ChannelMask, u32LevelMask) \ 188 { \ 189 (bpwm)->MSKEN = (u32ChannelMask); \ 190 (bpwm)->MSK = (u32LevelMask); \ 191 } 192 193 /** 194 * @brief This macro set the prescaler of all channels 195 * @param[in] bpwm The pointer of the specified BPWM module 196 * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. 197 * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFFF 198 * @return None 199 * \hideinitializer 200 */ 201 #define BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescaler) ((bpwm)->CLKPSC = (u32Prescaler)) 202 203 /** 204 * @brief This macro set the duty of the selected channel 205 * @param[in] bpwm The pointer of the specified BPWM module 206 * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 207 * @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF 208 * @return None 209 * @note This new setting will take effect on next BPWM period 210 * \hideinitializer 211 */ 212 #define BPWM_SET_CMR(bpwm, u32ChannelNum, u32CMR) ((bpwm)->CMPDAT[(u32ChannelNum)] = (u32CMR)) 213 214 /** 215 * @brief This macro get the duty of the selected channel 216 * @param[in] bpwm The pointer of the specified BPWM module 217 * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 218 * @return None 219 * \hideinitializer 220 */ 221 #define BPWM_GET_CMR(bpwm, u32ChannelNum) ((bpwm)->CMPDAT[(u32ChannelNum)]) 222 223 /** 224 * @brief This macro set the period of all channels 225 * @param[in] bpwm The pointer of the specified BPWM module 226 * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. 227 * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF 228 * @return None 229 * @note This new setting will take effect on next BPWM period 230 * @note BPWM counter will stop if period length set to 0 231 * \hideinitializer 232 */ 233 #define BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR) ((bpwm)->PERIOD = (u32CNR)) 234 235 /** 236 * @brief This macro get the period of all channels 237 * @param[in] bpwm The pointer of the specified BPWM module 238 * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. 239 * @return None 240 * \hideinitializer 241 */ 242 #define BPWM_GET_CNR(bpwm, u32ChannelNum) ((bpwm)->PERIOD) 243 244 /** 245 * @brief This macro set the BPWM aligned type 246 * @param[in] bpwm The pointer of the specified BPWM module 247 * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. 248 * @param[in] u32AlignedType BPWM aligned type, valid values are: 249 * - \ref BPWM_EDGE_ALIGNED 250 * - \ref BPWM_CENTER_ALIGNED 251 * @return None 252 * @note All channels share channel 0's setting. 253 * \hideinitializer 254 */ 255 #define BPWM_SET_ALIGNED_TYPE(bpwm, u32ChannelMask, u32AlignedType) ((bpwm)->CTL1 = (u32AlignedType)) 256 257 /** 258 * @brief Clear counter of channel 0 259 * @param[in] bpwm The pointer of the specified BPWM module 260 * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. 261 * @return None 262 * @details This macro is used to clear counter of channel 0 263 * \hideinitializer 264 */ 265 #define BPWM_CLR_COUNTER(bpwm, u32ChannelMask) ((bpwm)->CNTCLR = (BPWM_CNTCLR_CNTCLR0_Msk)) 266 267 /** 268 * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s) 269 * @param[in] bpwm The pointer of the specified BPWM module 270 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 271 * Bit 0 represents channel 0, bit 1 represents channel 1... 272 * @param[in] u32ZeroLevel output level at zero point, valid values are: 273 * - \ref BPWM_OUTPUT_NOTHING 274 * - \ref BPWM_OUTPUT_LOW 275 * - \ref BPWM_OUTPUT_HIGH 276 * - \ref BPWM_OUTPUT_TOGGLE 277 * @param[in] u32CmpUpLevel output level at compare up point, valid values are: 278 * - \ref BPWM_OUTPUT_NOTHING 279 * - \ref BPWM_OUTPUT_LOW 280 * - \ref BPWM_OUTPUT_HIGH 281 * - \ref BPWM_OUTPUT_TOGGLE 282 * @param[in] u32PeriodLevel output level at period(center) point, valid values are: 283 * - \ref BPWM_OUTPUT_NOTHING 284 * - \ref BPWM_OUTPUT_LOW 285 * - \ref BPWM_OUTPUT_HIGH 286 * - \ref BPWM_OUTPUT_TOGGLE 287 * @param[in] u32CmpDownLevel output level at compare down point, valid values are: 288 * - \ref BPWM_OUTPUT_NOTHING 289 * - \ref BPWM_OUTPUT_LOW 290 * - \ref BPWM_OUTPUT_HIGH 291 * - \ref BPWM_OUTPUT_TOGGLE 292 * @return None 293 * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s) 294 * \hideinitializer 295 */ 296 #define BPWM_SET_OUTPUT_LEVEL(bpwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \ 297 do{ \ 298 int i; \ 299 for(i = 0; i < 6; i++) { \ 300 if((u32ChannelMask) & (1 << i)) { \ 301 (bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (2 * i))) | ((u32ZeroLevel) << (2 * i))); \ 302 (bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (BPWM_WGCTL0_PRDPCTLn_Pos + (2 * i)))) | ((u32PeriodLevel) << (BPWM_WGCTL0_PRDPCTLn_Pos + (2 * i)))); \ 303 (bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (2 * i))) | ((u32CmpUpLevel) << (2 * i))); \ 304 (bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (BPWM_WGCTL1_CMPDCTLn_Pos + (2 * i)))) | ((u32CmpDownLevel) << (BPWM_WGCTL1_CMPDCTLn_Pos + (2 * i)))); \ 305 } \ 306 } \ 307 }while(0) 308 309 310 /*---------------------------------------------------------------------------------------------------------*/ 311 /* Define BPWM functions prototype */ 312 /*---------------------------------------------------------------------------------------------------------*/ 313 uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge); 314 uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle); 315 void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask); 316 void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask); 317 void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask); 318 void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition); 319 void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum); 320 void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition); 321 uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); 322 void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask); 323 void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask); 324 void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask); 325 void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask); 326 void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); 327 void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); 328 void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); 329 uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); 330 void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType); 331 void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum); 332 void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); 333 uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); 334 void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType); 335 void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum); 336 void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); 337 uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); 338 void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum); 339 void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum); 340 void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); 341 uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); 342 void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); 343 void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); 344 void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel); 345 uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); 346 void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); 347 348 349 /*@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */ 350 351 /*@}*/ /* end of group BPWM_Driver */ 352 353 /*@}*/ /* end of group Standard_Driver */ 354 355 #ifdef __cplusplus 356 } 357 #endif 358 359 #endif /* __BPWM_H__ */ 360 361 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ 362
