1 /**************************************************************************//** 2 * @file hsusbh_reg.h 3 * @version V1.00 4 * @brief HSUSBH register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __HSUSBH_REG_H__ 10 #define __HSUSBH_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup HSUSBH High Speed USB Host Controller (HSUSBH) 23 Memory Mapped Structure for HSUSBH Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var HSUSBH_T::EHCVNR 32 * Offset: 0x00 EHCI Version Number Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[7:0] |CRLEN |Capability Registers Length 37 * | | |This register is used as an offset to add to register base to find the beginning of the Operational Register Space. 38 * |[31:16] |VERSION |Host Controller Interface Version Number 39 * | | |This is a two-byte register containing a BCD encoding of the EHCI revision number supported by this host controller 40 * | | |The most significant byte of this register represents a major revision and the least significant byte is the minor revision. 41 * @var HSUSBH_T::EHCSPR 42 * Offset: 0x04 EHCI Structural Parameters Register 43 * --------------------------------------------------------------------------------------------------- 44 * |Bits |Field |Descriptions 45 * | :----: | :----: | :---- | 46 * |[3:0] |N_PORTS |Number of Physical Downstream Ports 47 * | | |This field specifies the number of physical downstream ports implemented on this host controller 48 * | | |The value of this field determines how many port registers are addressable in the Operational Register Space (see Table 2-8) 49 * | | |Valid values are in the range of 1H to FH. 50 * | | |A zero in this field is undefined. 51 * |[4] |PPC |Port Power Control 52 * | | |This field indicates whether the host controller implementation includes port power control 53 * | | |A one in this bit indicates the ports have port power switches 54 * | | |A zero in this bit indicates the port do not have port power stitches 55 * | | |The value of this field affects the functionality of the Port Power field in each port status and control register. 56 * |[11:8] |N_PCC |Number of Ports Per Companion Controller 57 * | | |This field indicates the number of ports supported per companion host controller 58 * | | |It is used to indicate the port routing configuration to system software. 59 * | | |For example, if N_PORTS has a value of 6 and N_CC has a value of 2 then N_PCC could have a value of 3 60 * | | |The convention is that the first N_PCC ports are assumed to be routed to companion controller 1, the next N_PCC ports to companion controller 2, etc 61 * | | |In the previous example, the N_PCC could have been 4, where the first 4 are routed to companion controller 1 and the last two are routed to companion controller 2. 62 * | | |The number in this field must be consistent with N_PORTS and N_CC. 63 * |[15:12] |N_CC |Number of Companion Controller 64 * | | |This field indicates the number of companion controllers associated with this USB 2.0 host controller. 65 * | | |A zero in this field indicates there are no companion host controllers 66 * | | |Port-ownership hand-off is not supported 67 * | | |Only high-speed devices are supported on the host controller root ports. 68 * | | |A value larger than zero in this field indicates there are companion USB 1.1 host controller(s) 69 * | | |Port-ownership hand-offs are supported 70 * | | |High, Full- and Low-speed devices are supported on the host controller root ports. 71 * @var HSUSBH_T::EHCCPR 72 * Offset: 0x08 EHCI Capability Parameters Register 73 * --------------------------------------------------------------------------------------------------- 74 * |Bits |Field |Descriptions 75 * | :----: | :----: | :---- | 76 * |[0] |AC64 |64-bit Addressing Capability 77 * | | |0 = Data structure using 32-bit address memory pointers. 78 * |[1] |PFLF |Programmable Frame List Flag 79 * | | |0 = System software must use a frame list length of 1024 elements with this EHCI host controller. 80 * |[2] |ASPC |Asynchronous Schedule Park Capability 81 * | | |0 = This EHCI host controller doesn't support park feature of high-speed queue heads in the Asynchronous Schedule. 82 * |[7:4] |IST |Isochronous Scheduling Threshold 83 * | | |This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. 84 * | | |When bit [7] is zero, the value of the least significant 3 bits indicates the number of micro-frames a host controller can hold a set of isochronous data structures (one or more) before flushing the state. 85 * |[15:8] |EECP |EHCI Extended Capabilities Pointer (EECP) 86 * | | |0 = No extended capabilities are implemented. 87 * @var HSUSBH_T::UCMDR 88 * Offset: 0x20 USB Command Register 89 * --------------------------------------------------------------------------------------------------- 90 * |Bits |Field |Descriptions 91 * | :----: | :----: | :---- | 92 * |[0] |RUN |Run/Stop (R/W) 93 * | | |When set to a 1, the Host Controller proceeds with execution of the schedule 94 * | | |The Host Controller continues execution as long as this bit is set to a 1 95 * | | |When this bit is set to 0, the Host Controller completes the current and any actively pipelined transactions on the USB and then halts 96 * | | |The Host Controller must halt within 16 micro-frames after software clears the Run bit 97 * | | |The HC Halted bit in the status register indicates when the Host Controller has finished its pending pipelined transactions and has entered the stopped state 98 * | | |Software must not write a one to this field unless the host controller is in the Halted state (i.e. 99 * | | |HCHalted in the USBSTS register is a one) 100 * | | |Doing so will yield undefined results. 101 * | | |0 = Stop. 102 * | | |1 = Run. 103 * |[1] |HCRST |Host Controller Reset (HCRESET) (R/W) 104 * | | |This control bit is used by software to reset the host controller 105 * | | |The effects of this on Root Hub registers are similar to a Chip Hardware Reset. 106 * | | |When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines, etc 107 * | | |to their initial value 108 * | | |Any transaction currently in progress on USB is immediately terminated 109 * | | |A USB reset is not driven on downstream ports. 110 * | | |All operational registers, including port registers and port state machines are set to their initial values 111 * | | |Port ownership reverts to the companion host controller(s), with the side effects 112 * | | |Software must reinitialize the host controller in order to return the host controller to an operational state. 113 * | | |This bit is set to zero by the Host Controller when the reset process is complete 114 * | | |Software cannot terminate the reset process early by writing a zero to this register. 115 * | | |Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero 116 * | | |Attempting to reset an actively running host controller will result in undefined behavior. 117 * |[3:2] |FLSZ |Frame List Size (R/W or RO) 118 * | | |This field is R/W only if Programmable Frame List Flag in the HCCPARAMS registers is set to a one 119 * | | |This field specifies the size of the frame list 120 * | | |The size the frame list controls which bits in the Frame Index Register should be used for the Frame List Current index 121 * | | |Values mean: 122 * | | |00 = 1024 elements (4096 bytes) Default value. 123 * | | |01 = 512 elements (2048 bytes). 124 * | | |10 = 256 elements (1024 bytes) u2013 for resource-constrained environment. 125 * | | |11 = Reserved. 126 * |[4] |PSEN |Periodic Schedule Enable (R/W) 127 * | | |This bit controls whether the host controller skips processing the Periodic Schedule. Values mean: 128 * | | |0 = Do not process the Periodic Schedule. 129 * | | |1 = Use the PERIODICLISTBASE register to access the Periodic Schedule. 130 * |[5] |ASEN |Asynchronous Schedule Enable (R/W) 131 * | | |This bit controls whether the host controller skips processing the Asynchronous Schedule. Values mean: 132 * | | |0 = Do not process the Asynchronous Schedule. 133 * | | |1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule. 134 * |[6] |IAAD |Interrupt on Asynchronous Advance Doorbell (R/W) 135 * | | |This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule 136 * | | |Software must write a 1 to this bit to ring the doorbell. 137 * | | |When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Asynchronous Advance status bit in the USBSTS register 138 * | | |If the Interrupt on Asynchronous Advance Enable bit in the USBINTR register is a one then the host controller will assert an interrupt at the next interrupt threshold. 139 * | | |The host controller sets this bit to a zero after it has set the Interrupt on Asynchronous Advance status bit in the USBSTS register to a one. 140 * | | |Software should not write a one to this bit when the asynchronous schedule is disabled 141 * | | |Doing so will yield undefined results. 142 * |[23:16] |ITC |Interrupt Threshold Control (R/W) 143 * | | |This field is used by system software to select the maximum rate at which the host controller will issue interrupts 144 * | | |The only valid values are defined below 145 * | | |If software writes an invalid value to this register, the results are undefined 146 * | | |Value Maximum Interrupt Interval 147 * | | |0x00 = Reserved. 148 * | | |0x01 = 1 micro-frame. 149 * | | |0x02 = 2 micro-frames. 150 * | | |0x04 = 4 micro-frames. 151 * | | |0x08 = 8 micro-frames (default, equates to 1 ms). 152 * | | |0x10 = 16 micro-frames (2 ms). 153 * | | |0x20 = 32 micro-frames (4 ms). 154 * | | |0x40 = 64 micro-frames (8 ms). 155 * | | |Any other value in this register yields undefined results. 156 * | | |Software modifications to this bit while HCHalted bit is equal to zero results in undefined behavior. 157 * @var HSUSBH_T::USTSR 158 * Offset: 0x24 USB Status Register 159 * --------------------------------------------------------------------------------------------------- 160 * |Bits |Field |Descriptions 161 * | :----: | :----: | :---- | 162 * |[0] |USBINT |USB Interrupt (USBINT) (R/WC) 163 * | | |The Host Controller sets this bit to 1 on the completion of a USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set. 164 * | | |The Host Controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes). 165 * |[1] |UERRINT |USB Error Interrupt (USBERRINT) (R/WC) 166 * | | |The Host Controller sets this bit to 1 when completion of a USB transaction results in an error condition (e.g., error counter underflow) 167 * | | |If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and USBINT bit are set. 168 * |[2] |PCD |Port Change Detect (R/WC) 169 * | | |The Host Controller sets this bit to a one when any port for which the Port Owner bit is set to zero has a change bit transition from a zero to a one or a Force Port Resume bit transition from a zero to a one as a result of a J-K transition detected on a suspended port 170 * | | |This bit will also be set as a result of the Connect Status Change being set to a one after system software has relinquished ownership of a connected port by writing a one to a port's Port Owner bit. 171 * | | |This bit is allowed to be maintained in the Auxiliary power well 172 * | | |Alternatively, it is also acceptable that on a D3 to D0 transition of the EHCI HC device, this bit is loaded with the OR of all of the PORTSC change bits (including: Force port resume, over-current change, enable/disable change and connect status change). 173 * |[3] |FLR |Frame List Rollover (R/WC) 174 * | | |The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero 175 * | | |The exact value at which the rollover occurs depends on the frame list size 176 * | | |For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX[13] toggles 177 * | | |Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX[12] toggles. 178 * |[4] |HSERR |Host System Error (R/WC) 179 * | | |The Host Controller sets this bit to 1 when a serious error occurs during a host system access involving the Host Controller module. 180 * |[5] |IAA |Interrupt on Asynchronous Advance (R/WC) 181 * | | |System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Asynchronous Advance Doorbell bit in the USBCMD register 182 * | | |This status bit indicates the assertion of that interrupt source. 183 * |[12] |HCHalted |HCHalted (RO) 184 * | | |This bit is a zero whenever the Run/Stop bit is a one 185 * | | |The Host Controller sets this bit to one after it has stopped executing as a result of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. 186 * | | |internal error). 187 * |[13] |RECLA |Reclamation (RO) 188 * | | |This is a read-only status bit, which is used to detect an empty asynchronous schedule. 189 * |[14] |PSS |Periodic Schedule Status (RO) 190 * | | |The bit reports the current real status of the Periodic Schedule 191 * | | |If this bit is a zero then the status of the Periodic Schedule is disabled 192 * | | |If this bit is a one then the status of the Periodic Schedule is enabled 193 * | | |The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register 194 * | | |When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). 195 * |[15] |ASS |Asynchronous Schedule Status (RO) 196 * | | |The bit reports the current real status of the Asynchronous Schedule 197 * | | |If this bit is a zero then the status of them Asynchronous Schedule is disabled 198 * | | |If this bit is a one then the status of the Asynchronous Schedule is enabled 199 * | | |The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register 200 * | | |When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). 201 * @var HSUSBH_T::UIENR 202 * Offset: 0x28 USB Interrupt Enable Register 203 * --------------------------------------------------------------------------------------------------- 204 * |Bits |Field |Descriptions 205 * | :----: | :----: | :---- | 206 * |[0] |USBIEN |USB Interrupt Enable or Disable Bit 207 * | | |When this bit is a one, and the USBINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold 208 * | | |The interrupt is acknowledged by software clearing the USBINT bit. 209 * | | |0 = USB interrupt Disabled. 210 * | | |1 = USB interrupt Enabled. 211 * |[1] |UERRIEN |USB Error Interrupt Enable or Disable Bit 212 * | | |When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host t controller will issue an interrupt at the next interrupt threshold 213 * | | |The interrupt is acknowledged by software clearing the USBERRINT bit. 214 * | | |0 = USB Error interrupt Disabled. 215 * | | |1 = USB Error interrupt Enabled. 216 * |[2] |PCIEN |Port Change Interrupt Enable or Disable Bit 217 * | | |When this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host controller will issue an interrupt 218 * | | |The interrupt is acknowledged by software clearing the Port Change Detect bit. 219 * | | |0 = Port Change interrupt Disabled. 220 * | | |1 = Port Change interrupt Enabled. 221 * |[3] |FLREN |Frame List Rollover Enable or Disable Bit 222 * | | |When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt 223 * | | |The interrupt is acknowledged by software clearing the Frame List Rollover bit. 224 * | | |0 = Frame List Rollover interrupt Disabled. 225 * | | |1 = Frame List Rollover interrupt Enabled. 226 * |[4] |HSERREN |Host System Error Enable or Disable Bit 227 * | | |When this bit is a one, and the Host System Error Status bit in the USBSTS register is a one, the host controller will issue an interrupt 228 * | | |The interrupt is acknowledged by software clearing the Host System Error bit. 229 * | | |0 = Host System Error interrupt Disabled. 230 * | | |1 = Host System Error interrupt Enabled. 231 * |[5] |IAAEN |Interrupt on Asynchronous Advance Enable or Disable Bit 232 * | | |When this bit is a one, and the Interrupt on Asynchronous Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold 233 * | | |The interrupt is acknowledged by software clearing the Interrupt on Asynchronous Advance bit. 234 * | | |0 = Interrupt on Asynchronous Advance Disabled. 235 * | | |1 = Interrupt on Asynchronous Advance Enabled. 236 * @var HSUSBH_T::UFINDR 237 * Offset: 0x2C USB Frame Index Register 238 * --------------------------------------------------------------------------------------------------- 239 * |Bits |Field |Descriptions 240 * | :----: | :----: | :---- | 241 * |[13:0] |FI |Frame Index 242 * | | |The value in this register increment at the end of each time frame (e.g. 243 * | | |micro-frame) 244 * | | |Bits [N:3] are used for the Frame List current index 245 * | | |This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index 246 * | | |The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register. 247 * | | |FLSZ (UCMDR[3:2] Number Elements N 248 * | | |0x0 1024 12 249 * | | |0x1 512 11 250 * | | |0x2 256 10 251 * | | |0x3 Reserved 252 * @var HSUSBH_T::UPFLBAR 253 * Offset: 0x34 USB Periodic Frame List Base Address Register 254 * --------------------------------------------------------------------------------------------------- 255 * |Bits |Field |Descriptions 256 * | :----: | :----: | :---- | 257 * |[31:12] |BADDR |Base Address 258 * | | |These bits correspond to memory address signals [31:12], respectively. 259 * @var HSUSBH_T::UCALAR 260 * Offset: 0x38 USB Current Asynchronous List Address Register 261 * --------------------------------------------------------------------------------------------------- 262 * |Bits |Field |Descriptions 263 * | :----: | :----: | :---- | 264 * |[31:5] |LPL |Link Pointer Low (LPL) 265 * | | |These bits correspond to memory address signals [31:5], respectively 266 * | | |This field may only reference a Queue Head (QH). 267 * @var HSUSBH_T::UASSTR 268 * Offset: 0x3C USB Asynchronous Schedule Sleep Timer Register 269 * --------------------------------------------------------------------------------------------------- 270 * |Bits |Field |Descriptions 271 * | :----: | :----: | :---- | 272 * |[11:0] |ASSTMR |Asynchronous Schedule Sleep Timer 273 * | | |This field defines the AsyncSchedSleepTime of EHCI spec. 274 * | | |The asynchronous schedule sleep timer is used to control how often the host controller fetches asynchronous schedule list from system memory while the asynchronous schedule is empty. 275 * | | |The default value of this timer is 12'hBD6 276 * | | |Because this timer is implemented in UTMI clock (30MHz) domain, the default sleeping time will be about 100us. 277 * @var HSUSBH_T::UCFGR 278 * Offset: 0x60 USB Configure Flag Register 279 * --------------------------------------------------------------------------------------------------- 280 * |Bits |Field |Descriptions 281 * | :----: | :----: | :---- | 282 * |[0] |CF |Configure Flag (CF) 283 * | | |Host software sets this bit as the last action in its process of configuring the Host Controller 284 * | | |This bit controls the default port-routing control logic 285 * | | |Bit values and side-effects are listed below. 286 * | | |0 = Port routing control logic default-routes each port to an implementation dependent classic host controller. 287 * | | |1 = Port routing control logic default-routes all ports to this host controller. 288 * @var HSUSBH_T::UPSCR[2] 289 * Offset: 0x64~0x68 USB Port 0~1 Status and Control Register 290 * --------------------------------------------------------------------------------------------------- 291 * |Bits |Field |Descriptions 292 * | :----: | :----: | :---- | 293 * |[0] |CCS |Current Connect Status (RO) 294 * | | |This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. 295 * | | |This field is zero if Port Power is zero. 296 * | | |0 = No device is present. 297 * | | |1 = Device is present on port. 298 * |[1] |CSC |Connect Status Change (R/W) 299 * | | |Indicates a change has occurred in the port's Current Connect Status 300 * | | |The host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change 301 * | | |For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be "setting" an already-set bit (i.e., the bit will remain set).Software sets this bit to 0 by writing a 1 to it. 302 * | | |This field is zero if Port Power is zero. 303 * | | |0 = No change. 304 * | | |1 = Change in Current Connect Status. 305 * |[2] |PE |Port Enabled/Disabled (R/W) 306 * | | |Ports can only be enabled by the host controller as a part of the reset and enable 307 * | | |Software cannot enable a port by writing a one to this field 308 * | | |The host controller will only set this bit to a one when the reset sequence determines that the attached device is a high-speed device. 309 * | | |Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software 310 * | | |Note that the bit status does not change until the port state actually changes 311 * | | |There may be a delay in disabling or enabling a port due to other host controller and bus events. 312 * | | |When the port is disabled (0b) downstream propagation of data is blocked on this port, except for reset. 313 * | | |This field is zero if Port Power is zero. 314 * | | |0 = Port Disabled. 315 * | | |1 = Port Enabled. 316 * |[3] |PEC |Port Enable/Disable Change (R/WC) 317 * | | |For the root hub, this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification for the definition of a Port Error) 318 * | | |Software clears this bit by writing a 1 to it. 319 * | | |This field is zero if Port Power is zero. 320 * | | |0 = No change. 321 * | | |1 = Port enabled/disabled status has changed. 322 * |[4] |OCA |Over-current Active (RO) 323 * | | |This bit will automatically transition from a one to a zero when the over current condition is removed. 324 * | | |0 = This port does not have an over-current condition. 325 * | | |1 = This port currently has an over-current condition. 326 * |[5] |OCC |Over-current Change (R/WC) 327 * | | |1 = This bit gets set to a one when there is a change to Over-current Active 328 * | | |Software clears this bit by writing a one to this bit position. 329 * |[6] |FPR |Force Port Resume (R/W) 330 * | | |This functionality defined for manipulating this bit depends on the value of the Suspend bit 331 * | | |For example, if the port is not suspended (Suspend and Enabled bits are a one) and software transitions this bit to a one, then the effects on the bus are undefined. 332 * | | |Software sets this bit to a 1 to drive resume signaling 333 * | | |The Host Controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state 334 * | | |When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to a one 335 * | | |If software sets this bit to a one, the host controller must not set the Port Change Detect bit. 336 * | | |Note that when the EHCI controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0 337 * | | |The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one 338 * | | |Software must appropriately time the Resume and set this bit to a zero when the appropriate amount of time has elapsed 339 * | | |Writing a zero (from one) causes the port to return to high-speed mode (forcing the bus below the port into a high-speed idle) 340 * | | |This bit will remain a one until the port has switched to the high-speed idle 341 * | | |The host controller must complete this transition within 2 milliseconds of software setting this bit to a zero. 342 * | | |This field is zero if Port Power is zero. 343 * | | |0 = No resume (K-state) detected/driven on port. 344 * | | |1 = Resume detected/driven on port. 345 * |[7] |SUSPEND |Suspend (R/W) 346 * | | |Port Enabled Bit and Suspend bit of this register define the port states as follows: 347 * | | |Port enable is 0 and suspend is 0 = Disable. 348 * | | |Port enable is 0 and suspend is 1 = Disable. 349 * | | |Port enable is 1 and suspend is 0 = Enable. 350 * | | |Port enable is 1 and suspend is 1 = Suspend. 351 * | | |When in suspend state, downstream propagation of data is blocked on this port, except for port reset 352 * | | |The blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1 353 * | | |In the suspend state, the port is sensitive to resume detection 354 * | | |Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. 355 * | | |A write of zero to this bit is ignored by the host controller 356 * | | |The host controller will unconditionally set this bit to a zero when: 357 * | | |Software sets the Force Port Resume bit to a zero (from a one). 358 * | | |Software sets the Port Reset bit to a one (from a zero). 359 * | | |If host software sets this bit to a one when the port is not enabled (i.e. 360 * | | |Port enabled bit is a zero) the results are undefined. 361 * | | |This field is zero if Port Power is zero. 362 * | | |0 = Port not in suspend state. 363 * | | |1 = Port in suspend state. 364 * |[8] |PRST |Port Reset (R/W) 365 * | | |When software writes a one to this bit (from a zero), the bus reset sequence as defined in the USB Specification Revision 2.0 is started 366 * | | |Software writes a zero to this bit to terminate the bus reset sequence 367 * | | |Software must keep this bit at a one long enough to ensure the reset sequence, as specified in the USB Specification Revision 2.0, completes 368 * | | |Note: when software writes this bit to a one, it must also write a zero to the Port Enable bit. 369 * | | |Note that when software writes a zero to this bit there may be a delay before the bit status changes to a zero 370 * | | |The bit status will not read as a zero until after the reset has completed 371 * | | |If the port is in high-speed mode after reset is complete, the host controller will automatically enable this port (e.g. 372 * | | |set the Port Enable bit to a one) 373 * | | |A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from a one to a zero 374 * | | |For example: if the port detects that the attached device is high-speed during reset, then the host controller must have the port in the enabled state within 2ms of software writing this bit to a zero. 375 * | | |The HCHalted bit in the USBSTS register should be a zero before software attempts to use this bit 376 * | | |The host controller may hold Port Reset asserted to a one when the HCHalted bit is a one. 377 * | | |This field is zero if Port Power is zero. 378 * | | |0 = Port is not in Reset. 379 * | | |1 = Port is in Reset. 380 * |[11:10] |LSTS |Line Status (RO) 381 * | | |These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines 382 * | | |These bits are used for detection of low-speed USB devices prior to the port reset and enable sequence 383 * | | |This field is valid only when the port enable bit is zero and the current connect status bit is set to a one. 384 * | | |The encoding of the bits are: 385 * | | |Bits[11:10] USB State Interpretation 386 * | | |00 = SE0 Not Low-speed device, perform EHCI reset. 387 * | | |01 = K-state Low-speed device, release ownership of port. 388 * | | |10 = J-state Not Low-speed device, perform EHCI reset. 389 * | | |11 = Undefined Not Low-speed device, perform EHCI reset. 390 * | | |This value of this field is undefined if Port Power is zero. 391 * |[12] |PP |Port Power (PP) 392 * | | |Host controller has port power control switches 393 * | | |This bit represents the Current setting of the switch (0 = off, 1 = on) 394 * | | |When power is not available on a port (i.e. 395 * | | |PP equals a 0), the port is nonfunctional and will not report attaches, detaches, etc. 396 * | | |When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller from a 1 to 0 (removing power from the port). 397 * |[13] |PO |Port Owner (R/W) 398 * | | |This bit unconditionally goes to a 0b when the Configured bit in the CONFIGFLAG register makes a 0 to 1 transition 399 * | | |This bit unconditionally goes to 1 whenever the Configured bit is zero. 400 * | | |System software uses this field to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed device) 401 * | | |Software writes a one to this bit when the attached device is not a high-speed device 402 * | | |A one in this bit means that a companion host controller owns and controls the port. 403 * |[19:16] |PTC |Port Test Control (R/W) 404 * | | |When this field is zero, the port is NOT operating in a test mode 405 * | | |A non-zero value indicates that it is operating in test mode and the specific test mode is indicated by the specific value 406 * | | |The encoding of the test mode bits are (0x6 ~ 0xF are reserved): 407 * | | |Bits Test Mode 408 * | | |0x0 = Test mode not enabled. 409 * | | |0x1 = Test J_STATE. 410 * | | |0x2 = Test K_STATE. 411 * | | |0x3 = Test SE0_NAK. 412 * | | |0x4 = Test Packet. 413 * | | |0x5 = Test FORCE_ENABLE. 414 * @var HSUSBH_T::USBPCR0 415 * Offset: 0xC4 USB PHY 0 Control Register 416 * --------------------------------------------------------------------------------------------------- 417 * |Bits |Field |Descriptions 418 * | :----: | :----: | :---- | 419 * |[8] |SUSPEND |Suspend Assertion 420 * | | |This bit controls the suspend mode of USB PHY 0. 421 * | | |While PHY was suspended, all circuits of PHY were powered down and outputs are tri-state. 422 * | | |This bit is 1'b0 in default 423 * | | |This means the USB PHY 0 is suspended in default 424 * | | |It is necessary to set this bit 1'b1 to make USB PHY 0 leave suspend mode before doing configuration of USB host. 425 * | | |0 = USB PHY 0 was suspended. 426 * | | |1 = USB PHY 0 was not suspended. 427 * |[11] |CLKVALID |UTMI Clock Valid 428 * | | |This bit is a flag to indicate if the UTMI clock from USB 2.0 PHY is ready 429 * | | |S/W program must prevent to write other control registers before this UTMI clock valid flag is active. 430 * | | |0 = UTMI clock is not valid. 431 * | | |1 = UTMI clock is valid. 432 * @var HSUSBH_T::USBPCR1 433 * Offset: 0xC8 USB PHY 1 Control Register 434 * --------------------------------------------------------------------------------------------------- 435 * |Bits |Field |Descriptions 436 * | :----: | :----: | :---- | 437 * |[8] |SUSPEND |Suspend Assertion 438 * | | |This bit controls the suspend mode of USB PHY 1. 439 * | | |While PHY was suspended, all circuits of PHY were powered down and outputs are tri-state. 440 * | | |This bit is 1'b0 in default 441 * | | |This means the USB PHY 0 is suspended in default 442 * | | |It is necessary to set this bit 1'b1 to make USB PHY 0 leave suspend mode before doing configuration of USB host. 443 * | | |0 = USB PHY 1 was suspended. 444 * | | |1 = USB PHY 1 was not suspended. 445 */ 446 __I uint32_t EHCVNR; /*!< [0x0000] EHCI Version Number Register */ 447 __I uint32_t EHCSPR; /*!< [0x0004] EHCI Structural Parameters Register */ 448 __I uint32_t EHCCPR; /*!< [0x0008] EHCI Capability Parameters Register */ 449 /// @cond HIDDEN_SYMBOLS 450 __I uint32_t RESERVE0[5]; 451 /// @endcond //HIDDEN_SYMBOLS 452 __IO uint32_t UCMDR; /*!< [0x0020] USB Command Register */ 453 __IO uint32_t USTSR; /*!< [0x0024] USB Status Register */ 454 __IO uint32_t UIENR; /*!< [0x0028] USB Interrupt Enable Register */ 455 __IO uint32_t UFINDR; /*!< [0x002c] USB Frame Index Register */ 456 /// @cond HIDDEN_SYMBOLS 457 __I uint32_t RESERVE1[1]; 458 /// @endcond //HIDDEN_SYMBOLS 459 __IO uint32_t UPFLBAR; /*!< [0x0034] USB Periodic Frame List Base Address Register */ 460 __IO uint32_t UCALAR; /*!< [0x0038] USB Current Asynchronous List Address Register */ 461 __IO uint32_t UASSTR; /*!< [0x003c] USB Asynchronous Schedule Sleep Timer Register */ 462 /// @cond HIDDEN_SYMBOLS 463 __I uint32_t RESERVE2[8]; 464 /// @endcond //HIDDEN_SYMBOLS 465 __IO uint32_t UCFGR; /*!< [0x0060] USB Configure Flag Register */ 466 __IO uint32_t UPSCR[2]; /*!< [0x0064] ~ [0x0068] USB Port 0 & 1 Status and Control Register */ 467 /// @cond HIDDEN_SYMBOLS 468 __I uint32_t RESERVE3[22]; 469 /// @endcond //HIDDEN_SYMBOLS 470 __IO uint32_t USBPCR0; /*!< [0x00c4] USB PHY 0 Control Register */ 471 __IO uint32_t USBPCR1; /*!< [0x00c8] USB PHY 1 Control Register */ 472 473 } HSUSBH_T; 474 475 /** 476 @addtogroup HSUSBH_CONST HSUSBH Bit Field Definition 477 Constant Definitions for HSUSBH Controller 478 @{ */ 479 480 #define HSUSBH_EHCVNR_CRLEN_Pos (0) /*!< HSUSBH_T::EHCVNR: CRLEN Position */ 481 #define HSUSBH_EHCVNR_CRLEN_Msk (0xfful << HSUSBH_EHCVNR_CRLEN_Pos) /*!< HSUSBH_T::EHCVNR: CRLEN Mask */ 482 483 #define HSUSBH_EHCVNR_VERSION_Pos (16) /*!< HSUSBH_T::EHCVNR: VERSION Position */ 484 #define HSUSBH_EHCVNR_VERSION_Msk (0xfffful << HSUSBH_EHCVNR_VERSION_Pos) /*!< HSUSBH_T::EHCVNR: VERSION Mask */ 485 486 #define HSUSBH_EHCSPR_N_PORTS_Pos (0) /*!< HSUSBH_T::EHCSPR: N_PORTS Position */ 487 #define HSUSBH_EHCSPR_N_PORTS_Msk (0xful << HSUSBH_EHCSPR_N_PORTS_Pos) /*!< HSUSBH_T::EHCSPR: N_PORTS Mask */ 488 489 #define HSUSBH_EHCSPR_PPC_Pos (4) /*!< HSUSBH_T::EHCSPR: PPC Position */ 490 #define HSUSBH_EHCSPR_PPC_Msk (0x1ul << HSUSBH_EHCSPR_PPC_Pos) /*!< HSUSBH_T::EHCSPR: PPC Mask */ 491 492 #define HSUSBH_EHCSPR_N_PCC_Pos (8) /*!< HSUSBH_T::EHCSPR: N_PCC Position */ 493 #define HSUSBH_EHCSPR_N_PCC_Msk (0xful << HSUSBH_EHCSPR_N_PCC_Pos) /*!< HSUSBH_T::EHCSPR: N_PCC Mask */ 494 495 #define HSUSBH_EHCSPR_N_CC_Pos (12) /*!< HSUSBH_T::EHCSPR: N_CC Position */ 496 #define HSUSBH_EHCSPR_N_CC_Msk (0xful << HSUSBH_EHCSPR_N_CC_Pos) /*!< HSUSBH_T::EHCSPR: N_CC Mask */ 497 498 #define HSUSBH_EHCCPR_AC64_Pos (0) /*!< HSUSBH_T::EHCCPR: AC64 Position */ 499 #define HSUSBH_EHCCPR_AC64_Msk (0x1ul << HSUSBH_EHCCPR_AC64_Pos) /*!< HSUSBH_T::EHCCPR: AC64 Mask */ 500 501 #define HSUSBH_EHCCPR_PFLF_Pos (1) /*!< HSUSBH_T::EHCCPR: PFLF Position */ 502 #define HSUSBH_EHCCPR_PFLF_Msk (0x1ul << HSUSBH_EHCCPR_PFLF_Pos) /*!< HSUSBH_T::EHCCPR: PFLF Mask */ 503 504 #define HSUSBH_EHCCPR_ASPC_Pos (2) /*!< HSUSBH_T::EHCCPR: ASPC Position */ 505 #define HSUSBH_EHCCPR_ASPC_Msk (0x1ul << HSUSBH_EHCCPR_ASPC_Pos) /*!< HSUSBH_T::EHCCPR: ASPC Mask */ 506 507 #define HSUSBH_EHCCPR_IST_Pos (4) /*!< HSUSBH_T::EHCCPR: IST Position */ 508 #define HSUSBH_EHCCPR_IST_Msk (0xful << HSUSBH_EHCCPR_IST_Pos) /*!< HSUSBH_T::EHCCPR: IST Mask */ 509 510 #define HSUSBH_EHCCPR_EECP_Pos (8) /*!< HSUSBH_T::EHCCPR: EECP Position */ 511 #define HSUSBH_EHCCPR_EECP_Msk (0xfful << HSUSBH_EHCCPR_EECP_Pos) /*!< HSUSBH_T::EHCCPR: EECP Mask */ 512 513 #define HSUSBH_UCMDR_RUN_Pos (0) /*!< HSUSBH_T::UCMDR: RUN Position */ 514 #define HSUSBH_UCMDR_RUN_Msk (0x1ul << HSUSBH_UCMDR_RUN_Pos) /*!< HSUSBH_T::UCMDR: RUN Mask */ 515 516 #define HSUSBH_UCMDR_HCRST_Pos (1) /*!< HSUSBH_T::UCMDR: HCRST Position */ 517 #define HSUSBH_UCMDR_HCRST_Msk (0x1ul << HSUSBH_UCMDR_HCRST_Pos) /*!< HSUSBH_T::UCMDR: HCRST Mask */ 518 519 #define HSUSBH_UCMDR_FLSZ_Pos (2) /*!< HSUSBH_T::UCMDR: FLSZ Position */ 520 #define HSUSBH_UCMDR_FLSZ_Msk (0x3ul << HSUSBH_UCMDR_FLSZ_Pos) /*!< HSUSBH_T::UCMDR: FLSZ Mask */ 521 522 #define HSUSBH_UCMDR_PSEN_Pos (4) /*!< HSUSBH_T::UCMDR: PSEN Position */ 523 #define HSUSBH_UCMDR_PSEN_Msk (0x1ul << HSUSBH_UCMDR_PSEN_Pos) /*!< HSUSBH_T::UCMDR: PSEN Mask */ 524 525 #define HSUSBH_UCMDR_ASEN_Pos (5) /*!< HSUSBH_T::UCMDR: ASEN Position */ 526 #define HSUSBH_UCMDR_ASEN_Msk (0x1ul << HSUSBH_UCMDR_ASEN_Pos) /*!< HSUSBH_T::UCMDR: ASEN Mask */ 527 528 #define HSUSBH_UCMDR_IAAD_Pos (6) /*!< HSUSBH_T::UCMDR: IAAD Position */ 529 #define HSUSBH_UCMDR_IAAD_Msk (0x1ul << HSUSBH_UCMDR_IAAD_Pos) /*!< HSUSBH_T::UCMDR: IAAD Mask */ 530 531 #define HSUSBH_UCMDR_ITC_Pos (16) /*!< HSUSBH_T::UCMDR: ITC Position */ 532 #define HSUSBH_UCMDR_ITC_Msk (0xfful << HSUSBH_UCMDR_ITC_Pos) /*!< HSUSBH_T::UCMDR: ITC Mask */ 533 534 #define HSUSBH_USTSR_USBINT_Pos (0) /*!< HSUSBH_T::USTSR: USBINT Position */ 535 #define HSUSBH_USTSR_USBINT_Msk (0x1ul << HSUSBH_USTSR_USBINT_Pos) /*!< HSUSBH_T::USTSR: USBINT Mask */ 536 537 #define HSUSBH_USTSR_UERRINT_Pos (1) /*!< HSUSBH_T::USTSR: UERRINT Position */ 538 #define HSUSBH_USTSR_UERRINT_Msk (0x1ul << HSUSBH_USTSR_UERRINT_Pos) /*!< HSUSBH_T::USTSR: UERRINT Mask */ 539 540 #define HSUSBH_USTSR_PCD_Pos (2) /*!< HSUSBH_T::USTSR: PCD Position */ 541 #define HSUSBH_USTSR_PCD_Msk (0x1ul << HSUSBH_USTSR_PCD_Pos) /*!< HSUSBH_T::USTSR: PCD Mask */ 542 543 #define HSUSBH_USTSR_FLR_Pos (3) /*!< HSUSBH_T::USTSR: FLR Position */ 544 #define HSUSBH_USTSR_FLR_Msk (0x1ul << HSUSBH_USTSR_FLR_Pos) /*!< HSUSBH_T::USTSR: FLR Mask */ 545 546 #define HSUSBH_USTSR_HSERR_Pos (4) /*!< HSUSBH_T::USTSR: HSERR Position */ 547 #define HSUSBH_USTSR_HSERR_Msk (0x1ul << HSUSBH_USTSR_HSERR_Pos) /*!< HSUSBH_T::USTSR: HSERR Mask */ 548 549 #define HSUSBH_USTSR_IAA_Pos (5) /*!< HSUSBH_T::USTSR: IAA Position */ 550 #define HSUSBH_USTSR_IAA_Msk (0x1ul << HSUSBH_USTSR_IAA_Pos) /*!< HSUSBH_T::USTSR: IAA Mask */ 551 552 #define HSUSBH_USTSR_HCHalted_Pos (12) /*!< HSUSBH_T::USTSR: HCHalted Position */ 553 #define HSUSBH_USTSR_HCHalted_Msk (0x1ul << HSUSBH_USTSR_HCHalted_Pos) /*!< HSUSBH_T::USTSR: HCHalted Mask */ 554 555 #define HSUSBH_USTSR_RECLA_Pos (13) /*!< HSUSBH_T::USTSR: RECLA Position */ 556 #define HSUSBH_USTSR_RECLA_Msk (0x1ul << HSUSBH_USTSR_RECLA_Pos) /*!< HSUSBH_T::USTSR: RECLA Mask */ 557 558 #define HSUSBH_USTSR_PSS_Pos (14) /*!< HSUSBH_T::USTSR: PSS Position */ 559 #define HSUSBH_USTSR_PSS_Msk (0x1ul << HSUSBH_USTSR_PSS_Pos) /*!< HSUSBH_T::USTSR: PSS Mask */ 560 561 #define HSUSBH_USTSR_ASS_Pos (15) /*!< HSUSBH_T::USTSR: ASS Position */ 562 #define HSUSBH_USTSR_ASS_Msk (0x1ul << HSUSBH_USTSR_ASS_Pos) /*!< HSUSBH_T::USTSR: ASS Mask */ 563 564 #define HSUSBH_UIENR_USBIEN_Pos (0) /*!< HSUSBH_T::UIENR: USBIEN Position */ 565 #define HSUSBH_UIENR_USBIEN_Msk (0x1ul << HSUSBH_UIENR_USBIEN_Pos) /*!< HSUSBH_T::UIENR: USBIEN Mask */ 566 567 #define HSUSBH_UIENR_UERRIEN_Pos (1) /*!< HSUSBH_T::UIENR: UERRIEN Position */ 568 #define HSUSBH_UIENR_UERRIEN_Msk (0x1ul << HSUSBH_UIENR_UERRIEN_Pos) /*!< HSUSBH_T::UIENR: UERRIEN Mask */ 569 570 #define HSUSBH_UIENR_PCIEN_Pos (2) /*!< HSUSBH_T::UIENR: PCIEN Position */ 571 #define HSUSBH_UIENR_PCIEN_Msk (0x1ul << HSUSBH_UIENR_PCIEN_Pos) /*!< HSUSBH_T::UIENR: PCIEN Mask */ 572 573 #define HSUSBH_UIENR_FLREN_Pos (3) /*!< HSUSBH_T::UIENR: FLREN Position */ 574 #define HSUSBH_UIENR_FLREN_Msk (0x1ul << HSUSBH_UIENR_FLREN_Pos) /*!< HSUSBH_T::UIENR: FLREN Mask */ 575 576 #define HSUSBH_UIENR_HSERREN_Pos (4) /*!< HSUSBH_T::UIENR: HSERREN Position */ 577 #define HSUSBH_UIENR_HSERREN_Msk (0x1ul << HSUSBH_UIENR_HSERREN_Pos) /*!< HSUSBH_T::UIENR: HSERREN Mask */ 578 579 #define HSUSBH_UIENR_IAAEN_Pos (5) /*!< HSUSBH_T::UIENR: IAAEN Position */ 580 #define HSUSBH_UIENR_IAAEN_Msk (0x1ul << HSUSBH_UIENR_IAAEN_Pos) /*!< HSUSBH_T::UIENR: IAAEN Mask */ 581 582 #define HSUSBH_UFINDR_FI_Pos (0) /*!< HSUSBH_T::UFINDR: FI Position */ 583 #define HSUSBH_UFINDR_FI_Msk (0x3ffful << HSUSBH_UFINDR_FI_Pos) /*!< HSUSBH_T::UFINDR: FI Mask */ 584 585 #define HSUSBH_UPFLBAR_BADDR_Pos (12) /*!< HSUSBH_T::UPFLBAR: BADDR Position */ 586 #define HSUSBH_UPFLBAR_BADDR_Msk (0xffffful << HSUSBH_UPFLBAR_BADDR_Pos) /*!< HSUSBH_T::UPFLBAR: BADDR Mask */ 587 588 #define HSUSBH_UCALAR_LPL_Pos (5) /*!< HSUSBH_T::UCALAR: LPL Position */ 589 #define HSUSBH_UCALAR_LPL_Msk (0x7fffffful << HSUSBH_UCALAR_LPL_Pos) /*!< HSUSBH_T::UCALAR: LPL Mask */ 590 591 #define HSUSBH_UASSTR_ASSTMR_Pos (0) /*!< HSUSBH_T::UASSTR: ASSTMR Position */ 592 #define HSUSBH_UASSTR_ASSTMR_Msk (0xffful << HSUSBH_UASSTR_ASSTMR_Pos) /*!< HSUSBH_T::UASSTR: ASSTMR Mask */ 593 594 #define HSUSBH_UCFGR_CF_Pos (0) /*!< HSUSBH_T::UCFGR: CF Position */ 595 #define HSUSBH_UCFGR_CF_Msk (0x1ul << HSUSBH_UCFGR_CF_Pos) /*!< HSUSBH_T::UCFGR: CF Mask */ 596 597 #define HSUSBH_UPSCR_CCS_Pos (0) /*!< HSUSBH_T::UPSCR[2]: CCS Position */ 598 #define HSUSBH_UPSCR_CCS_Msk (0x1ul << HSUSBH_UPSCR_CCS_Pos) /*!< HSUSBH_T::UPSCR[2]: CCS Mask */ 599 600 #define HSUSBH_UPSCR_CSC_Pos (1) /*!< HSUSBH_T::UPSCR[2]: CSC Position */ 601 #define HSUSBH_UPSCR_CSC_Msk (0x1ul << HSUSBH_UPSCR_CSC_Pos) /*!< HSUSBH_T::UPSCR[2]: CSC Mask */ 602 603 #define HSUSBH_UPSCR_PE_Pos (2) /*!< HSUSBH_T::UPSCR[2]: PE Position */ 604 #define HSUSBH_UPSCR_PE_Msk (0x1ul << HSUSBH_UPSCR_PE_Pos) /*!< HSUSBH_T::UPSCR[2]: PE Mask */ 605 606 #define HSUSBH_UPSCR_PEC_Pos (3) /*!< HSUSBH_T::UPSCR[2]: PEC Position */ 607 #define HSUSBH_UPSCR_PEC_Msk (0x1ul << HSUSBH_UPSCR_PEC_Pos) /*!< HSUSBH_T::UPSCR[2]: PEC Mask */ 608 609 #define HSUSBH_UPSCR_OCA_Pos (4) /*!< HSUSBH_T::UPSCR[2]: OCA Position */ 610 #define HSUSBH_UPSCR_OCA_Msk (0x1ul << HSUSBH_UPSCR_OCA_Pos) /*!< HSUSBH_T::UPSCR[2]: OCA Mask */ 611 612 #define HSUSBH_UPSCR_OCC_Pos (5) /*!< HSUSBH_T::UPSCR[2]: OCC Position */ 613 #define HSUSBH_UPSCR_OCC_Msk (0x1ul << HSUSBH_UPSCR_OCC_Pos) /*!< HSUSBH_T::UPSCR[2]: OCC Mask */ 614 615 #define HSUSBH_UPSCR_FPR_Pos (6) /*!< HSUSBH_T::UPSCR[2]: FPR Position */ 616 #define HSUSBH_UPSCR_FPR_Msk (0x1ul << HSUSBH_UPSCR_FPR_Pos) /*!< HSUSBH_T::UPSCR[2]: FPR Mask */ 617 618 #define HSUSBH_UPSCR_SUSPEND_Pos (7) /*!< HSUSBH_T::UPSCR[2]: SUSPEND Position */ 619 #define HSUSBH_UPSCR_SUSPEND_Msk (0x1ul << HSUSBH_UPSCR_SUSPEND_Pos) /*!< HSUSBH_T::UPSCR[2]: SUSPEND Mask */ 620 621 #define HSUSBH_UPSCR_PRST_Pos (8) /*!< HSUSBH_T::UPSCR[2]: PRST Position */ 622 #define HSUSBH_UPSCR_PRST_Msk (0x1ul << HSUSBH_UPSCR_PRST_Pos) /*!< HSUSBH_T::UPSCR[2]: PRST Mask */ 623 624 #define HSUSBH_UPSCR_LSTS_Pos (10) /*!< HSUSBH_T::UPSCR[2]: LSTS Position */ 625 #define HSUSBH_UPSCR_LSTS_Msk (0x3ul << HSUSBH_UPSCR_LSTS_Pos) /*!< HSUSBH_T::UPSCR[2]: LSTS Mask */ 626 627 #define HSUSBH_UPSCR_PP_Pos (12) /*!< HSUSBH_T::UPSCR[2]: PP Position */ 628 #define HSUSBH_UPSCR_PP_Msk (0x1ul << HSUSBH_UPSCR_PP_Pos) /*!< HSUSBH_T::UPSCR[2]: PP Mask */ 629 630 #define HSUSBH_UPSCR_PO_Pos (13) /*!< HSUSBH_T::UPSCR[2]: PO Position */ 631 #define HSUSBH_UPSCR_PO_Msk (0x1ul << HSUSBH_UPSCR_PO_Pos) /*!< HSUSBH_T::UPSCR[2]: PO Mask */ 632 633 #define HSUSBH_UPSCR_PTC_Pos (16) /*!< HSUSBH_T::UPSCR[2]: PTC Position */ 634 #define HSUSBH_UPSCR_PTC_Msk (0xful << HSUSBH_UPSCR_PTC_Pos) /*!< HSUSBH_T::UPSCR[2]: PTC Mask */ 635 636 #define HSUSBH_USBPCR0_SUSPEND_Pos (8) /*!< HSUSBH_T::USBPCR0: SUSPEND Position */ 637 #define HSUSBH_USBPCR0_SUSPEND_Msk (0x1ul << HSUSBH_USBPCR0_SUSPEND_Pos) /*!< HSUSBH_T::USBPCR0: SUSPEND Mask */ 638 639 #define HSUSBH_USBPCR0_CLKVALID_Pos (11) /*!< HSUSBH_T::USBPCR0: CLKVALID Position */ 640 #define HSUSBH_USBPCR0_CLKVALID_Msk (0x1ul << HSUSBH_USBPCR0_CLKVALID_Pos) /*!< HSUSBH_T::USBPCR0: CLKVALID Mask */ 641 642 #define HSUSBH_USBPCR1_SUSPEND_Pos (8) /*!< HSUSBH_T::USBPCR1: SUSPEND Position */ 643 #define HSUSBH_USBPCR1_SUSPEND_Msk (0x1ul << HSUSBH_USBPCR1_SUSPEND_Pos) /*!< HSUSBH_T::USBPCR1: SUSPEND Mask */ 644 645 /**@}*/ /* HSUSBH_CONST */ 646 /**@}*/ /* end of HSUSBH register group */ 647 /**@}*/ /* end of REGISTER group */ 648 649 #if defined ( __CC_ARM ) 650 #pragma no_anon_unions 651 #endif 652 653 #endif /* __HSUSBH_REG_H__ */ 654
