1 /**************************************************************************//** 2 * @file bpwm_reg.h 3 * @version V1.00 4 * @brief BPWM register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __BPWM_REG_H__ 10 #define __BPWM_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup BPWM Basic Pulse Width Modulation Controller(BPWM) 23 Memory Mapped Structure for BPWM Controller 24 @{ */ 25 26 typedef struct 27 { 28 /** 29 * @var BCAPDAT_T::RCAPDAT 30 * Offset: 0x20C BPWM Rising Capture Data Register 0~5 31 * --------------------------------------------------------------------------------------------------- 32 * |Bits |Field |Descriptions 33 * | :----: | :----: | :---- | 34 * |[15:0] |RCAPDAT |BPWM Rising Capture Data (Read Only) 35 * | | |When rising capture condition happened, the BPWM counter value will be saved in this register. 36 * @var BCAPDAT_T::FCAPDAT 37 * Offset: 0x210 BPWM Falling Capture Data Register 0~5 38 * --------------------------------------------------------------------------------------------------- 39 * |Bits |Field |Descriptions 40 * | :----: | :----: | :---- | 41 * |[15:0] |FCAPDAT |BPWM Falling Capture Data (Read Only) 42 * | | |When falling capture condition happened, the BPWM counter value will be saved in this register. 43 */ 44 __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] BPWM Rising Capture Data Register 0~5 */ 45 __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] BPWM Falling Capture Data Register 0~5 */ 46 } BCAPDAT_T; 47 48 typedef struct 49 { 50 51 52 /** 53 * @var BPWM_T::CTL0 54 * Offset: 0x00 BPWM Control Register 0 55 * --------------------------------------------------------------------------------------------------- 56 * |Bits |Field |Descriptions 57 * | :----: | :----: | :---- | 58 * |[0] |CTRLD0 |Center Re-load 59 * | | |Each bit n controls the corresponding BPWM channel n. 60 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period 61 * | | |CMPDAT will load to CMPBUF at the center point of a period 62 * |[1] |CTRLD1 |Center Re-load 63 * | | |Each bit n controls the corresponding BPWM channel n. 64 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period 65 * | | |CMPDAT will load to CMPBUF at the center point of a period 66 * |[2] |CTRLD2 |Center Re-load 67 * | | |Each bit n controls the corresponding BPWM channel n. 68 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period 69 * | | |CMPDAT will load to CMPBUF at the center point of a period 70 * |[3] |CTRLD3 |Center Re-load 71 * | | |Each bit n controls the corresponding BPWM channel n. 72 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period 73 * | | |CMPDAT will load to CMPBUF at the center point of a period 74 * |[4] |CTRLD4 |Center Re-load 75 * | | |Each bit n controls the corresponding BPWM channel n. 76 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period 77 * | | |CMPDAT will load to CMPBUF at the center point of a period 78 * |[5] |CTRLD5 |Center Re-load 79 * | | |Each bit n controls the corresponding BPWM channel n. 80 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period 81 * | | |CMPDAT will load to CMPBUF at the center point of a period 82 * |[16] |IMMLDEN0 |Immediately Load Enable Bit(S) 83 * | | |Each bit n controls the corresponding BPWM channel n. 84 * | | |0 = PERIOD will load to PBUF at the end point of each period 85 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 86 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. 87 * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. 88 * |[17] |IMMLDEN1 |Immediately Load Enable Bit(S) 89 * | | |Each bit n controls the corresponding BPWM channel n. 90 * | | |0 = PERIOD will load to PBUF at the end point of each period 91 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 92 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. 93 * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. 94 * |[18] |IMMLDEN2 |Immediately Load Enable Bit(S) 95 * | | |Each bit n controls the corresponding BPWM channel n. 96 * | | |0 = PERIOD will load to PBUF at the end point of each period 97 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 98 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. 99 * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. 100 * |[19] |IMMLDEN3 |Immediately Load Enable Bit(S) 101 * | | |Each bit n controls the corresponding BPWM channel n. 102 * | | |0 = PERIOD will load to PBUF at the end point of each period 103 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 104 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. 105 * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. 106 * |[20] |IMMLDEN4 |Immediately Load Enable Bit(S) 107 * | | |Each bit n controls the corresponding BPWM channel n. 108 * | | |0 = PERIOD will load to PBUF at the end point of each period 109 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 110 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. 111 * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. 112 * |[21] |IMMLDEN5 |Immediately Load Enable Bit(S) 113 * | | |Each bit n controls the corresponding BPWM channel n. 114 * | | |0 = PERIOD will load to PBUF at the end point of each period 115 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 116 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. 117 * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. 118 * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) 119 * | | |If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode. 120 * | | |0 = ICE debug mode counter halt Disabled. 121 * | | |1 = ICE debug mode counter halt Enabled. 122 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 123 * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect) 124 * | | |0 = ICE debug mode acknowledgement effects BPWM output. 125 * | | |BPWM pin will be forced as tri-state while ICE debug mode acknowledged. 126 * | | |1 = ICE debug mode acknowledgement Disabled. 127 * | | |BPWM pin will keep output no matter ICE debug mode acknowledged or not. 128 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 129 * @var BPWM_T::CTL1 130 * Offset: 0x04 BPWM Control Register 1 131 * --------------------------------------------------------------------------------------------------- 132 * |Bits |Field |Descriptions 133 * | :----: | :----: | :---- | 134 * |[1:0] |CNTTYPE0 |BPWM Counter Behavior Type 0 135 * | | |Each bit n controls corresponding BPWM channel n. 136 * | | |00 = Up counter type (supports in capture mode). 137 * | | |01 = Down count type (supports in capture mode). 138 * | | |10 = Up-down counter type. 139 * | | |11 = Reserved. 140 * @var BPWM_T::CLKSRC 141 * Offset: 0x10 BPWM Clock Source Register 142 * --------------------------------------------------------------------------------------------------- 143 * |Bits |Field |Descriptions 144 * | :----: | :----: | :---- | 145 * |[2:0] |ECLKSRC0 |BPWM_CH01 External Clock Source Select 146 * | | |000 = BPWMx_CLK, x denotes 0 or 1. 147 * | | |001 = TIMER0 overflow. 148 * | | |010 = TIMER1 overflow. 149 * | | |011 = TIMER2 overflow. 150 * | | |100 = TIMER3 overflow. 151 * | | |Others = Reserved. 152 * @var BPWM_T::CLKPSC 153 * Offset: 0x14 BPWM Clock Prescale Register 154 * --------------------------------------------------------------------------------------------------- 155 * |Bits |Field |Descriptions 156 * | :----: | :----: | :---- | 157 * |[11:0] |CLKPSC |BPWM Counter Clock Prescale 158 * | | |The clock of BPWM counter is decided by clock prescaler 159 * | | |Each BPWM pair share one BPWM counter clock prescaler 160 * | | |The clock of BPWM counter is divided by (CLKPSC+ 1) 161 * @var BPWM_T::CNTEN 162 * Offset: 0x20 BPWM Counter Enable Register 163 * --------------------------------------------------------------------------------------------------- 164 * |Bits |Field |Descriptions 165 * | :----: | :----: | :---- | 166 * |[0] |CNTEN0 |BPWM Counter 0 Enable Bit 167 * | | |0 = BPWM Counter and clock prescaler stop running. 168 * | | |1 = BPWM Counter and clock prescaler start running. 169 * @var BPWM_T::CNTCLR 170 * Offset: 0x24 BPWM Clear Counter Register 171 * --------------------------------------------------------------------------------------------------- 172 * |Bits |Field |Descriptions 173 * | :----: | :----: | :---- | 174 * |[0] |CNTCLR0 |Clear BPWM Counter Control Bit 0 175 * | | |It is automatically cleared by hardware. 176 * | | |0 = No effect. 177 * | | |1 = Clear 16-bit BPWM counter to 0000H. 178 * @var BPWM_T::PERIOD 179 * Offset: 0x30 BPWM Period Register 180 * --------------------------------------------------------------------------------------------------- 181 * |Bits |Field |Descriptions 182 * | :----: | :----: | :---- | 183 * |[15:0] |PERIOD |BPWM Period Register 184 * | | |Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0. 185 * | | |Down-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD. 186 * | | |BPWM period time = (PERIOD+1) * BPWM_CLK period. 187 * | | |Up-Down-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. 188 * | | |BPWM period time = 2 * PERIOD * BPWM_CLK period. 189 * @var BPWM_T::CMPDAT[6] 190 * Offset: 0x50 BPWM Comparator Register 0~5 191 * --------------------------------------------------------------------------------------------------- 192 * |Bits |Field |Descriptions 193 * | :----: | :----: | :---- | 194 * |[15:0] |CMPDAT |BPWM Comparator Register 195 * | | |CMPDAT use to compare with CNTR to generate BPWM waveform, interrupt and trigger EADC. 196 * | | |In independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point. 197 * @var BPWM_T::CNT 198 * Offset: 0x90 BPWM Counter Register 199 * --------------------------------------------------------------------------------------------------- 200 * |Bits |Field |Descriptions 201 * | :----: | :----: | :---- | 202 * |[15:0] |CNT |BPWM Data Register (Read Only) 203 * | | |User can monitor CNTR to know the current value in 16-bit period counter. 204 * |[16] |DIRF |BPWM Direction Indicator Flag (Read Only) 205 * | | |0 = Counter is Down count. 206 * | | |1 = Counter is UP count. 207 * @var BPWM_T::WGCTL0 208 * Offset: 0xB0 BPWM Generation Register 0 209 * --------------------------------------------------------------------------------------------------- 210 * |Bits |Field |Descriptions 211 * | :----: | :----: | :---- | 212 * |[1:0] |ZPCTL0 |BPWM Zero Point Control 213 * | | |Each bit n controls the corresponding BPWM channel n. 214 * | | |00 = Do nothing. 215 * | | |01 = BPWM zero point output Low. 216 * | | |10 = BPWM zero point output High. 217 * | | |11 = BPWM zero point output Toggle. 218 * | | |BPWM can control output level when BPWM counter count to zero. 219 * |[3:2] |ZPCTL1 |BPWM Zero Point Control 220 * | | |Each bit n controls the corresponding BPWM channel n. 221 * | | |00 = Do nothing. 222 * | | |01 = BPWM zero point output Low. 223 * | | |10 = BPWM zero point output High. 224 * | | |11 = BPWM zero point output Toggle. 225 * | | |BPWM can control output level when BPWM counter count to zero. 226 * |[5:4] |ZPCTL2 |BPWM Zero Point Control 227 * | | |Each bit n controls the corresponding BPWM channel n. 228 * | | |00 = Do nothing. 229 * | | |01 = BPWM zero point output Low. 230 * | | |10 = BPWM zero point output High. 231 * | | |11 = BPWM zero point output Toggle. 232 * | | |BPWM can control output level when BPWM counter count to zero. 233 * |[7:6] |ZPCTL3 |BPWM Zero Point Control 234 * | | |Each bit n controls the corresponding BPWM channel n. 235 * | | |00 = Do nothing. 236 * | | |01 = BPWM zero point output Low. 237 * | | |10 = BPWM zero point output High. 238 * | | |11 = BPWM zero point output Toggle. 239 * | | |BPWM can control output level when BPWM counter count to zero. 240 * |[9:8] |ZPCTL4 |BPWM Zero Point Control 241 * | | |Each bit n controls the corresponding BPWM channel n. 242 * | | |00 = Do nothing. 243 * | | |01 = BPWM zero point output Low. 244 * | | |10 = BPWM zero point output High. 245 * | | |11 = BPWM zero point output Toggle. 246 * | | |BPWM can control output level when BPWM counter count to zero. 247 * |[11:10] |ZPCTL5 |BPWM Zero Point Control 248 * | | |Each bit n controls the corresponding BPWM channel n. 249 * | | |00 = Do nothing. 250 * | | |01 = BPWM zero point output Low. 251 * | | |10 = BPWM zero point output High. 252 * | | |11 = BPWM zero point output Toggle. 253 * | | |BPWM can control output level when BPWM counter count to zero. 254 * |[17:16] |PRDPCTL0 |BPWM Period (Center) Point Control 255 * | | |Each bit n controls the corresponding BPWM channel n. 256 * | | |00 = Do nothing. 257 * | | |01 = BPWM period (center) point output Low. 258 * | | |10 = BPWM period (center) point output High. 259 * | | |11 = BPWM period (center) point output Toggle. 260 * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). 261 * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. 262 * |[19:18] |PRDPCTL1 |BPWM Period (Center) Point Control 263 * | | |Each bit n controls the corresponding BPWM channel n. 264 * | | |00 = Do nothing. 265 * | | |01 = BPWM period (center) point output Low. 266 * | | |10 = BPWM period (center) point output High. 267 * | | |11 = BPWM period (center) point output Toggle. 268 * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). 269 * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. 270 * |[21:20] |PRDPCTL2 |BPWM Period (Center) Point Control 271 * | | |Each bit n controls the corresponding BPWM channel n. 272 * | | |00 = Do nothing. 273 * | | |01 = BPWM period (center) point output Low. 274 * | | |10 = BPWM period (center) point output High. 275 * | | |11 = BPWM period (center) point output Toggle. 276 * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). 277 * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. 278 * |[23:22] |PRDPCTL3 |BPWM Period (Center) Point Control 279 * | | |Each bit n controls the corresponding BPWM channel n. 280 * | | |00 = Do nothing. 281 * | | |01 = BPWM period (center) point output Low. 282 * | | |10 = BPWM period (center) point output High. 283 * | | |11 = BPWM period (center) point output Toggle. 284 * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). 285 * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. 286 * |[25:24] |PRDPCTL4 |BPWM Period (Center) Point Control 287 * | | |Each bit n controls the corresponding BPWM channel n. 288 * | | |00 = Do nothing. 289 * | | |01 = BPWM period (center) point output Low. 290 * | | |10 = BPWM period (center) point output High. 291 * | | |11 = BPWM period (center) point output Toggle. 292 * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). 293 * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. 294 * |[27:26] |PRDPCTL5 |BPWM Period (Center) Point Control 295 * | | |Each bit n controls the corresponding BPWM channel n. 296 * | | |00 = Do nothing. 297 * | | |01 = BPWM period (center) point output Low. 298 * | | |10 = BPWM period (center) point output High. 299 * | | |11 = BPWM period (center) point output Toggle. 300 * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). 301 * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. 302 * @var BPWM_T::WGCTL1 303 * Offset: 0xB4 BPWM Generation Register 1 304 * --------------------------------------------------------------------------------------------------- 305 * |Bits |Field |Descriptions 306 * | :----: | :----: | :---- | 307 * |[1:0] |CMPUCTL0 |BPWM Compare Up Point Control 308 * | | |Each bit n controls the corresponding BPWM channel n. 309 * | | |00 = Do nothing. 310 * | | |01 = BPWM compare up point output Low. 311 * | | |10 = BPWM compare up point output High. 312 * | | |11 = BPWM compare up point output Toggle. 313 * | | |BPWM can control output level when BPWM counter up count to CMPDAT. 314 * |[3:2] |CMPUCTL1 |BPWM Compare Up Point Control 315 * | | |Each bit n controls the corresponding BPWM channel n. 316 * | | |00 = Do nothing. 317 * | | |01 = BPWM compare up point output Low. 318 * | | |10 = BPWM compare up point output High. 319 * | | |11 = BPWM compare up point output Toggle. 320 * | | |BPWM can control output level when BPWM counter up count to CMPDAT. 321 * |[5:4] |CMPUCTL2 |BPWM Compare Up Point Control 322 * | | |Each bit n controls the corresponding BPWM channel n. 323 * | | |00 = Do nothing. 324 * | | |01 = BPWM compare up point output Low. 325 * | | |10 = BPWM compare up point output High. 326 * | | |11 = BPWM compare up point output Toggle. 327 * | | |BPWM can control output level when BPWM counter up count to CMPDAT. 328 * |[7:6] |CMPUCTL3 |BPWM Compare Up Point Control 329 * | | |Each bit n controls the corresponding BPWM channel n. 330 * | | |00 = Do nothing. 331 * | | |01 = BPWM compare up point output Low. 332 * | | |10 = BPWM compare up point output High. 333 * | | |11 = BPWM compare up point output Toggle. 334 * | | |BPWM can control output level when BPWM counter up count to CMPDAT. 335 * |[9:8] |CMPUCTL4 |BPWM Compare Up Point Control 336 * | | |Each bit n controls the corresponding BPWM channel n. 337 * | | |00 = Do nothing. 338 * | | |01 = BPWM compare up point output Low. 339 * | | |10 = BPWM compare up point output High. 340 * | | |11 = BPWM compare up point output Toggle. 341 * | | |BPWM can control output level when BPWM counter up count to CMPDAT. 342 * |[11:10] |CMPUCTL5 |BPWM Compare Up Point Control 343 * | | |Each bit n controls the corresponding BPWM channel n. 344 * | | |00 = Do nothing. 345 * | | |01 = BPWM compare up point output Low. 346 * | | |10 = BPWM compare up point output High. 347 * | | |11 = BPWM compare up point output Toggle. 348 * | | |BPWM can control output level when BPWM counter up count to CMPDAT. 349 * |[17:16] |CMPDCTL0 |BPWM Compare Down Point Control 350 * | | |Each bit n controls the corresponding BPWM channel n. 351 * | | |00 = Do nothing. 352 * | | |01 = BPWM compare down point output Low. 353 * | | |10 = BPWM compare down point output High. 354 * | | |11 = BPWM compare down point output Toggle. 355 * | | |BPWM can control output level when BPWM counter down count to CMPDAT. 356 * |[19:18] |CMPDCTL1 |BPWM Compare Down Point Control 357 * | | |Each bit n controls the corresponding BPWM channel n. 358 * | | |00 = Do nothing. 359 * | | |01 = BPWM compare down point output Low. 360 * | | |10 = BPWM compare down point output High. 361 * | | |11 = BPWM compare down point output Toggle. 362 * | | |BPWM can control output level when BPWM counter down count to CMPDAT. 363 * |[21:20] |CMPDCTL2 |BPWM Compare Down Point Control 364 * | | |Each bit n controls the corresponding BPWM channel n. 365 * | | |00 = Do nothing. 366 * | | |01 = BPWM compare down point output Low. 367 * | | |10 = BPWM compare down point output High. 368 * | | |11 = BPWM compare down point output Toggle. 369 * | | |BPWM can control output level when BPWM counter down count to CMPDAT. 370 * |[23:22] |CMPDCTL3 |BPWM Compare Down Point Control 371 * | | |Each bit n controls the corresponding BPWM channel n. 372 * | | |00 = Do nothing. 373 * | | |01 = BPWM compare down point output Low. 374 * | | |10 = BPWM compare down point output High. 375 * | | |11 = BPWM compare down point output Toggle. 376 * | | |BPWM can control output level when BPWM counter down count to CMPDAT. 377 * |[25:24] |CMPDCTL4 |BPWM Compare Down Point Control 378 * | | |Each bit n controls the corresponding BPWM channel n. 379 * | | |00 = Do nothing. 380 * | | |01 = BPWM compare down point output Low. 381 * | | |10 = BPWM compare down point output High. 382 * | | |11 = BPWM compare down point output Toggle. 383 * | | |BPWM can control output level when BPWM counter down count to CMPDAT. 384 * |[27:26] |CMPDCTL5 |BPWM Compare Down Point Control 385 * | | |Each bit n controls the corresponding BPWM channel n. 386 * | | |00 = Do nothing. 387 * | | |01 = BPWM compare down point output Low. 388 * | | |10 = BPWM compare down point output High. 389 * | | |11 = BPWM compare down point output Toggle. 390 * | | |BPWM can control output level when BPWM counter down count to CMPDAT. 391 * @var BPWM_T::MSKEN 392 * Offset: 0xB8 BPWM Mask Enable Register 393 * --------------------------------------------------------------------------------------------------- 394 * |Bits |Field |Descriptions 395 * | :----: | :----: | :---- | 396 * |[0] |MSKEN0 |BPWM Mask Enable Bits 397 * | | |Each bit n controls the corresponding BPWM channel n. 398 * | | |The BPWM output signal will be masked when this bit is enabled 399 * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 400 * | | |0 = BPWM output signal is non-masked. 401 * | | |1 = BPWM output signal is masked and output MSKDATn data. 402 * |[1] |MSKEN1 |BPWM Mask Enable Bits 403 * | | |Each bit n controls the corresponding BPWM channel n. 404 * | | |The BPWM output signal will be masked when this bit is enabled 405 * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 406 * | | |0 = BPWM output signal is non-masked. 407 * | | |1 = BPWM output signal is masked and output MSKDATn data. 408 * |[2] |MSKEN2 |BPWM Mask Enable Bits 409 * | | |Each bit n controls the corresponding BPWM channel n. 410 * | | |The BPWM output signal will be masked when this bit is enabled 411 * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 412 * | | |0 = BPWM output signal is non-masked. 413 * | | |1 = BPWM output signal is masked and output MSKDATn data. 414 * |[3] |MSKEN3 |BPWM Mask Enable Bits 415 * | | |Each bit n controls the corresponding BPWM channel n. 416 * | | |The BPWM output signal will be masked when this bit is enabled 417 * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 418 * | | |0 = BPWM output signal is non-masked. 419 * | | |1 = BPWM output signal is masked and output MSKDATn data. 420 * |[4] |MSKEN4 |BPWM Mask Enable Bits 421 * | | |Each bit n controls the corresponding BPWM channel n. 422 * | | |The BPWM output signal will be masked when this bit is enabled 423 * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 424 * | | |0 = BPWM output signal is non-masked. 425 * | | |1 = BPWM output signal is masked and output MSKDATn data. 426 * |[5] |MSKEN5 |BPWM Mask Enable Bits 427 * | | |Each bit n controls the corresponding BPWM channel n. 428 * | | |The BPWM output signal will be masked when this bit is enabled 429 * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 430 * | | |0 = BPWM output signal is non-masked. 431 * | | |1 = BPWM output signal is masked and output MSKDATn data. 432 * @var BPWM_T::MSK 433 * Offset: 0xBC BPWM Mask Data Register 434 * --------------------------------------------------------------------------------------------------- 435 * |Bits |Field |Descriptions 436 * | :----: | :----: | :---- | 437 * |[0] |MSKDAT0 |BPWM Mask Data Bit 438 * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled 439 * | | |Each bit n controls the corresponding BPWM channel n. 440 * | | |0 = Output logic low to BPWMn. 441 * | | |1 = Output logic high to BPWMn. 442 * |[1] |MSKDAT1 |BPWM Mask Data Bit 443 * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled 444 * | | |Each bit n controls the corresponding BPWM channel n. 445 * | | |0 = Output logic low to BPWMn. 446 * | | |1 = Output logic high to BPWMn. 447 * |[2] |MSKDAT2 |BPWM Mask Data Bit 448 * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled 449 * | | |Each bit n controls the corresponding BPWM channel n. 450 * | | |0 = Output logic low to BPWMn. 451 * | | |1 = Output logic high to BPWMn. 452 * |[3] |MSKDAT3 |BPWM Mask Data Bit 453 * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled 454 * | | |Each bit n controls the corresponding BPWM channel n. 455 * | | |0 = Output logic low to BPWMn. 456 * | | |1 = Output logic high to BPWMn. 457 * |[4] |MSKDAT4 |BPWM Mask Data Bit 458 * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled 459 * | | |Each bit n controls the corresponding BPWM channel n. 460 * | | |0 = Output logic low to BPWMn. 461 * | | |1 = Output logic high to BPWMn. 462 * |[5] |MSKDAT5 |BPWM Mask Data Bit 463 * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled 464 * | | |Each bit n controls the corresponding BPWM channel n. 465 * | | |0 = Output logic low to BPWMn. 466 * | | |1 = Output logic high to BPWMn. 467 * @var BPWM_T::POLCTL 468 * Offset: 0xD4 BPWM Pin Polar Inverse Register 469 * --------------------------------------------------------------------------------------------------- 470 * |Bits |Field |Descriptions 471 * | :----: | :----: | :---- | 472 * |[0] |PINV0 |BPWM PIN Polar Inverse Control 473 * | | |The register controls polarity state of BPWM output 474 * | | |Each bit n controls the corresponding BPWM channel n. 475 * | | |0 = BPWM output polar inverse Disabled. 476 * | | |1 = BPWM output polar inverse Enabled. 477 * |[1] |PINV1 |BPWM PIN Polar Inverse Control 478 * | | |The register controls polarity state of BPWM output 479 * | | |Each bit n controls the corresponding BPWM channel n. 480 * | | |0 = BPWM output polar inverse Disabled. 481 * | | |1 = BPWM output polar inverse Enabled. 482 * |[2] |PINV2 |BPWM PIN Polar Inverse Control 483 * | | |The register controls polarity state of BPWM output 484 * | | |Each bit n controls the corresponding BPWM channel n. 485 * | | |0 = BPWM output polar inverse Disabled. 486 * | | |1 = BPWM output polar inverse Enabled. 487 * |[3] |PINV3 |BPWM PIN Polar Inverse Control 488 * | | |The register controls polarity state of BPWM output 489 * | | |Each bit n controls the corresponding BPWM channel n. 490 * | | |0 = BPWM output polar inverse Disabled. 491 * | | |1 = BPWM output polar inverse Enabled. 492 * |[4] |PINV4 |BPWM PIN Polar Inverse Control 493 * | | |The register controls polarity state of BPWM output 494 * | | |Each bit n controls the corresponding BPWM channel n. 495 * | | |0 = BPWM output polar inverse Disabled. 496 * | | |1 = BPWM output polar inverse Enabled. 497 * |[5] |PINV5 |BPWM PIN Polar Inverse Control 498 * | | |The register controls polarity state of BPWM output 499 * | | |Each bit n controls the corresponding BPWM channel n. 500 * | | |0 = BPWM output polar inverse Disabled. 501 * | | |1 = BPWM output polar inverse Enabled. 502 * @var BPWM_T::POEN 503 * Offset: 0xD8 BPWM Output Enable Register 504 * --------------------------------------------------------------------------------------------------- 505 * |Bits |Field |Descriptions 506 * | :----: | :----: | :---- | 507 * |[0] |POEN0 |BPWM Pin Output Enable Bits 508 * | | |Each bit n controls the corresponding BPWM channel n. 509 * | | |0 = BPWM pin at tri-state. 510 * | | |1 = BPWM pin in output mode. 511 * |[1] |POEN1 |BPWM Pin Output Enable Bits 512 * | | |Each bit n controls the corresponding BPWM channel n. 513 * | | |0 = BPWM pin at tri-state. 514 * | | |1 = BPWM pin in output mode. 515 * |[2] |POEN2 |BPWM Pin Output Enable Bits 516 * | | |Each bit n controls the corresponding BPWM channel n. 517 * | | |0 = BPWM pin at tri-state. 518 * | | |1 = BPWM pin in output mode. 519 * |[3] |POEN3 |BPWM Pin Output Enable Bits 520 * | | |Each bit n controls the corresponding BPWM channel n. 521 * | | |0 = BPWM pin at tri-state. 522 * | | |1 = BPWM pin in output mode. 523 * |[4] |POEN4 |BPWM Pin Output Enable Bits 524 * | | |Each bit n controls the corresponding BPWM channel n. 525 * | | |0 = BPWM pin at tri-state. 526 * | | |1 = BPWM pin in output mode. 527 * |[5] |POEN5 |BPWM Pin Output Enable Bits 528 * | | |Each bit n controls the corresponding BPWM channel n. 529 * | | |0 = BPWM pin at tri-state. 530 * | | |1 = BPWM pin in output mode. 531 * @var BPWM_T::INTEN 532 * Offset: 0xE0 BPWM Interrupt Enable Register 533 * --------------------------------------------------------------------------------------------------- 534 * |Bits |Field |Descriptions 535 * | :----: | :----: | :---- | 536 * |[0] |ZIEN0 |BPWM Zero Point Interrupt 0 Enable Bit 537 * | | |0 = Zero point interrupt Disabled. 538 * | | |1 = Zero point interrupt Enabled. 539 * |[8] |PIEN0 |BPWM Period Point Interrupt 0 Enable Bit 540 * | | |0 = Period point interrupt Disabled. 541 * | | |1 = Period point interrupt Enabled. 542 * | | |Note: When up-down counter type period point means center point. 543 * |[16] |CMPUIEN0 |BPWM Compare Up Count Interrupt Enable Bits 544 * | | |Each bit n controls the corresponding BPWM channel n. 545 * | | |0 = Compare up count interrupt Disabled. 546 * | | |1 = Compare up count interrupt Enabled. 547 * |[17] |CMPUIEN1 |BPWM Compare Up Count Interrupt Enable Bits 548 * | | |Each bit n controls the corresponding BPWM channel n. 549 * | | |0 = Compare up count interrupt Disabled. 550 * | | |1 = Compare up count interrupt Enabled. 551 * |[18] |CMPUIEN2 |BPWM Compare Up Count Interrupt Enable Bits 552 * | | |Each bit n controls the corresponding BPWM channel n. 553 * | | |0 = Compare up count interrupt Disabled. 554 * | | |1 = Compare up count interrupt Enabled. 555 * |[19] |CMPUIEN3 |BPWM Compare Up Count Interrupt Enable Bits 556 * | | |Each bit n controls the corresponding BPWM channel n. 557 * | | |0 = Compare up count interrupt Disabled. 558 * | | |1 = Compare up count interrupt Enabled. 559 * |[20] |CMPUIEN4 |BPWM Compare Up Count Interrupt Enable Bits 560 * | | |Each bit n controls the corresponding BPWM channel n. 561 * | | |0 = Compare up count interrupt Disabled. 562 * | | |1 = Compare up count interrupt Enabled. 563 * |[21] |CMPUIEN5 |BPWM Compare Up Count Interrupt Enable Bits 564 * | | |Each bit n controls the corresponding BPWM channel n. 565 * | | |0 = Compare up count interrupt Disabled. 566 * | | |1 = Compare up count interrupt Enabled. 567 * |[24] |CMPDIEN0 |BPWM Compare Down Count Interrupt Enable Bits 568 * | | |Each bit n controls the corresponding BPWM channel n. 569 * | | |0 = Compare down count interrupt Disabled. 570 * | | |1 = Compare down count interrupt Enabled. 571 * |[25] |CMPDIEN1 |BPWM Compare Down Count Interrupt Enable Bits 572 * | | |Each bit n controls the corresponding BPWM channel n. 573 * | | |0 = Compare down count interrupt Disabled. 574 * | | |1 = Compare down count interrupt Enabled. 575 * |[26] |CMPDIEN2 |BPWM Compare Down Count Interrupt Enable Bits 576 * | | |Each bit n controls the corresponding BPWM channel n. 577 * | | |0 = Compare down count interrupt Disabled. 578 * | | |1 = Compare down count interrupt Enabled. 579 * |[27] |CMPDIEN3 |BPWM Compare Down Count Interrupt Enable Bits 580 * | | |Each bit n controls the corresponding BPWM channel n. 581 * | | |0 = Compare down count interrupt Disabled. 582 * | | |1 = Compare down count interrupt Enabled. 583 * |[28] |CMPDIEN4 |BPWM Compare Down Count Interrupt Enable Bits 584 * | | |Each bit n controls the corresponding BPWM channel n. 585 * | | |0 = Compare down count interrupt Disabled. 586 * | | |1 = Compare down count interrupt Enabled. 587 * |[29] |CMPDIEN5 |BPWM Compare Down Count Interrupt Enable Bits 588 * | | |Each bit n controls the corresponding BPWM channel n. 589 * | | |0 = Compare down count interrupt Disabled. 590 * | | |1 = Compare down count interrupt Enabled. 591 * @var BPWM_T::INTSTS 592 * Offset: 0xE8 BPWM Interrupt Flag Register 593 * --------------------------------------------------------------------------------------------------- 594 * |Bits |Field |Descriptions 595 * | :----: | :----: | :---- | 596 * |[0] |ZIF0 |BPWM Zero Point Interrupt Flag 0 597 * | | |This bit is set by hardware when BPWM_CH0 counter reaches zero, software can write 1 to clear this bit to zero. 598 * |[8] |PIF0 |BPWM Period Point Interrupt Flag 0 599 * | | |This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to zero. 600 * |[16] |CMPUIF0 |BPWM Compare Up Count Interrupt Flag 601 * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it 602 * | | |Each bit n controls the corresponding BPWM channel n. 603 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 604 * |[17] |CMPUIF1 |BPWM Compare Up Count Interrupt Flag 605 * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it 606 * | | |Each bit n controls the corresponding BPWM channel n. 607 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 608 * |[18] |CMPUIF2 |BPWM Compare Up Count Interrupt Flag 609 * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it 610 * | | |Each bit n controls the corresponding BPWM channel n. 611 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 612 * |[19] |CMPUIF3 |BPWM Compare Up Count Interrupt Flag 613 * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it 614 * | | |Each bit n controls the corresponding BPWM channel n. 615 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 616 * |[20] |CMPUIF4 |BPWM Compare Up Count Interrupt Flag 617 * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it 618 * | | |Each bit n controls the corresponding BPWM channel n. 619 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 620 * |[21] |CMPUIF5 |BPWM Compare Up Count Interrupt Flag 621 * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it 622 * | | |Each bit n controls the corresponding BPWM channel n. 623 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 624 * |[24] |CMPDIF0 |BPWM Compare Down Count Interrupt Flag 625 * | | |Each bit n controls the corresponding BPWM channel n. 626 * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. 627 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 628 * |[25] |CMPDIF1 |BPWM Compare Down Count Interrupt Flag 629 * | | |Each bit n controls the corresponding BPWM channel n. 630 * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. 631 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 632 * |[26] |CMPDIF2 |BPWM Compare Down Count Interrupt Flag 633 * | | |Each bit n controls the corresponding BPWM channel n. 634 * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. 635 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 636 * |[27] |CMPDIF3 |BPWM Compare Down Count Interrupt Flag 637 * | | |Each bit n controls the corresponding BPWM channel n. 638 * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. 639 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 640 * |[28] |CMPDIF4 |BPWM Compare Down Count Interrupt Flag 641 * | | |Each bit n controls the corresponding BPWM channel n. 642 * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. 643 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 644 * |[29] |CMPDIF5 |BPWM Compare Down Count Interrupt Flag 645 * | | |Each bit n controls the corresponding BPWM channel n. 646 * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. 647 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 648 * @var BPWM_T::EADCTS0 649 * Offset: 0xF8 BPWM Trigger EADC Source Select Register 0 650 * --------------------------------------------------------------------------------------------------- 651 * |Bits |Field |Descriptions 652 * | :----: | :----: | :---- | 653 * |[3:0] |TRGSEL0 |BPWM_CH0 Trigger EADC Source Select 654 * | | |0000 = BPWM_CH0 zero point. 655 * | | |0001 = BPWM_CH0 period point. 656 * | | |0010 = BPWM_CH0 zero or period point. 657 * | | |0011 = BPWM_CH0 up-count CMPDAT point. 658 * | | |0100 = BPWM_CH0 down-count CMPDAT point. 659 * | | |0101 = Reserved. 660 * | | |0110 = Reserved. 661 * | | |0111 = Reserved. 662 * | | |1000 = BPWM_CH1 up-count CMPDAT point. 663 * | | |1001 = BPWM_CH1 down-count CMPDAT point. 664 * | | |Others reserved 665 * |[7] |TRGEN0 |BPWM_CH0 Trigger EADC Enable Bit 666 * |[11:8] |TRGSEL1 |BPWM_CH1 Trigger EADC Source Select 667 * | | |0000 = BPWM_CH0 zero point. 668 * | | |0001 = BPWM_CH0 period point. 669 * | | |0010 = BPWM_CH0 zero or period point. 670 * | | |0011 = BPWM_CH0 up-count CMPDAT point. 671 * | | |0100 = BPWM_CH0 down-count CMPDAT point. 672 * | | |0101 = Reserved. 673 * | | |0110 = Reserved. 674 * | | |0111 = Reserved. 675 * | | |1000 = BPWM_CH1 up-count CMPDAT point. 676 * | | |1001 = BPWM_CH1 down-count CMPDAT point. 677 * | | |Others reserved 678 * |[15] |TRGEN1 |BPWM_CH1 Trigger EADC Enable Bit 679 * |[19:16] |TRGSEL2 |BPWM_CH2 Trigger EADC Source Select 680 * | | |0000 = BPWM_CH2 zero point. 681 * | | |0001 = BPWM_CH2 period point. 682 * | | |0010 = BPWM_CH2 zero or period point. 683 * | | |0011 = BPWM_CH2 up-count CMPDAT point. 684 * | | |0100 = BPWM_CH2 down-count CMPDAT point. 685 * | | |0101 = Reserved. 686 * | | |0110 = Reserved. 687 * | | |0111 = Reserved. 688 * | | |1000 = BPWM_CH3 up-count CMPDAT point. 689 * | | |1001 = BPWM_CH3 down-count CMPDAT point. 690 * | | |Others reserved 691 * |[23] |TRGEN2 |BPWM_CH2 Trigger EADC Enable Bit 692 * |[27:24] |TRGSEL3 |BPWM_CH3 Trigger EADC Source Select 693 * | | |0000 = BPWM_CH2 zero point. 694 * | | |0001 = BPWM_CH2 period point. 695 * | | |0010 = BPWM_CH2 zero or period point. 696 * | | |0011 = BPWM_CH2 up-count CMPDAT point. 697 * | | |0100 = BPWM_CH2 down-count CMPDAT point. 698 * | | |0101 = Reserved. 699 * | | |0110 = Reserved. 700 * | | |0111 = Reserved. 701 * | | |1000 = BPWM_CH3 up-count CMPDAT point. 702 * | | |1001 = BPWM_CH3 down-count CMPDAT point. 703 * | | |Others reserved. 704 * |[31] |TRGEN3 |BPWM_CH3 Trigger EADC Enable Bit 705 * @var BPWM_T::EADCTS1 706 * Offset: 0xFC BPWM Trigger EADC Source Select Register 1 707 * --------------------------------------------------------------------------------------------------- 708 * |Bits |Field |Descriptions 709 * | :----: | :----: | :---- | 710 * |[3:0] |TRGSEL4 |BPWM_CH4 Trigger EADC Source Select 711 * | | |0000 = BPWM_CH4 zero point. 712 * | | |0001 = BPWM_CH4 period point. 713 * | | |0010 = BPWM_CH4 zero or period point. 714 * | | |0011 = BPWM_CH4 up-count CMPDAT point. 715 * | | |0100 = BPWM_CH4 down-count CMPDAT point. 716 * | | |0101 = Reserved. 717 * | | |0110 = Reserved. 718 * | | |0111 = Reserved. 719 * | | |1000 = BPWM_CH5 up-count CMPDAT point. 720 * | | |1001 = BPWM_CH5 down-count CMPDAT point. 721 * | | |Others reserved 722 * |[7] |TRGEN4 |BPWM_CH4 Trigger EADC Enable Bit 723 * |[11:8] |TRGSEL5 |BPWM_CH5 Trigger EADC Source Select 724 * | | |0000 = BPWM_CH4 zero point. 725 * | | |0001 = BPWM_CH4 period point. 726 * | | |0010 = BPWM_CH4 zero or period point. 727 * | | |0011 = BPWM_CH4 up-count CMPDAT point. 728 * | | |0100 = BPWM_CH4 down-count CMPDAT point. 729 * | | |0101 = Reserved. 730 * | | |0110 = Reserved. 731 * | | |0111 = Reserved. 732 * | | |1000 = BPWM_CH5 up-count CMPDAT point. 733 * | | |1001 = BPWM_CH5 down-count CMPDAT point. 734 * | | |Others reserved 735 * |[15] |TRGEN5 |BPWM_CH5 Trigger EADC Enable Bit 736 * @var BPWM_T::SSCTL 737 * Offset: 0x110 BPWM Synchronous Start Control Register 738 * --------------------------------------------------------------------------------------------------- 739 * |Bits |Field |Descriptions 740 * | :----: | :----: | :---- | 741 * |[0] |SSEN0 |BPWM Synchronous Start Function 0 Enable Bit 742 * | | |When synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN). 743 * | | |0 = BPWM synchronous start function Disabled. 744 * | | |1 = BPWM synchronous start function Enabled. 745 * |[9:8] |SSRC |BPWM Synchronous Start Source Select 746 * | | |00 = Synchronous start source come from PWM0. 747 * | | |01 = Synchronous start source come from PWM1. 748 * | | |10 = Synchronous start source come from BPWM0. 749 * | | |11 = Synchronous start source come from BPWM1. 750 * @var BPWM_T::SSTRG 751 * Offset: 0x114 BPWM Synchronous Start Trigger Register 752 * --------------------------------------------------------------------------------------------------- 753 * |Bits |Field |Descriptions 754 * | :----: | :----: | :---- | 755 * |[0] |CNTSEN |BPWM Counter Synchronous Start Enable Bit(Write Only) 756 * | | |BPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time. 757 * | | |Writing this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled. 758 * @var BPWM_T::STATUS 759 * Offset: 0x120 BPWM Status Register 760 * --------------------------------------------------------------------------------------------------- 761 * |Bits |Field |Descriptions 762 * | :----: | :----: | :---- | 763 * |[0] |CNTMAX0 |Time-base Counter 0 Equal to 0xFFFF Latched Status 764 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. 765 * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. 766 * |[16] |EADCTRG0 |EADC Start of Conversion Status 767 * | | |Each bit n controls the corresponding BPWM channel n. 768 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 769 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. 770 * |[17] |EADCTRG1 |EADC Start of Conversion Status 771 * | | |Each bit n controls the corresponding BPWM channel n. 772 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 773 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. 774 * |[18] |EADCTRG2 |EADC Start of Conversion Status 775 * | | |Each bit n controls the corresponding BPWM channel n. 776 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 777 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. 778 * |[19] |EADCTRG3 |EADC Start of Conversion Status 779 * | | |Each bit n controls the corresponding BPWM channel n. 780 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 781 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. 782 * |[20] |EADCTRG4 |EADC Start of Conversion Status 783 * | | |Each bit n controls the corresponding BPWM channel n. 784 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 785 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. 786 * |[21] |EADCTRG5 |EADC Start of Conversion Status 787 * | | |Each bit n controls the corresponding BPWM channel n. 788 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 789 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. 790 * @var BPWM_T::CAPINEN 791 * Offset: 0x200 BPWM Capture Input Enable Register 792 * --------------------------------------------------------------------------------------------------- 793 * |Bits |Field |Descriptions 794 * | :----: | :----: | :---- | 795 * |[0] |CAPINEN0 |Capture Input Enable Bits 796 * | | |Each bit n controls the corresponding BPWM channel n. 797 * | | |0 = BPWM Channel capture input path Disabled 798 * | | |The input of BPWM channel capture function is always regarded as 0. 799 * | | |1 = BPWM Channel capture input path Enabled 800 * | | |The input of BPWM channel capture function comes from correlative multifunction pin. 801 * |[1] |CAPINEN1 |Capture Input Enable Bits 802 * | | |Each bit n controls the corresponding BPWM channel n. 803 * | | |0 = BPWM Channel capture input path Disabled 804 * | | |The input of BPWM channel capture function is always regarded as 0. 805 * | | |1 = BPWM Channel capture input path Enabled 806 * | | |The input of BPWM channel capture function comes from correlative multifunction pin. 807 * |[2] |CAPINEN2 |Capture Input Enable Bits 808 * | | |Each bit n controls the corresponding BPWM channel n. 809 * | | |0 = BPWM Channel capture input path Disabled 810 * | | |The input of BPWM channel capture function is always regarded as 0. 811 * | | |1 = BPWM Channel capture input path Enabled 812 * | | |The input of BPWM channel capture function comes from correlative multifunction pin. 813 * |[3] |CAPINEN3 |Capture Input Enable Bits 814 * | | |Each bit n controls the corresponding BPWM channel n. 815 * | | |0 = BPWM Channel capture input path Disabled 816 * | | |The input of BPWM channel capture function is always regarded as 0. 817 * | | |1 = BPWM Channel capture input path Enabled 818 * | | |The input of BPWM channel capture function comes from correlative multifunction pin. 819 * |[4] |CAPINEN4 |Capture Input Enable Bits 820 * | | |Each bit n controls the corresponding BPWM channel n. 821 * | | |0 = BPWM Channel capture input path Disabled 822 * | | |The input of BPWM channel capture function is always regarded as 0. 823 * | | |1 = BPWM Channel capture input path Enabled 824 * | | |The input of BPWM channel capture function comes from correlative multifunction pin. 825 * |[5] |CAPINEN5 |Capture Input Enable Bits 826 * | | |Each bit n controls the corresponding BPWM channel n. 827 * | | |0 = BPWM Channel capture input path Disabled 828 * | | |The input of BPWM channel capture function is always regarded as 0. 829 * | | |1 = BPWM Channel capture input path Enabled 830 * | | |The input of BPWM channel capture function comes from correlative multifunction pin. 831 * @var BPWM_T::CAPCTL 832 * Offset: 0x204 BPWM Capture Control Register 833 * --------------------------------------------------------------------------------------------------- 834 * |Bits |Field |Descriptions 835 * | :----: | :----: | :---- | 836 * |[0] |CAPEN0 |Capture Function Enable Bits 837 * | | |Each bit n controls the corresponding BPWM channel n. 838 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 839 * | | |1 = Capture function Enabled 840 * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 841 * |[1] |CAPEN1 |Capture Function Enable Bits 842 * | | |Each bit n controls the corresponding BPWM channel n. 843 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 844 * | | |1 = Capture function Enabled 845 * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 846 * |[2] |CAPEN2 |Capture Function Enable Bits 847 * | | |Each bit n controls the corresponding BPWM channel n. 848 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 849 * | | |1 = Capture function Enabled 850 * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 851 * |[3] |CAPEN3 |Capture Function Enable Bits 852 * | | |Each bit n controls the corresponding BPWM channel n. 853 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 854 * | | |1 = Capture function Enabled 855 * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 856 * |[4] |CAPEN4 |Capture Function Enable Bits 857 * | | |Each bit n controls the corresponding BPWM channel n. 858 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 859 * | | |1 = Capture function Enabled 860 * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 861 * |[5] |CAPEN5 |Capture Function Enable Bits 862 * | | |Each bit n controls the corresponding BPWM channel n. 863 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 864 * | | |1 = Capture function Enabled 865 * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 866 * |[8] |CAPINV0 |Capture Inverter Enable Bits 867 * | | |Each bit n controls the corresponding BPWM channel n. 868 * | | |0 = Capture source inverter Disabled. 869 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 870 * |[9] |CAPINV1 |Capture Inverter Enable Bits 871 * | | |Each bit n controls the corresponding BPWM channel n. 872 * | | |0 = Capture source inverter Disabled. 873 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 874 * |[10] |CAPINV2 |Capture Inverter Enable Bits 875 * | | |Each bit n controls the corresponding BPWM channel n. 876 * | | |0 = Capture source inverter Disabled. 877 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 878 * |[11] |CAPINV3 |Capture Inverter Enable Bits 879 * | | |Each bit n controls the corresponding BPWM channel n. 880 * | | |0 = Capture source inverter Disabled. 881 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 882 * |[12] |CAPINV4 |Capture Inverter Enable Bits 883 * | | |Each bit n controls the corresponding BPWM channel n. 884 * | | |0 = Capture source inverter Disabled. 885 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 886 * |[13] |CAPINV5 |Capture Inverter Enable Bits 887 * | | |Each bit n controls the corresponding BPWM channel n. 888 * | | |0 = Capture source inverter Disabled. 889 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 890 * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits 891 * | | |Each bit n controls the corresponding BPWM channel n. 892 * | | |0 = Rising capture reload counter Disabled. 893 * | | |1 = Rising capture reload counter Enabled. 894 * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits 895 * | | |Each bit n controls the corresponding BPWM channel n. 896 * | | |0 = Rising capture reload counter Disabled. 897 * | | |1 = Rising capture reload counter Enabled. 898 * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits 899 * | | |Each bit n controls the corresponding BPWM channel n. 900 * | | |0 = Rising capture reload counter Disabled. 901 * | | |1 = Rising capture reload counter Enabled. 902 * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits 903 * | | |Each bit n controls the corresponding BPWM channel n. 904 * | | |0 = Rising capture reload counter Disabled. 905 * | | |1 = Rising capture reload counter Enabled. 906 * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits 907 * | | |Each bit n controls the corresponding BPWM channel n. 908 * | | |0 = Rising capture reload counter Disabled. 909 * | | |1 = Rising capture reload counter Enabled. 910 * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits 911 * | | |Each bit n controls the corresponding BPWM channel n. 912 * | | |0 = Rising capture reload counter Disabled. 913 * | | |1 = Rising capture reload counter Enabled. 914 * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits 915 * | | |Each bit n controls the corresponding BPWM channel n. 916 * | | |0 = Falling capture reload counter Disabled. 917 * | | |1 = Falling capture reload counter Enabled. 918 * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits 919 * | | |Each bit n controls the corresponding BPWM channel n. 920 * | | |0 = Falling capture reload counter Disabled. 921 * | | |1 = Falling capture reload counter Enabled. 922 * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits 923 * | | |Each bit n controls the corresponding BPWM channel n. 924 * | | |0 = Falling capture reload counter Disabled. 925 * | | |1 = Falling capture reload counter Enabled. 926 * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits 927 * | | |Each bit n controls the corresponding BPWM channel n. 928 * | | |0 = Falling capture reload counter Disabled. 929 * | | |1 = Falling capture reload counter Enabled. 930 * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits 931 * | | |Each bit n controls the corresponding BPWM channel n. 932 * | | |0 = Falling capture reload counter Disabled. 933 * | | |1 = Falling capture reload counter Enabled. 934 * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits 935 * | | |Each bit n controls the corresponding BPWM channel n. 936 * | | |0 = Falling capture reload counter Disabled. 937 * | | |1 = Falling capture reload counter Enabled. 938 * @var BPWM_T::CAPSTS 939 * Offset: 0x208 BPWM Capture Status Register 940 * --------------------------------------------------------------------------------------------------- 941 * |Bits |Field |Descriptions 942 * | :----: | :----: | :---- | 943 * |[0] |CRIFOV0 |Capture Rising Interrupt Flag Overrun Status (Read Only) 944 * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 945 * | | |Each bit n controls the corresponding BPWM channel n. 946 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. 947 * |[1] |CRIFOV1 |Capture Rising Interrupt Flag Overrun Status (Read Only) 948 * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 949 * | | |Each bit n controls the corresponding BPWM channel n. 950 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. 951 * |[2] |CRIFOV2 |Capture Rising Interrupt Flag Overrun Status (Read Only) 952 * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 953 * | | |Each bit n controls the corresponding BPWM channel n. 954 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. 955 * |[3] |CRIFOV3 |Capture Rising Interrupt Flag Overrun Status (Read Only) 956 * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 957 * | | |Each bit n controls the corresponding BPWM channel n. 958 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. 959 * |[4] |CRIFOV4 |Capture Rising Interrupt Flag Overrun Status (Read Only) 960 * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 961 * | | |Each bit n controls the corresponding BPWM channel n. 962 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. 963 * |[5] |CRIFOV5 |Capture Rising Interrupt Flag Overrun Status (Read Only) 964 * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 965 * | | |Each bit n controls the corresponding BPWM channel n. 966 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. 967 * |[8] |CFIFOV0 |Capture Falling Interrupt Flag Overrun Status (Read Only) 968 * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 969 * | | |Each bit n controls the corresponding BPWM channel n. 970 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. 971 * |[9] |CFIFOV1 |Capture Falling Interrupt Flag Overrun Status (Read Only) 972 * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 973 * | | |Each bit n controls the corresponding BPWM channel n. 974 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. 975 * |[10] |CFIFOV2 |Capture Falling Interrupt Flag Overrun Status (Read Only) 976 * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 977 * | | |Each bit n controls the corresponding BPWM channel n. 978 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. 979 * |[11] |CFIFOV3 |Capture Falling Interrupt Flag Overrun Status (Read Only) 980 * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 981 * | | |Each bit n controls the corresponding BPWM channel n. 982 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. 983 * |[12] |CFIFOV4 |Capture Falling Interrupt Flag Overrun Status (Read Only) 984 * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 985 * | | |Each bit n controls the corresponding BPWM channel n. 986 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. 987 * |[13] |CFIFOV5 |Capture Falling Interrupt Flag Overrun Status (Read Only) 988 * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 989 * | | |Each bit n controls the corresponding BPWM channel n. 990 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. 991 * @var BPWM_T::CAPIEN 992 * Offset: 0x250 BPWM Capture Interrupt Enable Register 993 * --------------------------------------------------------------------------------------------------- 994 * |Bits |Field |Descriptions 995 * | :----: | :----: | :---- | 996 * |[5:0] |CAPRIENn |BPWM Capture Rising Latch Interrupt Enable Bits 997 * | | |Each bit n controls the corresponding BPWM channel n. 998 * | | |0 = Capture rising edge latch interrupt Disabled. 999 * | | |1 = Capture rising edge latch interrupt Enabled. 1000 * |[13:8] |CAPFIENn |BPWM Capture Falling Latch Interrupt Enable Bits 1001 * | | |Each bit n controls the corresponding BPWM channel n. 1002 * | | |0 = Capture falling edge latch interrupt Disabled. 1003 * | | |1 = Capture falling edge latch interrupt Enabled. 1004 * @var BPWM_T::CAPIF 1005 * Offset: 0x254 BPWM Capture Interrupt Flag Register 1006 * --------------------------------------------------------------------------------------------------- 1007 * |Bits |Field |Descriptions 1008 * | :----: | :----: | :---- | 1009 * |[0] |CAPRIF0 |BPWM Capture Rising Latch Interrupt Flag 1010 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 1011 * | | |0 = No capture rising latch condition happened. 1012 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 1013 * |[1] |CAPRIF1 |BPWM Capture Rising Latch Interrupt Flag 1014 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 1015 * | | |0 = No capture rising latch condition happened. 1016 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 1017 * |[2] |CAPRIF2 |BPWM Capture Rising Latch Interrupt Flag 1018 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 1019 * | | |0 = No capture rising latch condition happened. 1020 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 1021 * |[3] |CAPRIF3 |BPWM Capture Rising Latch Interrupt Flag 1022 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 1023 * | | |0 = No capture rising latch condition happened. 1024 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 1025 * |[4] |CAPRIF4 |BPWM Capture Rising Latch Interrupt Flag 1026 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 1027 * | | |0 = No capture rising latch condition happened. 1028 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 1029 * |[5] |CAPRIF5 |BPWM Capture Rising Latch Interrupt Flag 1030 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 1031 * | | |0 = No capture rising latch condition happened. 1032 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 1033 * |[8] |CAPFIF0 |BPWM Capture Falling Latch Interrupt Flag 1034 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 1035 * | | |0 = No capture falling latch condition happened. 1036 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 1037 * |[9] |CAPFIF1 |BPWM Capture Falling Latch Interrupt Flag 1038 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 1039 * | | |0 = No capture falling latch condition happened. 1040 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 1041 * |[10] |CAPFIF2 |BPWM Capture Falling Latch Interrupt Flag 1042 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 1043 * | | |0 = No capture falling latch condition happened. 1044 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 1045 * |[11] |CAPFIF3 |BPWM Capture Falling Latch Interrupt Flag 1046 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 1047 * | | |0 = No capture falling latch condition happened. 1048 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 1049 * |[12] |CAPFIF4 |BPWM Capture Falling Latch Interrupt Flag 1050 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 1051 * | | |0 = No capture falling latch condition happened. 1052 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 1053 * |[13] |CAPFIF5 |BPWM Capture Falling Latch Interrupt Flag 1054 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 1055 * | | |0 = No capture falling latch condition happened. 1056 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 1057 * @var BPWM_T::PBUF 1058 * Offset: 0x304 BPWM PERIOD Buffer 1059 * --------------------------------------------------------------------------------------------------- 1060 * |Bits |Field |Descriptions 1061 * | :----: | :----: | :---- | 1062 * |[15:0] |PBUF |BPWM Period Buffer (Read Only) 1063 * | | |Used as PERIOD active register. 1064 * @var BPWM_T::CMPBUF[6] 1065 * Offset: 0x31C BPWM CMPDAT 0~5 Buffer 1066 * --------------------------------------------------------------------------------------------------- 1067 * |Bits |Field |Descriptions 1068 * | :----: | :----: | :---- | 1069 * |[15:0] |CMPBUF |BPWM Comparator Buffer (Read Only) 1070 * | | |Used as CMP active register. 1071 */ 1072 __IO uint32_t CTL0; /*!< [0x0000] BPWM Control Register 0 */ 1073 __IO uint32_t CTL1; /*!< [0x0004] BPWM Control Register 1 */ 1074 /// @cond HIDDEN_SYMBOLS 1075 __I uint32_t RESERVE0[2]; 1076 /// @endcond //HIDDEN_SYMBOLS 1077 __IO uint32_t CLKSRC; /*!< [0x0010] BPWM Clock Source Register */ 1078 __IO uint32_t CLKPSC; /*!< [0x0014] BPWM Clock Prescale Register */ 1079 /// @cond HIDDEN_SYMBOLS 1080 __I uint32_t RESERVE1[2]; 1081 /// @endcond //HIDDEN_SYMBOLS 1082 __IO uint32_t CNTEN; /*!< [0x0020] BPWM Counter Enable Register */ 1083 __IO uint32_t CNTCLR; /*!< [0x0024] BPWM Clear Counter Register */ 1084 /// @cond HIDDEN_SYMBOLS 1085 __I uint32_t RESERVE2[2]; 1086 /// @endcond //HIDDEN_SYMBOLS 1087 __IO uint32_t PERIOD; /*!< [0x0030] BPWM Period Register */ 1088 /// @cond HIDDEN_SYMBOLS 1089 __I uint32_t RESERVE3[7]; 1090 /// @endcond //HIDDEN_SYMBOLS 1091 __IO uint32_t CMPDAT[6]; /*!< [0x0050] BPWM Comparator Register 0~5 */ 1092 /// @cond HIDDEN_SYMBOLS 1093 __I uint32_t RESERVE4[10]; 1094 /// @endcond //HIDDEN_SYMBOLS 1095 __I uint32_t CNT; /*!< [0x0090] BPWM Counter Register */ 1096 /// @cond HIDDEN_SYMBOLS 1097 __I uint32_t RESERVE5[7]; 1098 /// @endcond //HIDDEN_SYMBOLS 1099 __IO uint32_t WGCTL0; /*!< [0x00b0] BPWM Generation Register 0 */ 1100 __IO uint32_t WGCTL1; /*!< [0x00b4] BPWM Generation Register 1 */ 1101 __IO uint32_t MSKEN; /*!< [0x00b8] BPWM Mask Enable Register */ 1102 __IO uint32_t MSK; /*!< [0x00bc] BPWM Mask Data Register */ 1103 /// @cond HIDDEN_SYMBOLS 1104 __I uint32_t RESERVE6[5]; 1105 /// @endcond //HIDDEN_SYMBOLS 1106 __IO uint32_t POLCTL; /*!< [0x00d4] BPWM Pin Polar Inverse Register */ 1107 __IO uint32_t POEN; /*!< [0x00d8] BPWM Output Enable Register */ 1108 /// @cond HIDDEN_SYMBOLS 1109 __I uint32_t RESERVE7[1]; 1110 /// @endcond //HIDDEN_SYMBOLS 1111 __IO uint32_t INTEN; /*!< [0x00e0] BPWM Interrupt Enable Register */ 1112 /// @cond HIDDEN_SYMBOLS 1113 __I uint32_t RESERVE8[1]; 1114 /// @endcond //HIDDEN_SYMBOLS 1115 __IO uint32_t INTSTS; /*!< [0x00e8] BPWM Interrupt Flag Register */ 1116 /// @cond HIDDEN_SYMBOLS 1117 __I uint32_t RESERVE9[3]; 1118 /// @endcond //HIDDEN_SYMBOLS 1119 __IO uint32_t EADCTS0; /*!< [0x00f8] BPWM Trigger EADC Source Select Register 0 */ 1120 __IO uint32_t EADCTS1; /*!< [0x00fc] BPWM Trigger EADC Source Select Register 1 */ 1121 /// @cond HIDDEN_SYMBOLS 1122 __I uint32_t RESERVE10[4]; 1123 /// @endcond //HIDDEN_SYMBOLS 1124 __IO uint32_t SSCTL; /*!< [0x0110] BPWM Synchronous Start Control Register */ 1125 __O uint32_t SSTRG; /*!< [0x0114] BPWM Synchronous Start Trigger Register */ 1126 /// @cond HIDDEN_SYMBOLS 1127 __I uint32_t RESERVE11[2]; 1128 /// @endcond //HIDDEN_SYMBOLS 1129 __IO uint32_t STATUS; /*!< [0x0120] BPWM Status Register */ 1130 /// @cond HIDDEN_SYMBOLS 1131 __I uint32_t RESERVE12[55]; 1132 /// @endcond //HIDDEN_SYMBOLS 1133 __IO uint32_t CAPINEN; /*!< [0x0200] BPWM Capture Input Enable Register */ 1134 __IO uint32_t CAPCTL; /*!< [0x0204] BPWM Capture Control Register */ 1135 __I uint32_t CAPSTS; /*!< [0x0208] BPWM Capture Status Register */ 1136 BCAPDAT_T CAPDAT[6]; /*!< [0x020C] BPWM Rising and Falling Capture Data Register 0~5 */ 1137 /// @cond HIDDEN_SYMBOLS 1138 __I uint32_t RESERVE13[5]; 1139 /// @endcond //HIDDEN_SYMBOLS 1140 __IO uint32_t CAPIEN; /*!< [0x0250] BPWM Capture Interrupt Enable Register */ 1141 __IO uint32_t CAPIF; /*!< [0x0254] BPWM Capture Interrupt Flag Register */ 1142 /// @cond HIDDEN_SYMBOLS 1143 __I uint32_t RESERVE14[43]; 1144 /// @endcond //HIDDEN_SYMBOLS 1145 __I uint32_t PBUF; /*!< [0x0304] BPWM PERIOD Buffer */ 1146 /// @cond HIDDEN_SYMBOLS 1147 __I uint32_t RESERVE15[5]; 1148 /// @endcond //HIDDEN_SYMBOLS 1149 __I uint32_t CMPBUF[6]; /*!< [0x031c] BPWM CMPDAT 0~5 Buffer */ 1150 1151 } BPWM_T; 1152 1153 /** 1154 @addtogroup BPWM_CONST BPWM Bit Field Definition 1155 Constant Definitions for BPWM Controller 1156 @{ */ 1157 1158 #define BPWM_CTL0_CTRLD0_Pos (0) /*!< BPWM_T::CTL0: CTRLD0 Position */ 1159 #define BPWM_CTL0_CTRLD0_Msk (0x1ul << BPWM_CTL0_CTRLD0_Pos) /*!< BPWM_T::CTL0: CTRLD0 Mask */ 1160 1161 #define BPWM_CTL0_CTRLD1_Pos (1) /*!< BPWM_T::CTL0: CTRLD1 Position */ 1162 #define BPWM_CTL0_CTRLD1_Msk (0x1ul << BPWM_CTL0_CTRLD1_Pos) /*!< BPWM_T::CTL0: CTRLD1 Mask */ 1163 1164 #define BPWM_CTL0_CTRLD2_Pos (2) /*!< BPWM_T::CTL0: CTRLD2 Position */ 1165 #define BPWM_CTL0_CTRLD2_Msk (0x1ul << BPWM_CTL0_CTRLD2_Pos) /*!< BPWM_T::CTL0: CTRLD2 Mask */ 1166 1167 #define BPWM_CTL0_CTRLD3_Pos (3) /*!< BPWM_T::CTL0: CTRLD3 Position */ 1168 #define BPWM_CTL0_CTRLD3_Msk (0x1ul << BPWM_CTL0_CTRLD3_Pos) /*!< BPWM_T::CTL0: CTRLD3 Mask */ 1169 1170 #define BPWM_CTL0_CTRLD4_Pos (4) /*!< BPWM_T::CTL0: CTRLD4 Position */ 1171 #define BPWM_CTL0_CTRLD4_Msk (0x1ul << BPWM_CTL0_CTRLD4_Pos) /*!< BPWM_T::CTL0: CTRLD4 Mask */ 1172 1173 #define BPWM_CTL0_CTRLD5_Pos (5) /*!< BPWM_T::CTL0: CTRLD5 Position */ 1174 #define BPWM_CTL0_CTRLD5_Msk (0x1ul << BPWM_CTL0_CTRLD5_Pos) /*!< BPWM_T::CTL0: CTRLD5 Mask */ 1175 1176 #define BPWM_CTL0_IMMLDEN0_Pos (16) /*!< BPWM_T::CTL0: IMMLDEN0 Position */ 1177 #define BPWM_CTL0_IMMLDEN0_Msk (0x1ul << BPWM_CTL0_IMMLDEN0_Pos) /*!< BPWM_T::CTL0: IMMLDEN0 Mask */ 1178 1179 #define BPWM_CTL0_IMMLDEN1_Pos (17) /*!< BPWM_T::CTL0: IMMLDEN1 Position */ 1180 #define BPWM_CTL0_IMMLDEN1_Msk (0x1ul << BPWM_CTL0_IMMLDEN1_Pos) /*!< BPWM_T::CTL0: IMMLDEN1 Mask */ 1181 1182 #define BPWM_CTL0_IMMLDEN2_Pos (18) /*!< BPWM_T::CTL0: IMMLDEN2 Position */ 1183 #define BPWM_CTL0_IMMLDEN2_Msk (0x1ul << BPWM_CTL0_IMMLDEN2_Pos) /*!< BPWM_T::CTL0: IMMLDEN2 Mask */ 1184 1185 #define BPWM_CTL0_IMMLDEN3_Pos (19) /*!< BPWM_T::CTL0: IMMLDEN3 Position */ 1186 #define BPWM_CTL0_IMMLDEN3_Msk (0x1ul << BPWM_CTL0_IMMLDEN3_Pos) /*!< BPWM_T::CTL0: IMMLDEN3 Mask */ 1187 1188 #define BPWM_CTL0_IMMLDEN4_Pos (20) /*!< BPWM_T::CTL0: IMMLDEN4 Position */ 1189 #define BPWM_CTL0_IMMLDEN4_Msk (0x1ul << BPWM_CTL0_IMMLDEN4_Pos) /*!< BPWM_T::CTL0: IMMLDEN4 Mask */ 1190 1191 #define BPWM_CTL0_IMMLDEN5_Pos (21) /*!< BPWM_T::CTL0: IMMLDEN5 Position */ 1192 #define BPWM_CTL0_IMMLDEN5_Msk (0x1ul << BPWM_CTL0_IMMLDEN5_Pos) /*!< BPWM_T::CTL0: IMMLDEN5 Mask */ 1193 1194 #define BPWM_CTL0_DBGHALT_Pos (30) /*!< BPWM_T::CTL0: DBGHALT Position */ 1195 #define BPWM_CTL0_DBGHALT_Msk (0x1ul << BPWM_CTL0_DBGHALT_Pos) /*!< BPWM_T::CTL0: DBGHALT Mask */ 1196 1197 #define BPWM_CTL0_DBGTRIOFF_Pos (31) /*!< BPWM_T::CTL0: DBGTRIOFF Position */ 1198 #define BPWM_CTL0_DBGTRIOFF_Msk (0x1ul << BPWM_CTL0_DBGTRIOFF_Pos) /*!< BPWM_T::CTL0: DBGTRIOFF Mask */ 1199 1200 #define BPWM_CTL1_CNTTYPE0_Pos (0) /*!< BPWM_T::CTL1: CNTTYPE0 Position */ 1201 #define BPWM_CTL1_CNTTYPE0_Msk (0x3ul << BPWM_CTL1_CNTTYPE0_Pos) /*!< BPWM_T::CTL1: CNTTYPE0 Mask */ 1202 1203 #define BPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< BPWM_T::CLKSRC: ECLKSRC0 Position */ 1204 #define BPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << BPWM_CLKSRC_ECLKSRC0_Pos) /*!< BPWM_T::CLKSRC: ECLKSRC0 Mask */ 1205 1206 #define BPWM_CLKPSC_CLKPSC_Pos (0) /*!< BPWM_T::CLKPSC: CLKPSC Position */ 1207 #define BPWM_CLKPSC_CLKPSC_Msk (0xffful << BPWM_CLKPSC_CLKPSC_Pos) /*!< BPWM_T::CLKPSC: CLKPSC Mask */ 1208 1209 #define BPWM_CNTEN_CNTEN0_Pos (0) /*!< BPWM_T::CNTEN: CNTEN0 Position */ 1210 #define BPWM_CNTEN_CNTEN0_Msk (0x1ul << BPWM_CNTEN_CNTEN0_Pos) /*!< BPWM_T::CNTEN: CNTEN0 Mask */ 1211 1212 #define BPWM_CNTCLR_CNTCLR0_Pos (0) /*!< BPWM_T::CNTCLR: CNTCLR0 Position */ 1213 #define BPWM_CNTCLR_CNTCLR0_Msk (0x1ul << BPWM_CNTCLR_CNTCLR0_Pos) /*!< BPWM_T::CNTCLR: CNTCLR0 Mask */ 1214 1215 #define BPWM_PERIOD_PERIOD_Pos (0) /*!< BPWM_T::PERIOD: PERIOD Position */ 1216 #define BPWM_PERIOD_PERIOD_Msk (0xfffful << BPWM_PERIOD_PERIOD_Pos) /*!< BPWM_T::PERIOD: PERIOD Mask */ 1217 1218 #define BPWM_CMPDAT0_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT0: CMPDAT Position */ 1219 #define BPWM_CMPDAT0_CMPDAT_Msk (0xfffful << BPWM_CMPDAT0_CMPDAT_Pos) /*!< BPWM_T::CMPDAT0: CMPDAT Mask */ 1220 1221 #define BPWM_CMPDAT1_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT1: CMPDAT Position */ 1222 #define BPWM_CMPDAT1_CMPDAT_Msk (0xfffful << BPWM_CMPDAT1_CMPDAT_Pos) /*!< BPWM_T::CMPDAT1: CMPDAT Mask */ 1223 1224 #define BPWM_CMPDAT2_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT2: CMPDAT Position */ 1225 #define BPWM_CMPDAT2_CMPDAT_Msk (0xfffful << BPWM_CMPDAT2_CMPDAT_Pos) /*!< BPWM_T::CMPDAT2: CMPDAT Mask */ 1226 1227 #define BPWM_CMPDAT3_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT3: CMPDAT Position */ 1228 #define BPWM_CMPDAT3_CMPDAT_Msk (0xfffful << BPWM_CMPDAT3_CMPDAT_Pos) /*!< BPWM_T::CMPDAT3: CMPDAT Mask */ 1229 1230 #define BPWM_CMPDAT4_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT4: CMPDAT Position */ 1231 #define BPWM_CMPDAT4_CMPDAT_Msk (0xfffful << BPWM_CMPDAT4_CMPDAT_Pos) /*!< BPWM_T::CMPDAT4: CMPDAT Mask */ 1232 1233 #define BPWM_CMPDAT5_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT5: CMPDAT Position */ 1234 #define BPWM_CMPDAT5_CMPDAT_Msk (0xfffful << BPWM_CMPDAT5_CMPDAT_Pos) /*!< BPWM_T::CMPDAT5: CMPDAT Mask */ 1235 1236 #define BPWM_CNT_CNT_Pos (0) /*!< BPWM_T::CNT: CNT Position */ 1237 #define BPWM_CNT_CNT_Msk (0xfffful << BPWM_CNT_CNT_Pos) /*!< BPWM_T::CNT: CNT Mask */ 1238 1239 #define BPWM_CNT_DIRF_Pos (16) /*!< BPWM_T::CNT: DIRF Position */ 1240 #define BPWM_CNT_DIRF_Msk (0x1ul << BPWM_CNT_DIRF_Pos) /*!< BPWM_T::CNT: DIRF Mask */ 1241 1242 #define BPWM_WGCTL0_ZPCTL0_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTL0 Position */ 1243 #define BPWM_WGCTL0_ZPCTL0_Msk (0x3ul << BPWM_WGCTL0_ZPCTL0_Pos) /*!< BPWM_T::WGCTL0: ZPCTL0 Mask */ 1244 1245 #define BPWM_WGCTL0_ZPCTL1_Pos (2) /*!< BPWM_T::WGCTL0: ZPCTL1 Position */ 1246 #define BPWM_WGCTL0_ZPCTL1_Msk (0x3ul << BPWM_WGCTL0_ZPCTL1_Pos) /*!< BPWM_T::WGCTL0: ZPCTL1 Mask */ 1247 1248 #define BPWM_WGCTL0_ZPCTL2_Pos (4) /*!< BPWM_T::WGCTL0: ZPCTL2 Position */ 1249 #define BPWM_WGCTL0_ZPCTL2_Msk (0x3ul << BPWM_WGCTL0_ZPCTL2_Pos) /*!< BPWM_T::WGCTL0: ZPCTL2 Mask */ 1250 1251 #define BPWM_WGCTL0_ZPCTL3_Pos (6) /*!< BPWM_T::WGCTL0: ZPCTL3 Position */ 1252 #define BPWM_WGCTL0_ZPCTL3_Msk (0x3ul << BPWM_WGCTL0_ZPCTL3_Pos) /*!< BPWM_T::WGCTL0: ZPCTL3 Mask */ 1253 1254 #define BPWM_WGCTL0_ZPCTL4_Pos (8) /*!< BPWM_T::WGCTL0: ZPCTL4 Position */ 1255 #define BPWM_WGCTL0_ZPCTL4_Msk (0x3ul << BPWM_WGCTL0_ZPCTL4_Pos) /*!< BPWM_T::WGCTL0: ZPCTL4 Mask */ 1256 1257 #define BPWM_WGCTL0_ZPCTL5_Pos (10) /*!< BPWM_T::WGCTL0: ZPCTL5 Position */ 1258 #define BPWM_WGCTL0_ZPCTL5_Msk (0x3ul << BPWM_WGCTL0_ZPCTL5_Pos) /*!< BPWM_T::WGCTL0: ZPCTL5 Mask */ 1259 1260 #define BPWM_WGCTL0_ZPCTLn_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTLn Position */ 1261 #define BPWM_WGCTL0_ZPCTLn_Msk (0xffful << BPWM_WGCTL0_ZPCTLn_Pos) /*!< BPWM_T::WGCTL0: ZPCTLn Mask */ 1262 1263 #define BPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTL0 Position */ 1264 #define BPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL0_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL0 Mask */ 1265 1266 #define BPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< BPWM_T::WGCTL0: PRDPCTL1 Position */ 1267 #define BPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL1_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL1 Mask */ 1268 1269 #define BPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< BPWM_T::WGCTL0: PRDPCTL2 Position */ 1270 #define BPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL2_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL2 Mask */ 1271 1272 #define BPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< BPWM_T::WGCTL0: PRDPCTL3 Position */ 1273 #define BPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL3_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL3 Mask */ 1274 1275 #define BPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< BPWM_T::WGCTL0: PRDPCTL4 Position */ 1276 #define BPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL4_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL4 Mask */ 1277 1278 #define BPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< BPWM_T::WGCTL0: PRDPCTL5 Position */ 1279 #define BPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL5_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL5 Mask */ 1280 1281 #define BPWM_WGCTL0_PRDPCTLn_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTLn Position */ 1282 #define BPWM_WGCTL0_PRDPCTLn_Msk (0xffful << BPWM_WGCTL0_PRDPCTLn_Pos) /*!< BPWM_T::WGCTL0: PRDPCTLn Mask */ 1283 1284 #define BPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTL0 Position */ 1285 #define BPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL0 Mask */ 1286 1287 #define BPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< BPWM_T::WGCTL1: CMPUCTL1 Position */ 1288 #define BPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL1 Mask */ 1289 1290 #define BPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< BPWM_T::WGCTL1: CMPUCTL2 Position */ 1291 #define BPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL2 Mask */ 1292 1293 #define BPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< BPWM_T::WGCTL1: CMPUCTL3 Position */ 1294 #define BPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL3 Mask */ 1295 1296 #define BPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< BPWM_T::WGCTL1: CMPUCTL4 Position */ 1297 #define BPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL4 Mask */ 1298 1299 #define BPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< BPWM_T::WGCTL1: CMPUCTL5 Position */ 1300 #define BPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL5 Mask */ 1301 1302 #define BPWM_WGCTL1_CMPUCTLn_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTLn Position */ 1303 #define BPWM_WGCTL1_CMPUCTLn_Msk (0xffful << BPWM_WGCTL1_CMPUCTLn_Pos) /*!< BPWM_T::WGCTL1: CMPUCTLn Mask */ 1304 1305 #define BPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTL0 Position */ 1306 #define BPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL0 Mask */ 1307 1308 #define BPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< BPWM_T::WGCTL1: CMPDCTL1 Position */ 1309 #define BPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL1 Mask */ 1310 1311 #define BPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< BPWM_T::WGCTL1: CMPDCTL2 Position */ 1312 #define BPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL2 Mask */ 1313 1314 #define BPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< BPWM_T::WGCTL1: CMPDCTL3 Position */ 1315 #define BPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL3 Mask */ 1316 1317 #define BPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< BPWM_T::WGCTL1: CMPDCTL4 Position */ 1318 #define BPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL4 Mask */ 1319 1320 #define BPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< BPWM_T::WGCTL1: CMPDCTL5 Position */ 1321 #define BPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL5 Mask */ 1322 1323 #define BPWM_WGCTL1_CMPDCTLn_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTLn Position */ 1324 #define BPWM_WGCTL1_CMPDCTLn_Msk (0xffful << BPWM_WGCTL1_CMPDCTLn_Pos) /*!< BPWM_T::WGCTL1: CMPDCTLn Mask */ 1325 1326 #define BPWM_MSKEN_MSKEN0_Pos (0) /*!< BPWM_T::MSKEN: MSKEN0 Position */ 1327 #define BPWM_MSKEN_MSKEN0_Msk (0x1ul << BPWM_MSKEN_MSKEN0_Pos) /*!< BPWM_T::MSKEN: MSKEN0 Mask */ 1328 1329 #define BPWM_MSKEN_MSKEN1_Pos (1) /*!< BPWM_T::MSKEN: MSKEN1 Position */ 1330 #define BPWM_MSKEN_MSKEN1_Msk (0x1ul << BPWM_MSKEN_MSKEN1_Pos) /*!< BPWM_T::MSKEN: MSKEN1 Mask */ 1331 1332 #define BPWM_MSKEN_MSKEN2_Pos (2) /*!< BPWM_T::MSKEN: MSKEN2 Position */ 1333 #define BPWM_MSKEN_MSKEN2_Msk (0x1ul << BPWM_MSKEN_MSKEN2_Pos) /*!< BPWM_T::MSKEN: MSKEN2 Mask */ 1334 1335 #define BPWM_MSKEN_MSKEN3_Pos (3) /*!< BPWM_T::MSKEN: MSKEN3 Position */ 1336 #define BPWM_MSKEN_MSKEN3_Msk (0x1ul << BPWM_MSKEN_MSKEN3_Pos) /*!< BPWM_T::MSKEN: MSKEN3 Mask */ 1337 1338 #define BPWM_MSKEN_MSKEN4_Pos (4) /*!< BPWM_T::MSKEN: MSKEN4 Position */ 1339 #define BPWM_MSKEN_MSKEN4_Msk (0x1ul << BPWM_MSKEN_MSKEN4_Pos) /*!< BPWM_T::MSKEN: MSKEN4 Mask */ 1340 1341 #define BPWM_MSKEN_MSKEN5_Pos (5) /*!< BPWM_T::MSKEN: MSKEN5 Position */ 1342 #define BPWM_MSKEN_MSKEN5_Msk (0x1ul << BPWM_MSKEN_MSKEN5_Pos) /*!< BPWM_T::MSKEN: MSKEN5 Mask */ 1343 1344 #define BPWM_MSKEN_MSKENn_Pos (0) /*!< BPWM_T::MSKEN: MSKENn Position */ 1345 #define BPWM_MSKEN_MSKENn_Msk (0x3ful << BPWM_MSKEN_MSKENn_Pos) /*!< BPWM_T::MSKEN: MSKENn Mask */ 1346 1347 #define BPWM_MSK_MSKDAT0_Pos (0) /*!< BPWM_T::MSK: MSKDAT0 Position */ 1348 #define BPWM_MSK_MSKDAT0_Msk (0x1ul << BPWM_MSK_MSKDAT0_Pos) /*!< BPWM_T::MSK: MSKDAT0 Mask */ 1349 1350 #define BPWM_MSK_MSKDAT1_Pos (1) /*!< BPWM_T::MSK: MSKDAT1 Position */ 1351 #define BPWM_MSK_MSKDAT1_Msk (0x1ul << BPWM_MSK_MSKDAT1_Pos) /*!< BPWM_T::MSK: MSKDAT1 Mask */ 1352 1353 #define BPWM_MSK_MSKDAT2_Pos (2) /*!< BPWM_T::MSK: MSKDAT2 Position */ 1354 #define BPWM_MSK_MSKDAT2_Msk (0x1ul << BPWM_MSK_MSKDAT2_Pos) /*!< BPWM_T::MSK: MSKDAT2 Mask */ 1355 1356 #define BPWM_MSK_MSKDAT3_Pos (3) /*!< BPWM_T::MSK: MSKDAT3 Position */ 1357 #define BPWM_MSK_MSKDAT3_Msk (0x1ul << BPWM_MSK_MSKDAT3_Pos) /*!< BPWM_T::MSK: MSKDAT3 Mask */ 1358 1359 #define BPWM_MSK_MSKDAT4_Pos (4) /*!< BPWM_T::MSK: MSKDAT4 Position */ 1360 #define BPWM_MSK_MSKDAT4_Msk (0x1ul << BPWM_MSK_MSKDAT4_Pos) /*!< BPWM_T::MSK: MSKDAT4 Mask */ 1361 1362 #define BPWM_MSK_MSKDAT5_Pos (5) /*!< BPWM_T::MSK: MSKDAT5 Position */ 1363 #define BPWM_MSK_MSKDAT5_Msk (0x1ul << BPWM_MSK_MSKDAT5_Pos) /*!< BPWM_T::MSK: MSKDAT5 Mask */ 1364 1365 #define BPWM_MSK_MSKDATn_Pos (0) /*!< BPWM_T::MSK: MSKDATn Position */ 1366 #define BPWM_MSK_MSKDATn_Msk (0x3ful << BPWM_MSK_MSKDATn_Pos) /*!< BPWM_T::MSK: MSKDATn Mask */ 1367 1368 #define BPWM_POLCTL_PINV0_Pos (0) /*!< BPWM_T::POLCTL: PINV0 Position */ 1369 #define BPWM_POLCTL_PINV0_Msk (0x1ul << BPWM_POLCTL_PINV0_Pos) /*!< BPWM_T::POLCTL: PINV0 Mask */ 1370 1371 #define BPWM_POLCTL_PINV1_Pos (1) /*!< BPWM_T::POLCTL: PINV1 Position */ 1372 #define BPWM_POLCTL_PINV1_Msk (0x1ul << BPWM_POLCTL_PINV1_Pos) /*!< BPWM_T::POLCTL: PINV1 Mask */ 1373 1374 #define BPWM_POLCTL_PINV2_Pos (2) /*!< BPWM_T::POLCTL: PINV2 Position */ 1375 #define BPWM_POLCTL_PINV2_Msk (0x1ul << BPWM_POLCTL_PINV2_Pos) /*!< BPWM_T::POLCTL: PINV2 Mask */ 1376 1377 #define BPWM_POLCTL_PINV3_Pos (3) /*!< BPWM_T::POLCTL: PINV3 Position */ 1378 #define BPWM_POLCTL_PINV3_Msk (0x1ul << BPWM_POLCTL_PINV3_Pos) /*!< BPWM_T::POLCTL: PINV3 Mask */ 1379 1380 #define BPWM_POLCTL_PINV4_Pos (4) /*!< BPWM_T::POLCTL: PINV4 Position */ 1381 #define BPWM_POLCTL_PINV4_Msk (0x1ul << BPWM_POLCTL_PINV4_Pos) /*!< BPWM_T::POLCTL: PINV4 Mask */ 1382 1383 #define BPWM_POLCTL_PINV5_Pos (5) /*!< BPWM_T::POLCTL: PINV5 Position */ 1384 #define BPWM_POLCTL_PINV5_Msk (0x1ul << BPWM_POLCTL_PINV5_Pos) /*!< BPWM_T::POLCTL: PINV5 Mask */ 1385 1386 #define BPWM_POLCTL_PINVn_Pos (0) /*!< BPWM_T::POLCTL: PINVn Position */ 1387 #define BPWM_POLCTL_PINVn_Msk (0x3ful << BPWM_POLCTL_PINVn_Pos) /*!< BPWM_T::POLCTL: PINVn Mask */ 1388 1389 #define BPWM_POEN_POEN0_Pos (0) /*!< BPWM_T::POEN: POEN0 Position */ 1390 #define BPWM_POEN_POEN0_Msk (0x1ul << BPWM_POEN_POEN0_Pos) /*!< BPWM_T::POEN: POEN0 Mask */ 1391 1392 #define BPWM_POEN_POEN1_Pos (1) /*!< BPWM_T::POEN: POEN1 Position */ 1393 #define BPWM_POEN_POEN1_Msk (0x1ul << BPWM_POEN_POEN1_Pos) /*!< BPWM_T::POEN: POEN1 Mask */ 1394 1395 #define BPWM_POEN_POEN2_Pos (2) /*!< BPWM_T::POEN: POEN2 Position */ 1396 #define BPWM_POEN_POEN2_Msk (0x1ul << BPWM_POEN_POEN2_Pos) /*!< BPWM_T::POEN: POEN2 Mask */ 1397 1398 #define BPWM_POEN_POEN3_Pos (3) /*!< BPWM_T::POEN: POEN3 Position */ 1399 #define BPWM_POEN_POEN3_Msk (0x1ul << BPWM_POEN_POEN3_Pos) /*!< BPWM_T::POEN: POEN3 Mask */ 1400 1401 #define BPWM_POEN_POEN4_Pos (4) /*!< BPWM_T::POEN: POEN4 Position */ 1402 #define BPWM_POEN_POEN4_Msk (0x1ul << BPWM_POEN_POEN4_Pos) /*!< BPWM_T::POEN: POEN4 Mask */ 1403 1404 #define BPWM_POEN_POEN5_Pos (5) /*!< BPWM_T::POEN: POEN5 Position */ 1405 #define BPWM_POEN_POEN5_Msk (0x1ul << BPWM_POEN_POEN5_Pos) /*!< BPWM_T::POEN: POEN5 Mask */ 1406 1407 #define BPWM_POEN_POENn_Pos (0) /*!< BPWM_T::POEN: POENn Position */ 1408 #define BPWM_POEN_POENn_Msk (0x3ful << BPWM_POEN_POENn_Pos) /*!< BPWM_T::POEN: POENn Mask */ 1409 1410 #define BPWM_INTEN_ZIEN0_Pos (0) /*!< BPWM_T::INTEN: ZIEN0 Position */ 1411 #define BPWM_INTEN_ZIEN0_Msk (0x1ul << BPWM_INTEN_ZIEN0_Pos) /*!< BPWM_T::INTEN: ZIEN0 Mask */ 1412 1413 #define BPWM_INTEN_PIEN0_Pos (8) /*!< BPWM_T::INTEN: PIEN0 Position */ 1414 #define BPWM_INTEN_PIEN0_Msk (0x1ul << BPWM_INTEN_PIEN0_Pos) /*!< BPWM_T::INTEN: PIEN0 Mask */ 1415 1416 #define BPWM_INTEN_CMPUIEN0_Pos (16) /*!< BPWM_T::INTEN: CMPUIEN0 Position */ 1417 #define BPWM_INTEN_CMPUIEN0_Msk (0x1ul << BPWM_INTEN_CMPUIEN0_Pos) /*!< BPWM_T::INTEN: CMPUIEN0 Mask */ 1418 1419 #define BPWM_INTEN_CMPUIEN1_Pos (17) /*!< BPWM_T::INTEN: CMPUIEN1 Position */ 1420 #define BPWM_INTEN_CMPUIEN1_Msk (0x1ul << BPWM_INTEN_CMPUIEN1_Pos) /*!< BPWM_T::INTEN: CMPUIEN1 Mask */ 1421 1422 #define BPWM_INTEN_CMPUIEN2_Pos (18) /*!< BPWM_T::INTEN: CMPUIEN2 Position */ 1423 #define BPWM_INTEN_CMPUIEN2_Msk (0x1ul << BPWM_INTEN_CMPUIEN2_Pos) /*!< BPWM_T::INTEN: CMPUIEN2 Mask */ 1424 1425 #define BPWM_INTEN_CMPUIEN3_Pos (19) /*!< BPWM_T::INTEN: CMPUIEN3 Position */ 1426 #define BPWM_INTEN_CMPUIEN3_Msk (0x1ul << BPWM_INTEN_CMPUIEN3_Pos) /*!< BPWM_T::INTEN: CMPUIEN3 Mask */ 1427 1428 #define BPWM_INTEN_CMPUIEN4_Pos (20) /*!< BPWM_T::INTEN: CMPUIEN4 Position */ 1429 #define BPWM_INTEN_CMPUIEN4_Msk (0x1ul << BPWM_INTEN_CMPUIEN4_Pos) /*!< BPWM_T::INTEN: CMPUIEN4 Mask */ 1430 1431 #define BPWM_INTEN_CMPUIEN5_Pos (21) /*!< BPWM_T::INTEN: CMPUIEN5 Position */ 1432 #define BPWM_INTEN_CMPUIEN5_Msk (0x1ul << BPWM_INTEN_CMPUIEN5_Pos) /*!< BPWM_T::INTEN: CMPUIEN5 Mask */ 1433 1434 #define BPWM_INTEN_CMPUIENn_Pos (16) /*!< BPWM_T::INTEN: CMPUIENn Position */ 1435 #define BPWM_INTEN_CMPUIENn_Msk (0x3ful << BPWM_INTEN_CMPUIENn_Pos) /*!< BPWM_T::INTEN: CMPUIENn Mask */ 1436 1437 #define BPWM_INTEN_CMPDIEN0_Pos (24) /*!< BPWM_T::INTEN: CMPDIEN0 Position */ 1438 #define BPWM_INTEN_CMPDIEN0_Msk (0x1ul << BPWM_INTEN_CMPDIEN0_Pos) /*!< BPWM_T::INTEN: CMPDIEN0 Mask */ 1439 1440 #define BPWM_INTEN_CMPDIEN1_Pos (25) /*!< BPWM_T::INTEN: CMPDIEN1 Position */ 1441 #define BPWM_INTEN_CMPDIEN1_Msk (0x1ul << BPWM_INTEN_CMPDIEN1_Pos) /*!< BPWM_T::INTEN: CMPDIEN1 Mask */ 1442 1443 #define BPWM_INTEN_CMPDIEN2_Pos (26) /*!< BPWM_T::INTEN: CMPDIEN2 Position */ 1444 #define BPWM_INTEN_CMPDIEN2_Msk (0x1ul << BPWM_INTEN_CMPDIEN2_Pos) /*!< BPWM_T::INTEN: CMPDIEN2 Mask */ 1445 1446 #define BPWM_INTEN_CMPDIEN3_Pos (27) /*!< BPWM_T::INTEN: CMPDIEN3 Position */ 1447 #define BPWM_INTEN_CMPDIEN3_Msk (0x1ul << BPWM_INTEN_CMPDIEN3_Pos) /*!< BPWM_T::INTEN: CMPDIEN3 Mask */ 1448 1449 #define BPWM_INTEN_CMPDIEN4_Pos (28) /*!< BPWM_T::INTEN: CMPDIEN4 Position */ 1450 #define BPWM_INTEN_CMPDIEN4_Msk (0x1ul << BPWM_INTEN_CMPDIEN4_Pos) /*!< BPWM_T::INTEN: CMPDIEN4 Mask */ 1451 1452 #define BPWM_INTEN_CMPDIEN5_Pos (29) /*!< BPWM_T::INTEN: CMPDIEN5 Position */ 1453 #define BPWM_INTEN_CMPDIEN5_Msk (0x1ul << BPWM_INTEN_CMPDIEN5_Pos) /*!< BPWM_T::INTEN: CMPDIEN5 Mask */ 1454 1455 #define BPWM_INTEN_CMPDIENn_Pos (24) /*!< BPWM_T::INTEN: CMPDIENn Position */ 1456 #define BPWM_INTEN_CMPDIENn_Msk (0x3ful << BPWM_INTEN_CMPDIENn_Pos) /*!< BPWM_T::INTEN: CMPDIENn Mask */ 1457 1458 #define BPWM_INTSTS_ZIF0_Pos (0) /*!< BPWM_T::INTSTS: ZIF0 Position */ 1459 #define BPWM_INTSTS_ZIF0_Msk (0x1ul << BPWM_INTSTS_ZIF0_Pos) /*!< BPWM_T::INTSTS: ZIF0 Mask */ 1460 1461 #define BPWM_INTSTS_PIF0_Pos (8) /*!< BPWM_T::INTSTS: PIF0 Position */ 1462 #define BPWM_INTSTS_PIF0_Msk (0x1ul << BPWM_INTSTS_PIF0_Pos) /*!< BPWM_T::INTSTS: PIF0 Mask */ 1463 1464 #define BPWM_INTSTS_CMPUIF0_Pos (16) /*!< BPWM_T::INTSTS: CMPUIF0 Position */ 1465 #define BPWM_INTSTS_CMPUIF0_Msk (0x1ul << BPWM_INTSTS_CMPUIF0_Pos) /*!< BPWM_T::INTSTS: CMPUIF0 Mask */ 1466 1467 #define BPWM_INTSTS_CMPUIF1_Pos (17) /*!< BPWM_T::INTSTS: CMPUIF1 Position */ 1468 #define BPWM_INTSTS_CMPUIF1_Msk (0x1ul << BPWM_INTSTS_CMPUIF1_Pos) /*!< BPWM_T::INTSTS: CMPUIF1 Mask */ 1469 1470 #define BPWM_INTSTS_CMPUIF2_Pos (18) /*!< BPWM_T::INTSTS: CMPUIF2 Position */ 1471 #define BPWM_INTSTS_CMPUIF2_Msk (0x1ul << BPWM_INTSTS_CMPUIF2_Pos) /*!< BPWM_T::INTSTS: CMPUIF2 Mask */ 1472 1473 #define BPWM_INTSTS_CMPUIF3_Pos (19) /*!< BPWM_T::INTSTS: CMPUIF3 Position */ 1474 #define BPWM_INTSTS_CMPUIF3_Msk (0x1ul << BPWM_INTSTS_CMPUIF3_Pos) /*!< BPWM_T::INTSTS: CMPUIF3 Mask */ 1475 1476 #define BPWM_INTSTS_CMPUIF4_Pos (20) /*!< BPWM_T::INTSTS: CMPUIF4 Position */ 1477 #define BPWM_INTSTS_CMPUIF4_Msk (0x1ul << BPWM_INTSTS_CMPUIF4_Pos) /*!< BPWM_T::INTSTS: CMPUIF4 Mask */ 1478 1479 #define BPWM_INTSTS_CMPUIF5_Pos (21) /*!< BPWM_T::INTSTS: CMPUIF5 Position */ 1480 #define BPWM_INTSTS_CMPUIF5_Msk (0x1ul << BPWM_INTSTS_CMPUIF5_Pos) /*!< BPWM_T::INTSTS: CMPUIF5 Mask */ 1481 1482 #define BPWM_INTSTS_CMPUIFn_Pos (16) /*!< BPWM_T::INTSTS: CMPUIFn Position */ 1483 #define BPWM_INTSTS_CMPUIFn_Msk (0x3ful << BPWM_INTSTS_CMPUIFn_Pos) /*!< BPWM_T::INTSTS: CMPUIFn Mask */ 1484 1485 #define BPWM_INTSTS_CMPDIF0_Pos (24) /*!< BPWM_T::INTSTS: CMPDIF0 Position */ 1486 #define BPWM_INTSTS_CMPDIF0_Msk (0x1ul << BPWM_INTSTS_CMPDIF0_Pos) /*!< BPWM_T::INTSTS: CMPDIF0 Mask */ 1487 1488 #define BPWM_INTSTS_CMPDIF1_Pos (25) /*!< BPWM_T::INTSTS: CMPDIF1 Position */ 1489 #define BPWM_INTSTS_CMPDIF1_Msk (0x1ul << BPWM_INTSTS_CMPDIF1_Pos) /*!< BPWM_T::INTSTS: CMPDIF1 Mask */ 1490 1491 #define BPWM_INTSTS_CMPDIF2_Pos (26) /*!< BPWM_T::INTSTS: CMPDIF2 Position */ 1492 #define BPWM_INTSTS_CMPDIF2_Msk (0x1ul << BPWM_INTSTS_CMPDIF2_Pos) /*!< BPWM_T::INTSTS: CMPDIF2 Mask */ 1493 1494 #define BPWM_INTSTS_CMPDIF3_Pos (27) /*!< BPWM_T::INTSTS: CMPDIF3 Position */ 1495 #define BPWM_INTSTS_CMPDIF3_Msk (0x1ul << BPWM_INTSTS_CMPDIF3_Pos) /*!< BPWM_T::INTSTS: CMPDIF3 Mask */ 1496 1497 #define BPWM_INTSTS_CMPDIF4_Pos (28) /*!< BPWM_T::INTSTS: CMPDIF4 Position */ 1498 #define BPWM_INTSTS_CMPDIF4_Msk (0x1ul << BPWM_INTSTS_CMPDIF4_Pos) /*!< BPWM_T::INTSTS: CMPDIF4 Mask */ 1499 1500 #define BPWM_INTSTS_CMPDIF5_Pos (29) /*!< BPWM_T::INTSTS: CMPDIF5 Position */ 1501 #define BPWM_INTSTS_CMPDIF5_Msk (0x1ul << BPWM_INTSTS_CMPDIF5_Pos) /*!< BPWM_T::INTSTS: CMPDIF5 Mask */ 1502 1503 #define BPWM_INTSTS_CMPDIFn_Pos (24) /*!< BPWM_T::INTSTS: CMPDIFn Position */ 1504 #define BPWM_INTSTS_CMPDIFn_Msk (0x3ful << BPWM_INTSTS_CMPDIFn_Pos) /*!< BPWM_T::INTSTS: CMPDIFn Mask */ 1505 1506 #define BPWM_EADCTS0_TRGSEL0_Pos (0) /*!< BPWM_T::EADCTS0: TRGSEL0 Position */ 1507 #define BPWM_EADCTS0_TRGSEL0_Msk (0xful << BPWM_EADCTS0_TRGSEL0_Pos) /*!< BPWM_T::EADCTS0: TRGSEL0 Mask */ 1508 1509 #define BPWM_EADCTS0_TRGEN0_Pos (7) /*!< BPWM_T::EADCTS0: TRGEN0 Position */ 1510 #define BPWM_EADCTS0_TRGEN0_Msk (0x1ul << BPWM_EADCTS0_TRGEN0_Pos) /*!< BPWM_T::EADCTS0: TRGEN0 Mask */ 1511 1512 #define BPWM_EADCTS0_TRGSEL1_Pos (8) /*!< BPWM_T::EADCTS0: TRGSEL1 Position */ 1513 #define BPWM_EADCTS0_TRGSEL1_Msk (0xful << BPWM_EADCTS0_TRGSEL1_Pos) /*!< BPWM_T::EADCTS0: TRGSEL1 Mask */ 1514 1515 #define BPWM_EADCTS0_TRGEN1_Pos (15) /*!< BPWM_T::EADCTS0: TRGEN1 Position */ 1516 #define BPWM_EADCTS0_TRGEN1_Msk (0x1ul << BPWM_EADCTS0_TRGEN1_Pos) /*!< BPWM_T::EADCTS0: TRGEN1 Mask */ 1517 1518 #define BPWM_EADCTS0_TRGSEL2_Pos (16) /*!< BPWM_T::EADCTS0: TRGSEL2 Position */ 1519 #define BPWM_EADCTS0_TRGSEL2_Msk (0xful << BPWM_EADCTS0_TRGSEL2_Pos) /*!< BPWM_T::EADCTS0: TRGSEL2 Mask */ 1520 1521 #define BPWM_EADCTS0_TRGEN2_Pos (23) /*!< BPWM_T::EADCTS0: TRGEN2 Position */ 1522 #define BPWM_EADCTS0_TRGEN2_Msk (0x1ul << BPWM_EADCTS0_TRGEN2_Pos) /*!< BPWM_T::EADCTS0: TRGEN2 Mask */ 1523 1524 #define BPWM_EADCTS0_TRGSEL3_Pos (24) /*!< BPWM_T::EADCTS0: TRGSEL3 Position */ 1525 #define BPWM_EADCTS0_TRGSEL3_Msk (0xful << BPWM_EADCTS0_TRGSEL3_Pos) /*!< BPWM_T::EADCTS0: TRGSEL3 Mask */ 1526 1527 #define BPWM_EADCTS0_TRGEN3_Pos (31) /*!< BPWM_T::EADCTS0: TRGEN3 Position */ 1528 #define BPWM_EADCTS0_TRGEN3_Msk (0x1ul << BPWM_EADCTS0_TRGEN3_Pos) /*!< BPWM_T::EADCTS0: TRGEN3 Mask */ 1529 1530 #define BPWM_EADCTS1_TRGSEL4_Pos (0) /*!< BPWM_T::EADCTS1: TRGSEL4 Position */ 1531 #define BPWM_EADCTS1_TRGSEL4_Msk (0xful << BPWM_EADCTS1_TRGSEL4_Pos) /*!< BPWM_T::EADCTS1: TRGSEL4 Mask */ 1532 1533 #define BPWM_EADCTS1_TRGEN4_Pos (7) /*!< BPWM_T::EADCTS1: TRGEN4 Position */ 1534 #define BPWM_EADCTS1_TRGEN4_Msk (0x1ul << BPWM_EADCTS1_TRGEN4_Pos) /*!< BPWM_T::EADCTS1: TRGEN4 Mask */ 1535 1536 #define BPWM_EADCTS1_TRGSEL5_Pos (8) /*!< BPWM_T::EADCTS1: TRGSEL5 Position */ 1537 #define BPWM_EADCTS1_TRGSEL5_Msk (0xful << BPWM_EADCTS1_TRGSEL5_Pos) /*!< BPWM_T::EADCTS1: TRGSEL5 Mask */ 1538 1539 #define BPWM_EADCTS1_TRGEN5_Pos (15) /*!< BPWM_T::EADCTS1: TRGEN5 Position */ 1540 #define BPWM_EADCTS1_TRGEN5_Msk (0x1ul << BPWM_EADCTS1_TRGEN5_Pos) /*!< BPWM_T::EADCTS1: TRGEN5 Mask */ 1541 1542 #define BPWM_SSCTL_SSEN0_Pos (0) /*!< BPWM_T::SSCTL: SSEN0 Position */ 1543 #define BPWM_SSCTL_SSEN0_Msk (0x1ul << BPWM_SSCTL_SSEN0_Pos) /*!< BPWM_T::SSCTL: SSEN0 Mask */ 1544 1545 #define BPWM_SSCTL_SSRC_Pos (8) /*!< BPWM_T::SSCTL: SSRC Position */ 1546 #define BPWM_SSCTL_SSRC_Msk (0x3ul << BPWM_SSCTL_SSRC_Pos) /*!< BPWM_T::SSCTL: SSRC Mask */ 1547 1548 #define BPWM_SSTRG_CNTSEN_Pos (0) /*!< BPWM_T::SSTRG: CNTSEN Position */ 1549 #define BPWM_SSTRG_CNTSEN_Msk (0x1ul << BPWM_SSTRG_CNTSEN_Pos) /*!< BPWM_T::SSTRG: CNTSEN Mask */ 1550 1551 #define BPWM_STATUS_CNTMAX0_Pos (0) /*!< BPWM_T::STATUS: CNTMAX0 Position */ 1552 #define BPWM_STATUS_CNTMAX0_Msk (0x1ul << BPWM_STATUS_CNTMAX0_Pos) /*!< BPWM_T::STATUS: CNTMAX0 Mask */ 1553 1554 #define BPWM_STATUS_EADCTRG0_Pos (16) /*!< BPWM_T::STATUS: EADCTRG0 Position */ 1555 #define BPWM_STATUS_EADCTRG0_Msk (0x1ul << BPWM_STATUS_EADCTRG0_Pos) /*!< BPWM_T::STATUS: EADCTRG0 Mask */ 1556 1557 #define BPWM_STATUS_EADCTRG1_Pos (17) /*!< BPWM_T::STATUS: EADCTRG1 Position */ 1558 #define BPWM_STATUS_EADCTRG1_Msk (0x1ul << BPWM_STATUS_EADCTRG1_Pos) /*!< BPWM_T::STATUS: EADCTRG1 Mask */ 1559 1560 #define BPWM_STATUS_EADCTRG2_Pos (18) /*!< BPWM_T::STATUS: EADCTRG2 Position */ 1561 #define BPWM_STATUS_EADCTRG2_Msk (0x1ul << BPWM_STATUS_EADCTRG2_Pos) /*!< BPWM_T::STATUS: EADCTRG2 Mask */ 1562 1563 #define BPWM_STATUS_EADCTRG3_Pos (19) /*!< BPWM_T::STATUS: EADCTRG3 Position */ 1564 #define BPWM_STATUS_EADCTRG3_Msk (0x1ul << BPWM_STATUS_EADCTRG3_Pos) /*!< BPWM_T::STATUS: EADCTRG3 Mask */ 1565 1566 #define BPWM_STATUS_EADCTRG4_Pos (20) /*!< BPWM_T::STATUS: EADCTRG4 Position */ 1567 #define BPWM_STATUS_EADCTRG4_Msk (0x1ul << BPWM_STATUS_EADCTRG4_Pos) /*!< BPWM_T::STATUS: EADCTRG4 Mask */ 1568 1569 #define BPWM_STATUS_EADCTRG5_Pos (21) /*!< BPWM_T::STATUS: EADCTRG5 Position */ 1570 #define BPWM_STATUS_EADCTRG5_Msk (0x1ul << BPWM_STATUS_EADCTRG5_Pos) /*!< BPWM_T::STATUS: EADCTRG5 Mask */ 1571 1572 #define BPWM_STATUS_EADCTRGn_Pos (16) /*!< BPWM_T::STATUS: EADCTRGn Position */ 1573 #define BPWM_STATUS_EADCTRGn_Msk (0x3ful << BPWM_STATUS_EADCTRGn_Pos) /*!< BPWM_T::STATUS: EADCTRGn Mask */ 1574 1575 #define BPWM_CAPINEN_CAPINEN0_Pos (0) /*!< BPWM_T::CAPINEN: CAPINEN0 Position */ 1576 #define BPWM_CAPINEN_CAPINEN0_Msk (0x1ul << BPWM_CAPINEN_CAPINEN0_Pos) /*!< BPWM_T::CAPINEN: CAPINEN0 Mask */ 1577 1578 #define BPWM_CAPINEN_CAPINEN1_Pos (1) /*!< BPWM_T::CAPINEN: CAPINEN1 Position */ 1579 #define BPWM_CAPINEN_CAPINEN1_Msk (0x1ul << BPWM_CAPINEN_CAPINEN1_Pos) /*!< BPWM_T::CAPINEN: CAPINEN1 Mask */ 1580 1581 #define BPWM_CAPINEN_CAPINEN2_Pos (2) /*!< BPWM_T::CAPINEN: CAPINEN2 Position */ 1582 #define BPWM_CAPINEN_CAPINEN2_Msk (0x1ul << BPWM_CAPINEN_CAPINEN2_Pos) /*!< BPWM_T::CAPINEN: CAPINEN2 Mask */ 1583 1584 #define BPWM_CAPINEN_CAPINEN3_Pos (3) /*!< BPWM_T::CAPINEN: CAPINEN3 Position */ 1585 #define BPWM_CAPINEN_CAPINEN3_Msk (0x1ul << BPWM_CAPINEN_CAPINEN3_Pos) /*!< BPWM_T::CAPINEN: CAPINEN3 Mask */ 1586 1587 #define BPWM_CAPINEN_CAPINEN4_Pos (4) /*!< BPWM_T::CAPINEN: CAPINEN4 Position */ 1588 #define BPWM_CAPINEN_CAPINEN4_Msk (0x1ul << BPWM_CAPINEN_CAPINEN4_Pos) /*!< BPWM_T::CAPINEN: CAPINEN4 Mask */ 1589 1590 #define BPWM_CAPINEN_CAPINEN5_Pos (5) /*!< BPWM_T::CAPINEN: CAPINEN5 Position */ 1591 #define BPWM_CAPINEN_CAPINEN5_Msk (0x1ul << BPWM_CAPINEN_CAPINEN5_Pos) /*!< BPWM_T::CAPINEN: CAPINEN5 Mask */ 1592 1593 #define BPWM_CAPINEN_CAPINENn_Pos (0) /*!< BPWM_T::CAPINEN: CAPINENn Position */ 1594 #define BPWM_CAPINEN_CAPINENn_Msk (0x3ful << BPWM_CAPINEN_CAPINENn_Pos) /*!< BPWM_T::CAPINEN: CAPINENn Mask */ 1595 1596 #define BPWM_CAPCTL_CAPEN0_Pos (0) /*!< BPWM_T::CAPCTL: CAPEN0 Position */ 1597 #define BPWM_CAPCTL_CAPEN0_Msk (0x1ul << BPWM_CAPCTL_CAPEN0_Pos) /*!< BPWM_T::CAPCTL: CAPEN0 Mask */ 1598 1599 #define BPWM_CAPCTL_CAPEN1_Pos (1) /*!< BPWM_T::CAPCTL: CAPEN1 Position */ 1600 #define BPWM_CAPCTL_CAPEN1_Msk (0x1ul << BPWM_CAPCTL_CAPEN1_Pos) /*!< BPWM_T::CAPCTL: CAPEN1 Mask */ 1601 1602 #define BPWM_CAPCTL_CAPEN2_Pos (2) /*!< BPWM_T::CAPCTL: CAPEN2 Position */ 1603 #define BPWM_CAPCTL_CAPEN2_Msk (0x1ul << BPWM_CAPCTL_CAPEN2_Pos) /*!< BPWM_T::CAPCTL: CAPEN2 Mask */ 1604 1605 #define BPWM_CAPCTL_CAPEN3_Pos (3) /*!< BPWM_T::CAPCTL: CAPEN3 Position */ 1606 #define BPWM_CAPCTL_CAPEN3_Msk (0x1ul << BPWM_CAPCTL_CAPEN3_Pos) /*!< BPWM_T::CAPCTL: CAPEN3 Mask */ 1607 1608 #define BPWM_CAPCTL_CAPEN4_Pos (4) /*!< BPWM_T::CAPCTL: CAPEN4 Position */ 1609 #define BPWM_CAPCTL_CAPEN4_Msk (0x1ul << BPWM_CAPCTL_CAPEN4_Pos) /*!< BPWM_T::CAPCTL: CAPEN4 Mask */ 1610 1611 #define BPWM_CAPCTL_CAPEN5_Pos (5) /*!< BPWM_T::CAPCTL: CAPEN5 Position */ 1612 #define BPWM_CAPCTL_CAPEN5_Msk (0x1ul << BPWM_CAPCTL_CAPEN5_Pos) /*!< BPWM_T::CAPCTL: CAPEN5 Mask */ 1613 1614 #define BPWM_CAPCTL_CAPENn_Pos (0) /*!< BPWM_T::CAPCTL: CAPENn Position */ 1615 #define BPWM_CAPCTL_CAPENn_Msk (0x3ful << BPWM_CAPCTL_CAPENn_Pos) /*!< BPWM_T::CAPCTL: CAPENn Mask */ 1616 1617 #define BPWM_CAPCTL_CAPINV0_Pos (8) /*!< BPWM_T::CAPCTL: CAPINV0 Position */ 1618 #define BPWM_CAPCTL_CAPINV0_Msk (0x1ul << BPWM_CAPCTL_CAPINV0_Pos) /*!< BPWM_T::CAPCTL: CAPINV0 Mask */ 1619 1620 #define BPWM_CAPCTL_CAPINV1_Pos (9) /*!< BPWM_T::CAPCTL: CAPINV1 Position */ 1621 #define BPWM_CAPCTL_CAPINV1_Msk (0x1ul << BPWM_CAPCTL_CAPINV1_Pos) /*!< BPWM_T::CAPCTL: CAPINV1 Mask */ 1622 1623 #define BPWM_CAPCTL_CAPINV2_Pos (10) /*!< BPWM_T::CAPCTL: CAPINV2 Position */ 1624 #define BPWM_CAPCTL_CAPINV2_Msk (0x1ul << BPWM_CAPCTL_CAPINV2_Pos) /*!< BPWM_T::CAPCTL: CAPINV2 Mask */ 1625 1626 #define BPWM_CAPCTL_CAPINV3_Pos (11) /*!< BPWM_T::CAPCTL: CAPINV3 Position */ 1627 #define BPWM_CAPCTL_CAPINV3_Msk (0x1ul << BPWM_CAPCTL_CAPINV3_Pos) /*!< BPWM_T::CAPCTL: CAPINV3 Mask */ 1628 1629 #define BPWM_CAPCTL_CAPINV4_Pos (12) /*!< BPWM_T::CAPCTL: CAPINV4 Position */ 1630 #define BPWM_CAPCTL_CAPINV4_Msk (0x1ul << BPWM_CAPCTL_CAPINV4_Pos) /*!< BPWM_T::CAPCTL: CAPINV4 Mask */ 1631 1632 #define BPWM_CAPCTL_CAPINV5_Pos (13) /*!< BPWM_T::CAPCTL: CAPINV5 Position */ 1633 #define BPWM_CAPCTL_CAPINV5_Msk (0x1ul << BPWM_CAPCTL_CAPINV5_Pos) /*!< BPWM_T::CAPCTL: CAPINV5 Mask */ 1634 1635 #define BPWM_CAPCTL_CAPINVn_Pos (8) /*!< BPWM_T::CAPCTL: CAPINVn Position */ 1636 #define BPWM_CAPCTL_CAPINVn_Msk (0x3ful << BPWM_CAPCTL_CAPINVn_Pos) /*!< BPWM_T::CAPCTL: CAPINVn Mask */ 1637 1638 #define BPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDEN0 Position */ 1639 #define BPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN0 Mask */ 1640 1641 #define BPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< BPWM_T::CAPCTL: RCRLDEN1 Position */ 1642 #define BPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN1 Mask */ 1643 1644 #define BPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< BPWM_T::CAPCTL: RCRLDEN2 Position */ 1645 #define BPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN2 Mask */ 1646 1647 #define BPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< BPWM_T::CAPCTL: RCRLDEN3 Position */ 1648 #define BPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN3 Mask */ 1649 1650 #define BPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< BPWM_T::CAPCTL: RCRLDEN4 Position */ 1651 #define BPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN4 Mask */ 1652 1653 #define BPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< BPWM_T::CAPCTL: RCRLDEN5 Position */ 1654 #define BPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN5 Mask */ 1655 1656 #define BPWM_CAPCTL_RCRLDENn_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDENn Position */ 1657 #define BPWM_CAPCTL_RCRLDENn_Msk (0x3ful << BPWM_CAPCTL_RCRLDENn_Pos) /*!< BPWM_T::CAPCTL: RCRLDENn Mask */ 1658 1659 #define BPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDEN0 Position */ 1660 #define BPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN0 Mask */ 1661 1662 #define BPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< BPWM_T::CAPCTL: FCRLDEN1 Position */ 1663 #define BPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN1 Mask */ 1664 1665 #define BPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< BPWM_T::CAPCTL: FCRLDEN2 Position */ 1666 #define BPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN2 Mask */ 1667 1668 #define BPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< BPWM_T::CAPCTL: FCRLDEN3 Position */ 1669 #define BPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN3 Mask */ 1670 1671 #define BPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< BPWM_T::CAPCTL: FCRLDEN4 Position */ 1672 #define BPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN4 Mask */ 1673 1674 #define BPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< BPWM_T::CAPCTL: FCRLDEN5 Position */ 1675 #define BPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN5 Mask */ 1676 1677 #define BPWM_CAPCTL_FCRLDENn_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDENn Position */ 1678 #define BPWM_CAPCTL_FCRLDENn_Msk (0x3ful << BPWM_CAPCTL_FCRLDENn_Pos) /*!< BPWM_T::CAPCTL: FCRLDENn Mask */ 1679 1680 #define BPWM_CAPSTS_CRIFOV0_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOV0 Position */ 1681 #define BPWM_CAPSTS_CRIFOV0_Msk (0x1ul << BPWM_CAPSTS_CRIFOV0_Pos) /*!< BPWM_T::CAPSTS: CRIFOV0 Mask */ 1682 1683 #define BPWM_CAPSTS_CRIFOV1_Pos (1) /*!< BPWM_T::CAPSTS: CRIFOV1 Position */ 1684 #define BPWM_CAPSTS_CRIFOV1_Msk (0x1ul << BPWM_CAPSTS_CRIFOV1_Pos) /*!< BPWM_T::CAPSTS: CRIFOV1 Mask */ 1685 1686 #define BPWM_CAPSTS_CRIFOV2_Pos (2) /*!< BPWM_T::CAPSTS: CRIFOV2 Position */ 1687 #define BPWM_CAPSTS_CRIFOV2_Msk (0x1ul << BPWM_CAPSTS_CRIFOV2_Pos) /*!< BPWM_T::CAPSTS: CRIFOV2 Mask */ 1688 1689 #define BPWM_CAPSTS_CRIFOV3_Pos (3) /*!< BPWM_T::CAPSTS: CRIFOV3 Position */ 1690 #define BPWM_CAPSTS_CRIFOV3_Msk (0x1ul << BPWM_CAPSTS_CRIFOV3_Pos) /*!< BPWM_T::CAPSTS: CRIFOV3 Mask */ 1691 1692 #define BPWM_CAPSTS_CRIFOV4_Pos (4) /*!< BPWM_T::CAPSTS: CRIFOV4 Position */ 1693 #define BPWM_CAPSTS_CRIFOV4_Msk (0x1ul << BPWM_CAPSTS_CRIFOV4_Pos) /*!< BPWM_T::CAPSTS: CRIFOV4 Mask */ 1694 1695 #define BPWM_CAPSTS_CRIFOV5_Pos (5) /*!< BPWM_T::CAPSTS: CRIFOV5 Position */ 1696 #define BPWM_CAPSTS_CRIFOV5_Msk (0x1ul << BPWM_CAPSTS_CRIFOV5_Pos) /*!< BPWM_T::CAPSTS: CRIFOV5 Mask */ 1697 1698 #define BPWM_CAPSTS_CRIFOVn_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOVn Position */ 1699 #define BPWM_CAPSTS_CRIFOVn_Msk (0x3ful << BPWM_CAPSTS_CRIFOVn_Pos) /*!< BPWM_T::CAPSTS: CRIFOVn Mask */ 1700 1701 #define BPWM_CAPSTS_CFIFOV0_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOV0 Position */ 1702 #define BPWM_CAPSTS_CFIFOV0_Msk (0x1ul << BPWM_CAPSTS_CFIFOV0_Pos) /*!< BPWM_T::CAPSTS: CFIFOV0 Mask */ 1703 1704 #define BPWM_CAPSTS_CFIFOV1_Pos (9) /*!< BPWM_T::CAPSTS: CFIFOV1 Position */ 1705 #define BPWM_CAPSTS_CFIFOV1_Msk (0x1ul << BPWM_CAPSTS_CFIFOV1_Pos) /*!< BPWM_T::CAPSTS: CFIFOV1 Mask */ 1706 1707 #define BPWM_CAPSTS_CFIFOV2_Pos (10) /*!< BPWM_T::CAPSTS: CFIFOV2 Position */ 1708 #define BPWM_CAPSTS_CFIFOV2_Msk (0x1ul << BPWM_CAPSTS_CFIFOV2_Pos) /*!< BPWM_T::CAPSTS: CFIFOV2 Mask */ 1709 1710 #define BPWM_CAPSTS_CFIFOV3_Pos (11) /*!< BPWM_T::CAPSTS: CFIFOV3 Position */ 1711 #define BPWM_CAPSTS_CFIFOV3_Msk (0x1ul << BPWM_CAPSTS_CFIFOV3_Pos) /*!< BPWM_T::CAPSTS: CFIFOV3 Mask */ 1712 1713 #define BPWM_CAPSTS_CFIFOV4_Pos (12) /*!< BPWM_T::CAPSTS: CFIFOV4 Position */ 1714 #define BPWM_CAPSTS_CFIFOV4_Msk (0x1ul << BPWM_CAPSTS_CFIFOV4_Pos) /*!< BPWM_T::CAPSTS: CFIFOV4 Mask */ 1715 1716 #define BPWM_CAPSTS_CFIFOV5_Pos (13) /*!< BPWM_T::CAPSTS: CFIFOV5 Position */ 1717 #define BPWM_CAPSTS_CFIFOV5_Msk (0x1ul << BPWM_CAPSTS_CFIFOV5_Pos) /*!< BPWM_T::CAPSTS: CFIFOV5 Mask */ 1718 1719 #define BPWM_CAPSTS_CFIFOVn_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOVn Position */ 1720 #define BPWM_CAPSTS_CFIFOVn_Msk (0x3ful << BPWM_CAPSTS_CFIFOVn_Pos) /*!< BPWM_T::CAPSTS: CFIFOVn Mask */ 1721 1722 #define BPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT0: RCAPDAT Position */ 1723 #define BPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT0_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT0: RCAPDAT Mask */ 1724 1725 #define BPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT0: FCAPDAT Position */ 1726 #define BPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT0_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT0: FCAPDAT Mask */ 1727 1728 #define BPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT1: RCAPDAT Position */ 1729 #define BPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT1_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT1: RCAPDAT Mask */ 1730 1731 #define BPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT1: FCAPDAT Position */ 1732 #define BPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT1_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT1: FCAPDAT Mask */ 1733 1734 #define BPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT2: RCAPDAT Position */ 1735 #define BPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT2_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT2: RCAPDAT Mask */ 1736 1737 #define BPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT2: FCAPDAT Position */ 1738 #define BPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT2_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT2: FCAPDAT Mask */ 1739 1740 #define BPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT3: RCAPDAT Position */ 1741 #define BPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT3_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT3: RCAPDAT Mask */ 1742 1743 #define BPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT3: FCAPDAT Position */ 1744 #define BPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT3_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT3: FCAPDAT Mask */ 1745 1746 #define BPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT4: RCAPDAT Position */ 1747 #define BPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT4_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT4: RCAPDAT Mask */ 1748 1749 #define BPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT4: FCAPDAT Position */ 1750 #define BPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT4_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT4: FCAPDAT Mask */ 1751 1752 #define BPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT5: RCAPDAT Position */ 1753 #define BPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT5_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT5: RCAPDAT Mask */ 1754 1755 #define BPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT5: FCAPDAT Position */ 1756 #define BPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT5_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT5: FCAPDAT Mask */ 1757 1758 #define BPWM_CAPIEN_CAPRIENn_Pos (0) /*!< BPWM_T::CAPIEN: CAPRIENn Position */ 1759 #define BPWM_CAPIEN_CAPRIENn_Msk (0x3ful << BPWM_CAPIEN_CAPRIENn_Pos) /*!< BPWM_T::CAPIEN: CAPRIENn Mask */ 1760 1761 #define BPWM_CAPIEN_CAPFIENn_Pos (8) /*!< BPWM_T::CAPIEN: CAPFIENn Position */ 1762 #define BPWM_CAPIEN_CAPFIENn_Msk (0x3ful << BPWM_CAPIEN_CAPFIENn_Pos) /*!< BPWM_T::CAPIEN: CAPFIENn Mask */ 1763 1764 #define BPWM_CAPIF_CAPRIF0_Pos (0) /*!< BPWM_T::CAPIF: CAPRIF0 Position */ 1765 #define BPWM_CAPIF_CAPRIF0_Msk (0x1ul << BPWM_CAPIF_CAPRIF0_Pos) /*!< BPWM_T::CAPIF: CAPRIF0 Mask */ 1766 1767 #define BPWM_CAPIF_CAPRIF1_Pos (1) /*!< BPWM_T::CAPIF: CAPRIF1 Position */ 1768 #define BPWM_CAPIF_CAPRIF1_Msk (0x1ul << BPWM_CAPIF_CAPRIF1_Pos) /*!< BPWM_T::CAPIF: CAPRIF1 Mask */ 1769 1770 #define BPWM_CAPIF_CAPRIF2_Pos (2) /*!< BPWM_T::CAPIF: CAPRIF2 Position */ 1771 #define BPWM_CAPIF_CAPRIF2_Msk (0x1ul << BPWM_CAPIF_CAPRIF2_Pos) /*!< BPWM_T::CAPIF: CAPRIF2 Mask */ 1772 1773 #define BPWM_CAPIF_CAPRIF3_Pos (3) /*!< BPWM_T::CAPIF: CAPRIF3 Position */ 1774 #define BPWM_CAPIF_CAPRIF3_Msk (0x1ul << BPWM_CAPIF_CAPRIF3_Pos) /*!< BPWM_T::CAPIF: CAPRIF3 Mask */ 1775 1776 #define BPWM_CAPIF_CAPRIF4_Pos (4) /*!< BPWM_T::CAPIF: CAPRIF4 Position */ 1777 #define BPWM_CAPIF_CAPRIF4_Msk (0x1ul << BPWM_CAPIF_CAPRIF4_Pos) /*!< BPWM_T::CAPIF: CAPRIF4 Mask */ 1778 1779 #define BPWM_CAPIF_CAPRIF5_Pos (5) /*!< BPWM_T::CAPIF: CAPRIF5 Position */ 1780 #define BPWM_CAPIF_CAPRIF5_Msk (0x1ul << BPWM_CAPIF_CAPRIF5_Pos) /*!< BPWM_T::CAPIF: CAPRIF5 Mask */ 1781 1782 #define BPWM_CAPIF_CAPRIFn_Pos (0) /*!< BPWM_T::CAPIF: CAPRIFn Position */ 1783 #define BPWM_CAPIF_CAPRIFn_Msk (0x3ful << BPWM_CAPIF_CAPRIFn_Pos) /*!< BPWM_T::CAPIF: CAPRIFn Mask */ 1784 1785 #define BPWM_CAPIF_CAPFIF0_Pos (8) /*!< BPWM_T::CAPIF: CAPFIF0 Position */ 1786 #define BPWM_CAPIF_CAPFIF0_Msk (0x1ul << BPWM_CAPIF_CAPFIF0_Pos) /*!< BPWM_T::CAPIF: CAPFIF0 Mask */ 1787 1788 #define BPWM_CAPIF_CAPFIF1_Pos (9) /*!< BPWM_T::CAPIF: CAPFIF1 Position */ 1789 #define BPWM_CAPIF_CAPFIF1_Msk (0x1ul << BPWM_CAPIF_CAPFIF1_Pos) /*!< BPWM_T::CAPIF: CAPFIF1 Mask */ 1790 1791 #define BPWM_CAPIF_CAPFIF2_Pos (10) /*!< BPWM_T::CAPIF: CAPFIF2 Position */ 1792 #define BPWM_CAPIF_CAPFIF2_Msk (0x1ul << BPWM_CAPIF_CAPFIF2_Pos) /*!< BPWM_T::CAPIF: CAPFIF2 Mask */ 1793 1794 #define BPWM_CAPIF_CAPFIF3_Pos (11) /*!< BPWM_T::CAPIF: CAPFIF3 Position */ 1795 #define BPWM_CAPIF_CAPFIF3_Msk (0x1ul << BPWM_CAPIF_CAPFIF3_Pos) /*!< BPWM_T::CAPIF: CAPFIF3 Mask */ 1796 1797 #define BPWM_CAPIF_CAPFIF4_Pos (12) /*!< BPWM_T::CAPIF: CAPFIF4 Position */ 1798 #define BPWM_CAPIF_CAPFIF4_Msk (0x1ul << BPWM_CAPIF_CAPFIF4_Pos) /*!< BPWM_T::CAPIF: CAPFIF4 Mask */ 1799 1800 #define BPWM_CAPIF_CAPFIF5_Pos (13) /*!< BPWM_T::CAPIF: CAPFIF5 Position */ 1801 #define BPWM_CAPIF_CAPFIF5_Msk (0x1ul << BPWM_CAPIF_CAPFIF5_Pos) /*!< BPWM_T::CAPIF: CAPFIF5 Mask */ 1802 1803 #define BPWM_CAPIF_CAPFIFn_Pos (8) /*!< BPWM_T::CAPIF: CAPFIFn Position */ 1804 #define BPWM_CAPIF_CAPFIFn_Msk (0x3ful << BPWM_CAPIF_CAPFIFn_Pos) /*!< BPWM_T::CAPIF: CAPFIFn Mask */ 1805 1806 #define BPWM_PBUF_PBUF_Pos (0) /*!< BPWM_T::PBUF: PBUF Position */ 1807 #define BPWM_PBUF_PBUF_Msk (0xfffful << BPWM_PBUF_PBUF_Pos) /*!< BPWM_T::PBUF: PBUF Mask */ 1808 1809 #define BPWM_CMPBUF0_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF0: CMPBUF Position */ 1810 #define BPWM_CMPBUF0_CMPBUF_Msk (0xfffful << BPWM_CMPBUF0_CMPBUF_Pos) /*!< BPWM_T::CMPBUF0: CMPBUF Mask */ 1811 1812 #define BPWM_CMPBUF1_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF1: CMPBUF Position */ 1813 #define BPWM_CMPBUF1_CMPBUF_Msk (0xfffful << BPWM_CMPBUF1_CMPBUF_Pos) /*!< BPWM_T::CMPBUF1: CMPBUF Mask */ 1814 1815 #define BPWM_CMPBUF2_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF2: CMPBUF Position */ 1816 #define BPWM_CMPBUF2_CMPBUF_Msk (0xfffful << BPWM_CMPBUF2_CMPBUF_Pos) /*!< BPWM_T::CMPBUF2: CMPBUF Mask */ 1817 1818 #define BPWM_CMPBUF3_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF3: CMPBUF Position */ 1819 #define BPWM_CMPBUF3_CMPBUF_Msk (0xfffful << BPWM_CMPBUF3_CMPBUF_Pos) /*!< BPWM_T::CMPBUF3: CMPBUF Mask */ 1820 1821 #define BPWM_CMPBUF4_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF4: CMPBUF Position */ 1822 #define BPWM_CMPBUF4_CMPBUF_Msk (0xfffful << BPWM_CMPBUF4_CMPBUF_Pos) /*!< BPWM_T::CMPBUF4: CMPBUF Mask */ 1823 1824 #define BPWM_CMPBUF5_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF5: CMPBUF Position */ 1825 #define BPWM_CMPBUF5_CMPBUF_Msk (0xfffful << BPWM_CMPBUF5_CMPBUF_Pos) /*!< BPWM_T::CMPBUF5: CMPBUF Mask */ 1826 1827 /**@}*/ /* BPWM_CONST */ 1828 /**@}*/ /* end of BPWM register group */ 1829 /**@}*/ /* end of REGISTER group */ 1830 1831 #if defined ( __CC_ARM ) 1832 #pragma no_anon_unions 1833 #endif 1834 1835 #endif /* __BPWM_REG_H__ */ 1836
