1 /**************************************************************************//** 2 * @file acmp_reg.h 3 * @version V1.00 4 * @brief ACMP register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __ACMP_REG_H__ 10 #define __ACMP_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup ACMP Analog Comparator Controller(ACMP) 23 Memory Mapped Structure for ACMP Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var ACMP_T::CTL 32 * Offset: 0x00~0x04 Analog Comparator 0/1 Control Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[0] |ACMPEN |Comparator Enable Bit 37 * | | |0 = Comparator x Disabled. 38 * | | |1 = Comparator x Enabled. 39 * |[1] |ACMPIE |Comparator Interrupt Enable Bit 40 * | | |0 = Comparator x interrupt Disabled. 41 * | | |1 = Comparator x interrupt Enabled 42 * | | |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well. 43 * |[3] |ACMPOINV |Comparator Output Inverse 44 * | | |0 = Comparator x output inverse Disabled. 45 * | | |1 = Comparator x output inverse Enabled. 46 * |[5:4] |NEGSEL |Comparator Negative Input Selection 47 * | | |00 = ACMPx_N pin. 48 * | | |01 = Internal comparator reference voltage (CRV). 49 * | | |10 = Band-gap voltage. 50 * | | |11 = DAC output. 51 * |[7:6] |POSSEL |Comparator Positive Input Selection 52 * | | |00 = Input from ACMPx_P0. 53 * | | |01 = Input from ACMPx_P1. 54 * | | |10 = Input from ACMPx_P2. 55 * | | |11 = Input from ACMPx_P3. 56 * |[9:8] |INTPOL |Interrupt Condition Polarity Selection 57 * | | |ACMPIFx will be set to 1 when comparator output edge condition is detected. 58 * | | |00 = Rising edge or falling edge. 59 * | | |01 = Rising edge. 60 * | | |10 = Falling edge. 61 * | | |11 = Reserved. 62 * |[12] |OUTSEL |Comparator Output Select 63 * | | |0 = Comparator x output to ACMPx_O pin is unfiltered comparator output. 64 * | | |1 = Comparator x output to ACMPx_O pin is from filter output. 65 * |[15:13] |FILTSEL |Comparator Output Filter Count Selection 66 * | | |000 = Filter function is Disabled. 67 * | | |001 = ACMPx output is sampled 1 consecutive PCLK. 68 * | | |010 = ACMPx output is sampled 2 consecutive PCLKs. 69 * | | |011 = ACMPx output is sampled 4 consecutive PCLKs. 70 * | | |100 = ACMPx output is sampled 8 consecutive PCLKs. 71 * | | |101 = ACMPx output is sampled 16 consecutive PCLKs. 72 * | | |110 = ACMPx output is sampled 32 consecutive PCLKs. 73 * | | |111 = ACMPx output is sampled 64 consecutive PCLKs. 74 * |[16] |WKEN |Power-down Wake-up Enable Bit 75 * | | |0 = Wake-up function Disabled. 76 * | | |1 = Wake-up function Enabled. 77 * |[17] |WLATEN |Window Latch Mode Enable Bit 78 * | | |0 = Window Latch Mode Disabled. 79 * | | |1 = Window Latch Mode Enabled. 80 * |[18] |WCMPSEL |Window Compare Mode Selection 81 * | | |0 = Window Compare Mode Disabled. 82 * | | |1 = Window Compare Mode is Selected. 83 * |[25:24] |HYSSEL |Hysteresis Mode Selection 84 * | | |00 = Hysteresis is 0mV. 85 * | | |01 = Hysteresis is 10mV. 86 * | | |10 = Hysteresis is 20mV. 87 * | | |11 = Hysteresis is 30mV. 88 * |[29:28] |MODESEL |Propagation Delay Mode Selection 89 * | | |00 = Max propagation delay is 4.5uS, operation current is 1.2uA. 90 * | | |01 = Max propagation delay is 2uS, operation current is 3uA. 91 * | | |10 = Max propagation delay is 600nS, operation current is 10uA. 92 * | | |11 = Max propagation delay is 200nS, operation current is 75uA. 93 * @var ACMP_T::STATUS 94 * Offset: 0x08 Analog Comparator Status Register 95 * --------------------------------------------------------------------------------------------------- 96 * |Bits |Field |Descriptions 97 * | :----: | :----: | :---- | 98 * |[0] |ACMPIF0 |Comparator 0 Interrupt Flag 99 * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) 100 * | | |is detected on comparator 0 output. 101 * | | |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1. 102 * | | |Note: Write 1 to clear this bit to 0. 103 * |[1] |ACMPIF1 |Comparator 1 Interrupt Flag 104 * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) 105 * | | |is detected on comparator 1 output. 106 * | | |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1. 107 * | | |Note: Write 1 to clear this bit to 0. 108 * |[4] |ACMPO0 |Comparator 0 Output 109 * | | |Synchronized to the PCLK to allow reading by software 110 * | | |Cleared when the comparator 0 is disabled, i.e. 111 * | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0. 112 * |[5] |ACMPO1 |Comparator 1 Output 113 * | | |Synchronized to the PCLK to allow reading by software. 114 * | | |Cleared when the comparator 1 is disabled, i.e. 115 * | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0. 116 * |[8] |WKIF0 |Comparator 0 Power-down Wake-up Interrupt Flag 117 * | | |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs. 118 * | | |0 = No power-down wake-up occurred. 119 * | | |1 = Power-down wake-up occurred. 120 * | | |Note: Write 1 to clear this bit to 0. 121 * |[9] |WKIF1 |Comparator 1 Power-down Wake-up Interrupt Flag 122 * | | |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs. 123 * | | |0 = No power-down wake-up occurred. 124 * | | |1 = Power-down wake-up occurred. 125 * | | |Note: Write 1 to clear this bit to 0. 126 * |[12] |ACMPS0 |Comparator 0 Status 127 * | | |Synchronized to the PCLK to allow reading by software 128 * | | |Cleared when the comparator 0 is disabled, i.e. 129 * | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0. 130 * |[13] |ACMPS1 |Comparator 1 Status 131 * | | |Synchronized to the PCLK to allow reading by software 132 * | | |Cleared when the comparator 1 is disabled, i.e. 133 * | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0. 134 * |[16] |ACMPWO |Comparator Window Output 135 * | | |This bit shows the output status of window compare mode 136 * | | |0 = The positive input voltage is outside the window. 137 * | | |1 = The positive input voltage is in the window. 138 * @var ACMP_T::VREF 139 * Offset: 0x0C Analog Comparator Reference Voltage Control Register 140 * --------------------------------------------------------------------------------------------------- 141 * |Bits |Field |Descriptions 142 * | :----: | :----: | :---- | 143 * |[3:0] |CRVCTL |Comparator Reference Voltage Setting 144 * | | |CRV = CRV source voltage * (1/6+CRVCTL/24). 145 * |[6] |CRVSSEL |CRV Source Voltage Selection 146 * | | |0 = VDDA is selected as CRV source voltage. 147 * | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage. 148 */ 149 __IO uint32_t CTL[2]; /*!< [0x0000~0x0004] Analog Comparator 0/1 Control Register */ 150 __IO uint32_t STATUS; /*!< [0x0008] Analog Comparator Status Register */ 151 __IO uint32_t VREF; /*!< [0x000c] Analog Comparator Reference Voltage Control Register */ 152 153 } ACMP_T; 154 155 /** 156 @addtogroup ACMP_CONST ACMP Bit Field Definition 157 Constant Definitions for ACMP Controller 158 @{ */ 159 160 #define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP_T::CTL: ACMPEN Position */ 161 #define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP_T::CTL: ACMPEN Mask */ 162 163 #define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP_T::CTL: ACMPIE Position */ 164 #define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP_T::CTL: ACMPIE Mask */ 165 166 #define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP_T::CTL: ACMPOINV Position */ 167 #define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP_T::CTL: ACMPOINV Mask */ 168 169 #define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP_T::CTL: NEGSEL Position */ 170 #define ACMP_CTL_NEGSEL_Msk (0x3ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_T::CTL: NEGSEL Mask */ 171 172 #define ACMP_CTL_POSSEL_Pos (6) /*!< ACMP_T::CTL: POSSEL Position */ 173 #define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP_T::CTL: POSSEL Mask */ 174 175 #define ACMP_CTL_INTPOL_Pos (8) /*!< ACMP_T::CTL: INTPOL Position */ 176 #define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) /*!< ACMP_T::CTL: INTPOL Mask */ 177 178 #define ACMP_CTL_OUTSEL_Pos (12) /*!< ACMP_T::CTL: OUTSEL Position */ 179 #define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) /*!< ACMP_T::CTL: OUTSEL Mask */ 180 181 #define ACMP_CTL_FILTSEL_Pos (13) /*!< ACMP_T::CTL: FILTSEL Position */ 182 #define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_T::CTL: FILTSEL Mask */ 183 184 #define ACMP_CTL_WKEN_Pos (16) /*!< ACMP_T::CTL: WKEN Position */ 185 #define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) /*!< ACMP_T::CTL: WKEN Mask */ 186 187 #define ACMP_CTL_WLATEN_Pos (17) /*!< ACMP_T::CTL: WLATEN Position */ 188 #define ACMP_CTL_WLATEN_Msk (0x1ul << ACMP_CTL_WLATEN_Pos) /*!< ACMP_T::CTL: WLATEN Mask */ 189 190 #define ACMP_CTL_WCMPSEL_Pos (18) /*!< ACMP_T::CTL: WCMPSEL Position */ 191 #define ACMP_CTL_WCMPSEL_Msk (0x1ul << ACMP_CTL_WCMPSEL_Pos) /*!< ACMP_T::CTL: WCMPSEL Mask */ 192 193 #define ACMP_CTL_HYSSEL_Pos (24) /*!< ACMP_T::CTL: HYSSEL Position */ 194 #define ACMP_CTL_HYSSEL_Msk (0x3ul << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_T::CTL: HYSSEL Mask */ 195 196 #define ACMP_CTL_MODESEL_Pos (28) /*!< ACMP_T::CTL: MODESEL Position */ 197 #define ACMP_CTL_MODESEL_Msk (0x3ul << ACMP_CTL_MODESEL_Pos) /*!< ACMP_T::CTL: MODESEL Mask */ 198 199 #define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP_T::STATUS: ACMPIF0 Position */ 200 #define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP_T::STATUS: ACMPIF0 Mask */ 201 202 #define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP_T::STATUS: ACMPIF1 Position */ 203 #define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP_T::STATUS: ACMPIF1 Mask */ 204 205 #define ACMP_STATUS_ACMPO0_Pos (4) /*!< ACMP_T::STATUS: ACMPO0 Position */ 206 #define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP_T::STATUS: ACMPO0 Mask */ 207 208 #define ACMP_STATUS_ACMPO1_Pos (5) /*!< ACMP_T::STATUS: ACMPO1 Position */ 209 #define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP_T::STATUS: ACMPO1 Mask */ 210 211 #define ACMP_STATUS_WKIF0_Pos (8) /*!< ACMP_T::STATUS: WKIF0 Position */ 212 #define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) /*!< ACMP_T::STATUS: WKIF0 Mask */ 213 214 #define ACMP_STATUS_WKIF1_Pos (9) /*!< ACMP_T::STATUS: WKIF1 Position */ 215 #define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) /*!< ACMP_T::STATUS: WKIF1 Mask */ 216 217 #define ACMP_STATUS_ACMPS0_Pos (12) /*!< ACMP_T::STATUS: ACMPS0 Position */ 218 #define ACMP_STATUS_ACMPS0_Msk (0x1ul << ACMP_STATUS_ACMPS0_Pos) /*!< ACMP_T::STATUS: ACMPS0 Mask */ 219 220 #define ACMP_STATUS_ACMPS1_Pos (13) /*!< ACMP_T::STATUS: ACMPS1 Position */ 221 #define ACMP_STATUS_ACMPS1_Msk (0x1ul << ACMP_STATUS_ACMPS1_Pos) /*!< ACMP_T::STATUS: ACMPS1 Mask */ 222 223 #define ACMP_STATUS_ACMPWO_Pos (16) /*!< ACMP_T::STATUS: ACMPWO Position */ 224 #define ACMP_STATUS_ACMPWO_Msk (0x1ul << ACMP_STATUS_ACMPWO_Pos) /*!< ACMP_T::STATUS: ACMPWO Mask */ 225 226 #define ACMP_VREF_CRVCTL_Pos (0) /*!< ACMP_T::VREF: CRVCTL Position */ 227 #define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) /*!< ACMP_T::VREF: CRVCTL Mask */ 228 229 #define ACMP_VREF_CRVSSEL_Pos (6) /*!< ACMP_T::VREF: CRVSSEL Position */ 230 #define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_T::VREF: CRVSSEL Mask */ 231 232 /**@}*/ /* ACMP_CONST */ 233 /**@}*/ /* end of ACMP register group */ 234 /**@}*/ /* end of REGISTER group */ 235 236 #if defined ( __CC_ARM ) 237 #pragma no_anon_unions 238 #endif 239 240 #endif /* __ACMP_REG_H__ */ 241
