1 /**************************************************************************//**
2 * @file pdma.c
3 * @version V1.00
4 * @brief PDMA driver source file
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
8 *****************************************************************************/
9 #include "NuMicro.h"
10
11
12 static uint8_t au8ChSelect[PDMA_CH_MAX];
13
14 /** @addtogroup Standard_Driver Standard Driver
15 @{
16 */
17
18 /** @addtogroup PDMA_Driver PDMA Driver
19 @{
20 */
21
22
23 /** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
24 @{
25 */
26
27 /**
28 * @brief PDMA Open
29 *
30 * @param[in] pdma The pointer of the specified PDMA module
31 *
32 * @param[in] u32Mask Channel enable bits.
33 *
34 * @return None
35 *
36 * @details This function enable the PDMA channels.
37 */
PDMA_Open(PDMA_T * pdma,uint32_t u32Mask)38 void PDMA_Open(PDMA_T * pdma,uint32_t u32Mask)
39 {
40 uint32_t i;
41
42 for(i = 0UL; i < (int)PDMA_CH_MAX; i++)
43 {
44 if((1 << i) & u32Mask)
45 {
46 (pdma)->DSCT[i].CTL = 0UL;
47 au8ChSelect[i] = (uint8_t)PDMA_MEM;
48 }
49 }
50
51 (pdma)->CHCTL |= u32Mask;
52 }
53
54 /**
55 * @brief PDMA Close
56 *
57 * @param[in] pdma The pointer of the specified PDMA module
58 *
59 * @return None
60 *
61 * @details This function disable all PDMA channels.
62 */
PDMA_Close(PDMA_T * pdma)63 void PDMA_Close(PDMA_T * pdma)
64 {
65 (pdma)->CHCTL = 0UL;
66 }
67
68 /**
69 * @brief Set PDMA Transfer Count
70 *
71 * @param[in] pdma The pointer of the specified PDMA module
72 * @param[in] u32Ch The selected channel
73 * @param[in] u32Width Data width. Valid values are
74 * - \ref PDMA_WIDTH_8
75 * - \ref PDMA_WIDTH_16
76 * - \ref PDMA_WIDTH_32
77 * @param[in] u32TransCount Transfer count
78 *
79 * @return None
80 *
81 * @details This function set the selected channel data width and transfer count.
82 */
PDMA_SetTransferCnt(PDMA_T * pdma,uint32_t u32Ch,uint32_t u32Width,uint32_t u32TransCount)83 void PDMA_SetTransferCnt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
84 {
85 (pdma)->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXCNT_Msk | PDMA_DSCT_CTL_TXWIDTH_Msk);
86 (pdma)->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount - 1UL) << PDMA_DSCT_CTL_TXCNT_Pos));
87 }
88
89 /**
90 * @brief Set PDMA Stride Mode
91 *
92 * @param[in] pdma The pointer of the specified PDMA module
93 * @param[in] u32Ch The selected channel
94 * @param[in] u32DestLen Destination stride count
95 * @param[in] u32SrcLen Source stride count
96 * @param[in] u32TransCount Transfer count
97 *
98 * @return None
99 *
100 * @details This function set the selected stride mode.
101 */
PDMA_SetStride(PDMA_T * pdma,uint32_t u32Ch,uint32_t u32DestLen,uint32_t u32SrcLen,uint32_t u32TransCount)102 void PDMA_SetStride(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount)
103 {
104 (pdma)->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_STRIDEEN_Msk;
105 (pdma)->STRIDE[u32Ch].ASOCR = (u32DestLen << 16) | u32SrcLen;
106 (pdma)->STRIDE[u32Ch].STCR = u32TransCount;
107 }
108
109 /**
110 * @brief Set PDMA Repeat
111 *
112 * @param[in] pdma The pointer of the specified PDMA module
113 * @param[in] u32Ch The selected channel
114 * @param[in] u32DestInterval Destination address interval count
115 * @param[in] u32SrcInterval Source address interval count
116 * @param[in] u32RepeatCount Repeat count
117 *
118 * @return None
119 *
120 * @details This function set the selected repeat.
121 */
PDMA_SetRepeat(PDMA_T * pdma,uint32_t u32Ch,uint32_t u32DestInterval,uint32_t u32SrcInterval,uint32_t u32RepeatCount)122 void PDMA_SetRepeat(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32DestInterval, uint32_t u32SrcInterval, uint32_t u32RepeatCount)
123 {
124 (pdma)->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_STRIDEEN_Msk;
125 (pdma)->REPEAT[u32Ch].AICTL =((u32DestInterval)<<16) | (u32SrcInterval);
126 (pdma)->REPEAT[u32Ch].RCNT = u32RepeatCount;
127 }
128
129 /**
130 * @brief Set PDMA Transfer Address
131 *
132 * @param[in] pdma The pointer of the specified PDMA module
133 * @param[in] u32Ch The selected channel
134 * @param[in] u32SrcAddr Source address
135 * @param[in] u32SrcCtrl Source control attribute. Valid values are
136 * - \ref PDMA_SAR_INC
137 * - \ref PDMA_SAR_FIX
138 * @param[in] u32DstAddr destination address
139 * @param[in] u32DstCtrl destination control attribute. Valid values are
140 * - \ref PDMA_DAR_INC
141 * - \ref PDMA_DAR_FIX
142 *
143 * @return None
144 *
145 * @details This function set the selected channel source/destination address and attribute.
146 */
PDMA_SetTransferAddr(PDMA_T * pdma,uint32_t u32Ch,uint32_t u32SrcAddr,uint32_t u32SrcCtrl,uint32_t u32DstAddr,uint32_t u32DstCtrl)147 void PDMA_SetTransferAddr(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
148 {
149 (pdma)->DSCT[u32Ch].SA = u32SrcAddr;
150 (pdma)->DSCT[u32Ch].DA = u32DstAddr;
151 (pdma)->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_SAINC_Msk | PDMA_DSCT_CTL_DAINC_Msk);
152 (pdma)->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl);
153 }
154
155 /**
156 * @brief Set PDMA Transfer Mode
157 *
158 * @param[in] pdma The pointer of the specified PDMA module
159 * @param[in] u32Ch The selected channel
160 * @param[in] u32Peripheral The selected peripheral. Valid values are
161 * - \ref PDMA_MEM
162 * - \ref PDMA_USB_TX
163 * - \ref PDMA_USB_RX
164 * - \ref PDMA_UART0_TX
165 * - \ref PDMA_UART0_RX
166 * - \ref PDMA_UART1_TX
167 * - \ref PDMA_UART1_RX
168 * - \ref PDMA_UART2_TX
169 * - \ref PDMA_UART2_RX
170 * - \ref PDMA_UART3_TX
171 * - \ref PDMA_UART3_RX
172 * - \ref PDMA_UART4_TX
173 * - \ref PDMA_UART4_RX
174 * - \ref PDMA_UART5_TX
175 * - \ref PDMA_UART5_RX
176 * - \ref PDMA_USCI0_TX
177 * - \ref PDMA_USCI0_RX
178 * - \ref PDMA_QSPI0_TX
179 * - \ref PDMA_QSPI0_RX
180 * - \ref PDMA_SPI0_TX
181 * - \ref PDMA_SPI0_RX
182 * - \ref PDMA_SPI1_TX
183 * - \ref PDMA_SPI1_RX
184 * - \ref PDMA_SPI2_TX
185 * - \ref PDMA_SPI2_RX
186 * - \ref PDMA_SPI3_TX
187 * - \ref PDMA_SPI3_RX
188 * - \ref PDMA_QSPI1_TX
189 * - \ref PDMA_QSPI1_RX
190 * - \ref PDMA_EPWM0_P1_RX
191 * - \ref PDMA_EPWM0_P2_RX
192 * - \ref PDMA_EPWM0_P3_RX
193 * - \ref PDMA_EPWM1_P1_RX
194 * - \ref PDMA_EPWM1_P2_RX
195 * - \ref PDMA_EPWM1_P3_RX
196 * - \ref PDMA_I2C0_TX
197 * - \ref PDMA_I2C0_RX
198 * - \ref PDMA_I2C1_TX
199 * - \ref PDMA_I2C1_RX
200 * - \ref PDMA_I2C2_TX
201 * - \ref PDMA_I2C2_RX
202 * - \ref PDMA_I2S0_TX
203 * - \ref PDMA_I2S0_RX
204 * - \ref PDMA_TMR0
205 * - \ref PDMA_TMR1
206 * - \ref PDMA_TMR2
207 * - \ref PDMA_TMR3
208 * - \ref PDMA_EADC0_RX
209 * - \ref PDMA_DAC0_TX
210 * - \ref PDMA_DAC1_TX
211 * - \ref PDMA_EPWM0_CH0_TX
212 * - \ref PDMA_EPWM0_CH1_TX
213 * - \ref PDMA_EPWM0_CH2_TX
214 * - \ref PDMA_EPWM0_CH3_TX
215 * - \ref PDMA_EPWM0_CH4_TX
216 * - \ref PDMA_EPWM0_CH5_TX
217 * - \ref PDMA_EPWM1_CH0_TX
218 * - \ref PDMA_EPWM1_CH1_TX
219 * - \ref PDMA_EPWM1_CH2_TX
220 * - \ref PDMA_EPWM1_CH3_TX
221 * - \ref PDMA_EPWM1_CH4_TX
222 * - \ref PDMA_EPWM1_CH5_TX
223 * - \ref PDMA_UART6_TX
224 * - \ref PDMA_UART6_RX
225 * - \ref PDMA_UART7_TX
226 * - \ref PDMA_UART7_RX
227 * - \ref PDMA_EADC1_RX
228 * - \ref PDMA_ACMP0
229 * - \ref PDMA_ACMP1
230 * - \ref PDMA_PSIO_TX
231 * - \ref PDMA_PSIO_RX
232 * - \ref PDMA_I2C3_TX
233 * - \ref PDMA_I2C3_RX
234 * - \ref PDMA_I2C4_TX
235 * - \ref PDMA_I2C4_RX
236 * - \ref PDMA_I2S1_TX
237 * - \ref PDMA_I2S1_RX
238 * - \ref PDMA_EINT0
239 * - \ref PDMA_EINT1
240 * - \ref PDMA_EINT2
241 * - \ref PDMA_EINT3
242 * - \ref PDMA_EINT4
243 * - \ref PDMA_EINT5
244 * - \ref PDMA_EINT6
245 * - \ref PDMA_EINT7
246 * - \ref PDMA_UART8_TX
247 * - \ref PDMA_UART8_RX
248 * - \ref PDMA_UART9_TX
249 * - \ref PDMA_UART9_RX
250 * - \ref PDMA_EADC2_RX
251 * - \ref PDMA_ACMP2
252 * - \ref PDMA_ACMP3
253 * @param[in] u32ScatterEn Scatter-gather mode enable
254 * @param[in] u32DescAddr Scatter-gather descriptor address
255 *
256 * @return None
257 *
258 * @details This function set the selected channel transfer mode. Include peripheral setting.
259 */
PDMA_SetTransferMode(PDMA_T * pdma,uint32_t u32Ch,uint32_t u32Peripheral,uint32_t u32ScatterEn,uint32_t u32DescAddr)260 void PDMA_SetTransferMode(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
261 {
262 au8ChSelect[u32Ch] = (uint8_t)u32Peripheral;
263 switch(u32Ch)
264 {
265 case 0UL:
266 (pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC0_Msk) | u32Peripheral;
267 break;
268 case 1UL:
269 (pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC1_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC1_Pos);
270 break;
271 case 2UL:
272 (pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC2_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC2_Pos);
273 break;
274 case 3UL:
275 (pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC3_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC3_Pos);
276 break;
277 case 4UL:
278 (pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC4_Msk) | u32Peripheral;
279 break;
280 case 5UL:
281 (pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC5_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC5_Pos);
282 break;
283 case 6UL:
284 (pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC6_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC6_Pos);
285 break;
286 case 7UL:
287 (pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC7_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC7_Pos);
288 break;
289 case 8UL:
290 (pdma)->REQSEL8_11 = ((pdma)->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC8_Msk) | u32Peripheral;
291 break;
292 case 9UL:
293 (pdma)->REQSEL8_11 = ((pdma)->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC9_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC9_Pos);
294 break;
295 case 10UL:
296 (pdma)->REQSEL8_11 = ((pdma)->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC10_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC10_Pos);
297 break;
298 case 11UL:
299 (pdma)->REQSEL8_11 = ((pdma)->REQSEL8_11 & ~PDMA_REQSEL8_11_REQSRC11_Msk) | (u32Peripheral << PDMA_REQSEL8_11_REQSRC11_Pos);
300 break;
301 case 12UL:
302 (pdma)->REQSEL12_15 = ((pdma)->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC12_Msk) | u32Peripheral;
303 break;
304 case 13UL:
305 (pdma)->REQSEL12_15 = ((pdma)->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC13_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC13_Pos);
306 break;
307 case 14UL:
308 (pdma)->REQSEL12_15 = ((pdma)->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC14_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC14_Pos);
309 break;
310 case 15UL:
311 (pdma)->REQSEL12_15 = ((pdma)->REQSEL12_15 & ~PDMA_REQSEL12_15_REQSRC15_Msk) | (u32Peripheral << PDMA_REQSEL12_15_REQSRC15_Pos);
312 break;
313 default:
314 break;
315 }
316
317 if(u32ScatterEn)
318 {
319 (pdma)->DSCT[u32Ch].CTL = ((pdma)->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER;
320 (pdma)->DSCT[u32Ch].NEXT = u32DescAddr - ((pdma)->SCATBA);
321 }
322 else
323 {
324 (pdma)->DSCT[u32Ch].CTL = ((pdma)->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC;
325 }
326 }
327
328 /**
329 * @brief Set PDMA Burst Type and Size
330 *
331 * @param[in] pdma The pointer of the specified PDMA module
332 * @param[in] u32Ch The selected channel
333 * @param[in] u32BurstType Burst mode or single mode. Valid values are
334 * - \ref PDMA_REQ_SINGLE
335 * - \ref PDMA_REQ_BURST
336 * @param[in] u32BurstSize Set the size of burst mode. Valid values are
337 * - \ref PDMA_BURST_128
338 * - \ref PDMA_BURST_64
339 * - \ref PDMA_BURST_32
340 * - \ref PDMA_BURST_16
341 * - \ref PDMA_BURST_8
342 * - \ref PDMA_BURST_4
343 * - \ref PDMA_BURST_2
344 * - \ref PDMA_BURST_1
345 *
346 * @return None
347 *
348 * @details This function set the selected channel burst type and size.
349 */
PDMA_SetBurstType(PDMA_T * pdma,uint32_t u32Ch,uint32_t u32BurstType,uint32_t u32BurstSize)350 void PDMA_SetBurstType(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize)
351 {
352 (pdma)->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXTYPE_Msk | PDMA_DSCT_CTL_BURSIZE_Msk);
353 (pdma)->DSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize);
354 }
355
356 /**
357 * @brief Enable timeout function
358 *
359 * @param[in] pdma The pointer of the specified PDMA module
360 *
361 * @param[in] u32Mask Channel enable bits.
362 *
363 * @return None
364 *
365 * @details This function enable timeout function of the selected channel(s).
366 */
PDMA_EnableTimeout(PDMA_T * pdma,uint32_t u32Mask)367 void PDMA_EnableTimeout(PDMA_T * pdma,uint32_t u32Mask)
368 {
369 (pdma)->TOUTEN |= u32Mask;
370 }
371
372 /**
373 * @brief Disable timeout function
374 *
375 * @param[in] pdma The pointer of the specified PDMA module
376 *
377 * @param[in] u32Mask Channel enable bits.
378 *
379 * @return None
380 *
381 * @details This function disable timeout function of the selected channel(s).
382 */
PDMA_DisableTimeout(PDMA_T * pdma,uint32_t u32Mask)383 void PDMA_DisableTimeout(PDMA_T * pdma,uint32_t u32Mask)
384 {
385 (pdma)->TOUTEN &= ~u32Mask;
386 }
387
388 /**
389 * @brief Set PDMA Timeout Count
390 *
391 * @param[in] pdma The pointer of the specified PDMA module
392 * @param[in] u32Ch The selected channel,
393 * @param[in] u32OnOff Enable/disable time out function
394 * @param[in] u32TimeOutCnt Timeout count
395 *
396 * @return None
397 *
398 * @details This function set the timeout count.
399 */
PDMA_SetTimeOut(PDMA_T * pdma,uint32_t u32Ch,uint32_t u32OnOff,uint32_t u32TimeOutCnt)400 void PDMA_SetTimeOut(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
401 {
402 switch(u32Ch)
403 {
404 case 0UL:
405 (pdma)->TOC0_1 = ((pdma)->TOC0_1 & ~PDMA_TOC0_1_TOC0_Msk) | u32TimeOutCnt;
406 break;
407 case 1UL:
408 (pdma)->TOC0_1 = ((pdma)->TOC0_1 & ~PDMA_TOC0_1_TOC1_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos);
409 break;
410 case 2UL:
411 (pdma)->TOC2_3 = ((pdma)->TOC2_3 & ~PDMA_TOC2_3_TOC2_Msk) | u32TimeOutCnt;
412 break;
413 case 3UL:
414 (pdma)->TOC2_3 = ((pdma)->TOC2_3 & ~PDMA_TOC2_3_TOC3_Msk) | (u32TimeOutCnt << PDMA_TOC2_3_TOC3_Pos);
415 break;
416 case 4UL:
417 (pdma)->TOC4_5 = ((pdma)->TOC4_5 & ~PDMA_TOC4_5_TOC4_Msk) | u32TimeOutCnt;
418 break;
419 case 5UL:
420 (pdma)->TOC4_5 = ((pdma)->TOC4_5 & ~PDMA_TOC4_5_TOC5_Msk) | (u32TimeOutCnt << PDMA_TOC4_5_TOC5_Pos);
421 break;
422 case 6UL:
423 (pdma)->TOC6_7 = ((pdma)->TOC6_7 & ~PDMA_TOC6_7_TOC6_Msk) | u32TimeOutCnt;
424 break;
425 case 7UL:
426 (pdma)->TOC6_7 = ((pdma)->TOC6_7 & ~PDMA_TOC6_7_TOC7_Msk) | (u32TimeOutCnt << PDMA_TOC6_7_TOC7_Pos);
427 break;
428 case 8UL:
429 (pdma)->TOC8_9 = ((pdma)->TOC8_9 & ~PDMA_TOC8_9_TOC8_Msk) | u32TimeOutCnt;
430 break;
431 case 9UL:
432 (pdma)->TOC8_9 = ((pdma)->TOC8_9 & ~PDMA_TOC8_9_TOC9_Msk) | (u32TimeOutCnt << PDMA_TOC8_9_TOC9_Pos);
433 break;
434 case 10UL:
435 (pdma)->TOC10_11 = ((pdma)->TOC10_11 & ~PDMA_TOC10_11_TOC10_Msk) | u32TimeOutCnt;
436 break;
437 case 11UL:
438 (pdma)->TOC10_11 = ((pdma)->TOC10_11 & ~PDMA_TOC10_11_TOC11_Msk) | (u32TimeOutCnt << PDMA_TOC10_11_TOC11_Pos);
439 break;
440 case 12UL:
441 (pdma)->TOC12_13 = ((pdma)->TOC12_13 & ~PDMA_TOC12_13_TOC12_Msk) | u32TimeOutCnt;
442 break;
443 case 13UL:
444 (pdma)->TOC12_13 = ((pdma)->TOC12_13 & ~PDMA_TOC12_13_TOC13_Msk) | (u32TimeOutCnt << PDMA_TOC12_13_TOC13_Pos);
445 break;
446 case 14UL:
447 (pdma)->TOC14_15 = ((pdma)->TOC14_15 & ~PDMA_TOC14_15_TOC14_Msk) | u32TimeOutCnt;
448 break;
449 case 15UL:
450 (pdma)->TOC14_15 = ((pdma)->TOC14_15 & ~PDMA_TOC14_15_TOC15_Msk) | (u32TimeOutCnt << PDMA_TOC14_15_TOC15_Pos);
451 break;
452 default:
453 break;
454 }
455
456 if (u32OnOff)
457 {
458 (pdma)->TOUTEN |= (1UL << u32Ch);
459 }
460 else
461 {
462 (pdma)->TOUTEN &= ~(1UL << u32Ch);
463 }
464 }
465
466 /**
467 * @brief Trigger PDMA
468 *
469 * @param[in] pdma The pointer of the specified PDMA module
470 * @param[in] u32Ch The selected channel
471 *
472 * @return None
473 *
474 * @details This function trigger the selected channel.
475 */
PDMA_Trigger(PDMA_T * pdma,uint32_t u32Ch)476 void PDMA_Trigger(PDMA_T * pdma,uint32_t u32Ch)
477 {
478 if(au8ChSelect[u32Ch] == PDMA_MEM)
479 {
480 (pdma)->SWREQ = (1UL << u32Ch);
481 }
482 }
483
484 /**
485 * @brief Enable Interrupt
486 *
487 * @param[in] pdma The pointer of the specified PDMA module
488 * @param[in] u32Ch The selected channel
489 * @param[in] u32Mask The Interrupt Type. Valid values are
490 * - \ref PDMA_INT_TRANS_DONE
491 * - \ref PDMA_INT_TEMPTY
492 * - \ref PDMA_INT_TIMEOUT
493 *
494 * @return None
495 *
496 * @details This function enable the selected channel interrupt.
497 */
PDMA_EnableInt(PDMA_T * pdma,uint32_t u32Ch,uint32_t u32Mask)498 void PDMA_EnableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask)
499 {
500 switch(u32Mask)
501 {
502 case PDMA_INT_TRANS_DONE:
503 (pdma)->INTEN |= (1UL << u32Ch);
504 break;
505 case PDMA_INT_TEMPTY:
506 (pdma)->DSCT[u32Ch].CTL &= ~PDMA_DSCT_CTL_TBINTDIS_Msk;
507 break;
508 case PDMA_INT_TIMEOUT:
509 (pdma)->TOUTIEN |= (1UL << u32Ch);
510 break;
511
512 default:
513 break;
514 }
515 }
516
517 /**
518 * @brief Disable Interrupt
519 *
520 * @param[in] pdma The pointer of the specified PDMA module
521 * @param[in] u32Ch The selected channel
522 * @param[in] u32Mask The Interrupt Type. Valid values are
523 * - \ref PDMA_INT_TRANS_DONE
524 * - \ref PDMA_INT_TEMPTY
525 * - \ref PDMA_INT_TIMEOUT
526 *
527 * @return None
528 *
529 * @details This function disable the selected channel interrupt.
530 * @note The transfer done interrupt is disabled when table empty interrupt is disabled(PDMA_INT_TEMPTY).
531 */
PDMA_DisableInt(PDMA_T * pdma,uint32_t u32Ch,uint32_t u32Mask)532 void PDMA_DisableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask)
533 {
534 switch(u32Mask)
535 {
536 case PDMA_INT_TRANS_DONE:
537 (pdma)->INTEN &= ~(1UL << u32Ch);
538 break;
539 case PDMA_INT_TEMPTY:
540 (pdma)->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_TBINTDIS_Msk;
541 break;
542 case PDMA_INT_TIMEOUT:
543 (pdma)->TOUTIEN &= ~(1UL << u32Ch);
544 break;
545
546 default:
547 break;
548 }
549 }
550
551 /*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */
552
553 /*@}*/ /* end of group PDMA_Driver */
554
555 /*@}*/ /* end of group Standard_Driver */
556
557
