1 /**************************************************************************//**
2 * @file i2s.h
3 * @version V3.00
4 * @brief M460 series I2S driver header file
5 *
6 * @copyright SPDX-License-Identifier: Apache-2.0
7 * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
8 *****************************************************************************/
9 #ifndef __I2S_H__
10 #define __I2S_H__
11
12 #ifdef __cplusplus
13 extern "C"
14 {
15 #endif
16
17
18 /** @addtogroup Standard_Driver Standard Driver
19 @{
20 */
21
22 /** @addtogroup I2S_Driver I2S Driver
23 @{
24 */
25
26 /** @addtogroup I2S_EXPORTED_CONSTANTS I2S Exported Constants
27 @{
28 */
29
30 #define I2S_DATABIT_8 (0U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */
31 #define I2S_DATABIT_16 (1U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */
32 #define I2S_DATABIT_24 (2U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */
33 #define I2S_DATABIT_32 (3U << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */
34
35 /* Audio Format */
36 #define I2S_MONO I2S_CTL0_MONO_Msk /*!< Mono channel \hideinitializer */
37 #define I2S_STEREO (0U) /*!< Stereo channel \hideinitializer */
38 #define I2S_ENABLE_MONO I2S_MONO
39 #define I2S_DISABLE_MONO I2S_STEREO
40
41 /* I2S Data Format */
42 #define I2S_FORMAT_I2S (0U << I2S_CTL0_FORMAT_Pos) /*!< I2S data format \hideinitializer */
43 #define I2S_FORMAT_I2S_MSB (1U << I2S_CTL0_FORMAT_Pos) /*!< I2S MSB data format \hideinitializer */
44 #define I2S_FORMAT_I2S_LSB (2U << I2S_CTL0_FORMAT_Pos) /*!< I2S LSB data format \hideinitializer */
45 #define I2S_FORMAT_PCM (4U << I2S_CTL0_FORMAT_Pos) /*!< PCM data format \hideinitializer */
46 #define I2S_FORMAT_PCM_MSB (5U << I2S_CTL0_FORMAT_Pos) /*!< PCM MSB data format \hideinitializer */
47 #define I2S_FORMAT_PCM_LSB (6U << I2S_CTL0_FORMAT_Pos) /*!< PCM LSB data format \hideinitializer */
48
49 /* I2S Data Format */
50 #define I2S_ORDER_AT_MSB (0U) /*!< Channel data is at MSB \hideinitializer */
51 #define I2S_ORDER_AT_LSB I2S_CTL0_ORDER_Msk /*!< Channel data is at LSB \hideinitializer */
52
53 /* I2S TDM Channel Number */
54 #define I2S_TDM_2CH 0U /*!< Use TDM 2 channel \hideinitializer */
55 #define I2S_TDM_4CH 1U /*!< Use TDM 4 channel \hideinitializer */
56 #define I2S_TDM_6CH 2U /*!< Use TDM 6 channel \hideinitializer */
57 #define I2S_TDM_8CH 3U /*!< Use TDM 8 channel \hideinitializer */
58
59 /* I2S TDM Channel Width */
60 #define I2S_TDM_WIDTH_8BIT 0U /*!< TDM channel witch is 8-bit \hideinitializer */
61 #define I2S_TDM_WIDTH_16BIT 1U /*!< TDM channel witch is 16-bit \hideinitializer */
62 #define I2S_TDM_WIDTH_24BIT 2U /*!< TDM channel witch is 24-bit \hideinitializer */
63 #define I2S_TDM_WIDTH_32BIT 3U /*!< TDM channel witch is 32-bit \hideinitializer */
64
65 /* I2S TDM Sync Width */
66 #define I2S_TDM_SYNC_ONE_BCLK 0U /*!< TDM sync widht is one BLCK period \hideinitializer */
67 #define I2S_TDM_SYNC_ONE_CHANNEL 1U /*!< TDM sync widht is one channel period \hideinitializer */
68
69 /* I2S Operation mode */
70 #define I2S_MODE_SLAVE I2S_CTL0_SLAVE_Msk /*!< As slave mode \hideinitializer */
71 #define I2S_MODE_MASTER (0U) /*!< As master mode \hideinitializer */
72
73 /* I2S FIFO Threshold */
74 #define I2S_FIFO_TX_LEVEL_WORD_0 (0U) /*!< TX threshold is 0 word \hideinitializer */
75 #define I2S_FIFO_TX_LEVEL_WORD_1 (1U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 1 word \hideinitializer */
76 #define I2S_FIFO_TX_LEVEL_WORD_2 (2U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 2 words \hideinitializer */
77 #define I2S_FIFO_TX_LEVEL_WORD_3 (3U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 3 words \hideinitializer */
78 #define I2S_FIFO_TX_LEVEL_WORD_4 (4U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 4 words \hideinitializer */
79 #define I2S_FIFO_TX_LEVEL_WORD_5 (5U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 5 words \hideinitializer */
80 #define I2S_FIFO_TX_LEVEL_WORD_6 (6U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 6 words \hideinitializer */
81 #define I2S_FIFO_TX_LEVEL_WORD_7 (7U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 7 words \hideinitializer */
82 #define I2S_FIFO_TX_LEVEL_WORD_8 (8U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 8 words \hideinitializer */
83 #define I2S_FIFO_TX_LEVEL_WORD_9 (9U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 9 words \hideinitializer */
84 #define I2S_FIFO_TX_LEVEL_WORD_10 (10U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 10 words \hideinitializer */
85 #define I2S_FIFO_TX_LEVEL_WORD_11 (11U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 11 words \hideinitializer */
86 #define I2S_FIFO_TX_LEVEL_WORD_12 (12U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 12 words \hideinitializer */
87 #define I2S_FIFO_TX_LEVEL_WORD_13 (13U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 13 words \hideinitializer */
88 #define I2S_FIFO_TX_LEVEL_WORD_14 (14U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 14 words \hideinitializer */
89 #define I2S_FIFO_TX_LEVEL_WORD_15 (15U << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 15 words \hideinitializer */
90
91 #define I2S_FIFO_RX_LEVEL_WORD_1 (0U) /*!< RX threshold is 1 word \hideinitializer */
92 #define I2S_FIFO_RX_LEVEL_WORD_2 (1U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 2 words \hideinitializer */
93 #define I2S_FIFO_RX_LEVEL_WORD_3 (2U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 3 words \hideinitializer */
94 #define I2S_FIFO_RX_LEVEL_WORD_4 (3U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 4 words \hideinitializer */
95 #define I2S_FIFO_RX_LEVEL_WORD_5 (4U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 5 words \hideinitializer */
96 #define I2S_FIFO_RX_LEVEL_WORD_6 (5U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 6 words \hideinitializer */
97 #define I2S_FIFO_RX_LEVEL_WORD_7 (6U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 7 words \hideinitializer */
98 #define I2S_FIFO_RX_LEVEL_WORD_8 (7U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 8 words \hideinitializer */
99 #define I2S_FIFO_RX_LEVEL_WORD_9 (8U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 9 words \hideinitializer */
100 #define I2S_FIFO_RX_LEVEL_WORD_10 (9U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 10 words \hideinitializer */
101 #define I2S_FIFO_RX_LEVEL_WORD_11 (10U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 11 words \hideinitializer */
102 #define I2S_FIFO_RX_LEVEL_WORD_12 (11U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 12 words \hideinitializer */
103 #define I2S_FIFO_RX_LEVEL_WORD_13 (12U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 13 words \hideinitializer */
104 #define I2S_FIFO_RX_LEVEL_WORD_14 (13U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 14 words \hideinitializer */
105 #define I2S_FIFO_RX_LEVEL_WORD_15 (14U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 15 words \hideinitializer */
106 #define I2S_FIFO_RX_LEVEL_WORD_16 (15U << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 16 words \hideinitializer */
107
108 /* I2S Record Channel */
109 #define I2S_MONO_RIGHT (0U) /*!< Record mono right channel \hideinitializer */
110 #define I2S_MONO_LEFT I2S_CTL0_RXLCH_Msk /*!< Record mono left channel \hideinitializer */
111
112 /* I2S Channel */
113 #define I2S_RIGHT (0U) /*!< Select right channel \hideinitializer */
114 #define I2S_LEFT (1U) /*!< Select left channel \hideinitializer */
115
116 /*@}*/ /* end of group I2S_EXPORTED_CONSTANTS */
117
118
119 /** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions
120 @{
121 */
122
123 /**
124 * @brief Enable zero cross detect function.
125 * @param[in] i2s is the base address of I2S module.
126 * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8).
127 * @return none
128 * \hideinitializer
129 */
I2S_ENABLE_TX_ZCD(I2S_T * i2s,uint32_t u32ChMask)130 __STATIC_INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
131 {
132 if((u32ChMask > 0U) && (u32ChMask < 9U))
133 {
134 i2s->CTL1 |= ((uint32_t)1U << (u32ChMask-1U));
135 }
136 }
137
138 /**
139 * @brief Disable zero cross detect function.
140 * @param[in] i2s is the base address of I2S module.
141 * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8).
142 * @return none
143 * \hideinitializer
144 */
I2S_DISABLE_TX_ZCD(I2S_T * i2s,uint32_t u32ChMask)145 __STATIC_INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
146 {
147 if((u32ChMask > 0U) && (u32ChMask < 9U))
148 {
149 i2s->CTL1 &= ~((uint32_t)1U << (u32ChMask-1U));
150 }
151 }
152
153 /**
154 * @brief Enable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.
155 * @param[in] i2s is the base address of I2S module.
156 * @return none
157 * \hideinitializer
158 */
159 #define I2S_ENABLE_TXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXPDMAEN_Msk )
160
161 /**
162 * @brief Disable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.
163 * @param[in] i2s is the base address of I2S module.
164 * @return none
165 * \hideinitializer
166 */
167 #define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXPDMAEN_Msk )
168
169 /**
170 * @brief Enable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.
171 * @param[in] i2s is the base address of I2S module.
172 * @return none
173 * \hideinitializer
174 */
175 #define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXPDMAEN_Msk )
176
177 /**
178 * @brief Disable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.
179 * @param[in] i2s is the base address of I2S module.
180 * @return none
181 * \hideinitializer
182 */
183 #define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXPDMAEN_Msk )
184
185 /**
186 * @brief Enable I2S Tx function .
187 * @param[in] i2s is the base address of I2S module.
188 * @return none
189 * \hideinitializer
190 */
191 #define I2S_ENABLE_TX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXEN_Msk )
192
193 /**
194 * @brief Disable I2S Tx function .
195 * @param[in] i2s is the base address of I2S module.
196 * @return none
197 * \hideinitializer
198 */
199 #define I2S_DISABLE_TX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXEN_Msk )
200
201 /**
202 * @brief Enable I2S Rx function .
203 * @param[in] i2s is the base address of I2S module.
204 * @return none
205 * \hideinitializer
206 */
207 #define I2S_ENABLE_RX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXEN_Msk )
208
209 /**
210 * @brief Disable I2S Rx function .
211 * @param[in] i2s is the base address of I2S module.
212 * @return none
213 * \hideinitializer
214 */
215 #define I2S_DISABLE_RX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXEN_Msk )
216
217 /**
218 * @brief Enable Tx Mute function .
219 * @param[in] i2s is the base address of I2S module.
220 * @return none
221 * \hideinitializer
222 */
223 #define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->CTL0 |= I2S_CTL0_MUTE_Msk )
224
225 /**
226 * @brief Disable Tx Mute function .
227 * @param[in] i2s is the base address of I2S module.
228 * @return none
229 * \hideinitializer
230 */
231 #define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_MUTE_Msk )
232
233 /**
234 * @brief Clear Tx FIFO. Internal pointer is reset to FIFO start point.
235 * @param[in] i2s is the base address of I2S module.
236 * @return none
237 * \hideinitializer
238 */
239 #define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXFBCLR_Msk )
240
241 /**
242 * @brief Clear Rx FIFO. Internal pointer is reset to FIFO start point.
243 * @param[in] i2s is the base address of I2S module.
244 * @return none
245 * \hideinitializer
246 */
247 #define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXFBCLR_Msk )
248
249 /**
250 * @brief This function sets the recording source channel when mono mode is used.
251 * @param[in] i2s is the base address of I2S module.
252 * @param[in] u32Ch left or right channel. Valid values are:
253 * - \ref I2S_MONO_LEFT
254 * - \ref I2S_MONO_RIGHT
255 * @return none
256 * \hideinitializer
257 */
I2S_SET_MONO_RX_CHANNEL(I2S_T * i2s,uint32_t u32Ch)258 __STATIC_INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch)
259 {
260 u32Ch == I2S_MONO_LEFT ?
261 (i2s->CTL0 |= I2S_CTL0_RXLCH_Msk) :
262 (i2s->CTL0 &= ~I2S_CTL0_RXLCH_Msk);
263 }
264
265 /**
266 * @brief Write data to I2S Tx FIFO.
267 * @param[in] i2s is the base address of I2S module.
268 * @param[in] u32Data: The data written to FIFO.
269 * @return none
270 * \hideinitializer
271 */
272 #define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TXFIFO = (u32Data) )
273
274 /**
275 * @brief Read Rx FIFO.
276 * @param[in] i2s is the base address of I2S module.
277 * @return Data in Rx FIFO.
278 * \hideinitializer
279 */
280 #define I2S_READ_RX_FIFO(i2s) ( (i2s)->RXFIFO )
281
282 /**
283 * @brief This function gets the interrupt flag according to the mask parameter.
284 * @param[in] i2s is the base address of I2S module.
285 * @param[in] u32Mask is the mask for the all interrupt flags.
286 * @return The masked bit value of interrupt flag.
287 * \hideinitializer
288 */
289 #define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 & (u32Mask) )
290
291 /**
292 * @brief This function clears the interrupt flag according to the mask parameter.
293 * @param[in] i2s is the base address of I2S module.
294 * @param[in] u32Mask is the mask for the all interrupt flags.
295 * @return none
296 * \hideinitializer
297 */
298 #define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 |= (u32Mask) )
299
300 /**
301 * @brief This function gets the zero crossing interrupt flag according to the mask parameter.
302 * @param[in] i2s is the base address of I2S module.
303 * @param[in] u32Mask is the mask for the all interrupt flags.
304 * @return The masked bit value of interrupt flag.
305 * \hideinitializer
306 */
307 #define I2S_GET_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 & (u32Mask) )
308
309 /**
310 * @brief This function clears the zero crossing interrupt flag according to the mask parameter.
311 * @param[in] i2s is the base address of I2S module.
312 * @param[in] u32Mask is the mask for the all interrupt flags.
313 * @return none
314 * \hideinitializer
315 */
316 #define I2S_CLR_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 |= (u32Mask) )
317
318 /**
319 * @brief Get transmit FIFO level
320 * @param[in] i2s is the base address of I2S module.
321 * @return FIFO level
322 * \hideinitializer
323 */
324 #define I2S_GET_TX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_TXCNT_Msk) >> I2S_STATUS1_TXCNT_Pos) & 0xF )
325
326 /**
327 * @brief Get receive FIFO level
328 * @param[in] i2s is the base address of I2S module.
329 * @return FIFO level
330 * \hideinitializer
331 */
332 #define I2S_GET_RX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_RXCNT_Msk) >> I2S_STATUS1_RXCNT_Pos) & 0xF )
333
334 uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat);
335 void I2S_Close(I2S_T *i2s);
336 void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask);
337 void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask);
338 uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock);
339 void I2S_DisableMCLK(I2S_T *i2s);
340 void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
341 void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth);
342
343
344 /*@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */
345
346 /*@}*/ /* end of group I2S_Driver */
347
348 /*@}*/ /* end of group Standard_Driver */
349
350 #ifdef __cplusplus
351 }
352 #endif
353
354 #endif /* __I2S_H__ */
355
