1 /**************************************************************************//** 2 * @file wdt_reg.h 3 * @version V3.00 4 * @brief WDT register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __WDT_REG_H__ 10 #define __WDT_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** @addtogroup REGISTER Control Register 17 @{ 18 */ 19 20 /*---------------------- Watch Dog Timer Controller -------------------------*/ 21 /** 22 @addtogroup WDT Watch Dog Timer Controller (WDT) 23 Memory Mapped Structure for WDT Controller 24 @{ 25 */ 26 27 typedef struct 28 { 29 30 31 /** 32 * @var WDT_T::CTL 33 * Offset: 0x00 WDT Control Register 34 * --------------------------------------------------------------------------------------------------- 35 * |Bits |Field |Descriptions 36 * | :----: | :----: | :---- | 37 * |[1] |RSTEN |WDT Time-out Reset Enable Control (Write Protect) 38 * | | |Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires. 39 * | | |0 = WDT time-out reset function Disabled. 40 * | | |1 = WDT time-out reset function Enabled. 41 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 42 * |[2] |RSTF |WDT Time-out Reset Flag 43 * | | |This bit indicates the system has been reset by WDT time-out reset or not. 44 * | | |0 = WDT time-out reset did not occur. 45 * | | |1 = WDT time-out reset occurred. 46 * | | |Note: This bit is cleared by writing 1 to it. 47 * |[3] |IF |WDT Time-out Interrupt Flag 48 * | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval 49 * | | |0 = WDT time-out interrupt did not occur. 50 * | | |1 = WDT time-out interrupt occurred. 51 * | | |Note: This bit is cleared by writing 1 to it. 52 * |[4] |WKEN |WDT Time-out Wake-up Function Control (Write Protect) 53 * | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip. 54 * | | |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated. 55 * | | |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated. 56 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. 57 * | | |Note2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz internal low speed RC oscillator (LIRC) or LXT. 58 * |[5] |WKF |WDT Time-out Wake-up Flag (Write Protect) 59 * | | |This bit indicates the interrupt wake-up flag status of WDT 60 * | | |0 = WDT does not cause chip wake-up. 61 * | | |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated. 62 * | | |Note: This bit is cleared by writing 1 to it. 63 * |[6] |INTEN |WDT Time-out Interrupt Enable Control (Write Protect) 64 * | | |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. 65 * | | |0 = WDT time-out interrupt Disabled. 66 * | | |1 = WDT time-out interrupt Enabled. 67 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 68 * |[7] |WDTEN |WDT Enable Bit (Write Protect) 69 * | | |0 = WDT Disabled (This action will reset the internal up counter value). 70 * | | |1 = WDT Enabled. 71 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. 72 * | | |Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111, this bit is forced as 1 and user cannot change this bit to 0. 73 * |[11:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect) 74 * | | |These three bits select the time-out interval period for the WDT. 75 * | | |000 = 2^4 * WDT_CLK. 76 * | | |001 = 2^6 * WDT_CLK. 77 * | | |010 = 2^8 * WDT_CLK. 78 * | | |011 = 2^10 * WDT_CLK. 79 * | | |100 = 2^12 * WDT_CLK. 80 * | | |101 = 2^14 * WDT_CLK. 81 * | | |110 = 2^16 * WDT_CLK. 82 * | | |111 = 2^18 * WDT_CLK. 83 * | | |111 = 2^20 * WDT_CLK. 84 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 85 * |[30] |SYNC |WDT Enable Control SYNC Flag Indicator (Read Only) 86 * | | |If user execute enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not. 87 * | | |0 = Setting WDTEN bit is completed and WDT is ready. 88 * | | |1 = Setting WDTEN bit is synchronizing and not become active yet. 89 * | | |Note: Perform enable or disable WDTEN bit needs 4 * WDT_CLK period to become active. 90 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit (Write Protect) 91 * | | |0 = ICE debug mode acknowledgement affects WDT counting. 92 * | | |WDT up counter will be held while CPU is held by ICE. 93 * | | |1 = ICE debug mode acknowledgement Disabled. 94 * | | |WDT up counter will keep going no matter CPU is held by ICE or not. 95 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 96 * @var WDT_T::ALTCTL 97 * Offset: 0x04 WDT Alternative Control Register 98 * --------------------------------------------------------------------------------------------------- 99 * |Bits |Field |Descriptions 100 * | :----: | :----: | :---- | 101 * |[1:0] |RSTDSEL |WDT Reset Delay Selection (Write Protect) 102 * | | |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by programming 0x5AA5 to prevent WDT time-out reset happened. 103 * | | |User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period. 104 * | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK. 105 * | | |01 = WDT Reset Delay Period is 130 * WDT_CLK. 106 * | | |10 = WDT Reset Delay Period is 18 * WDT_CLK. 107 * | | |11 = WDT Reset Delay Period is 3 * WDT_CLK. 108 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. 109 * | | |Note2: This register will be reset to 0 if WDT time-out reset happened. 110 * @var WDT_T::RSTCNT 111 * Offset: 0x08 WDT Reset Counter Register 112 * --------------------------------------------------------------------------------------------------- 113 * |Bits |Field |Descriptions 114 * | :----: | :----: | :---- | 115 * |[31:0] |RSTCNT |WDT Reset Counter Register 116 * | | |Writing 0x00005AA5 to this field will reset the internal 20-bit WDT up counter value to 0. 117 * | | |Note: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active. 118 */ 119 __IO uint32_t CTL; /*!< [0x0000] WDT Control Register */ 120 __IO uint32_t ALTCTL; /*!< [0x0004] WDT Alternative Control Register */ 121 __O uint32_t RSTCNT; /*!< [0x0008] WDT Reset Counter Register */ 122 123 } WDT_T; 124 125 /** 126 @addtogroup WDT_CONST WDT Bit Field Definition 127 Constant Definitions for WDT Controller 128 @{ 129 */ 130 131 #define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */ 132 #define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */ 133 134 #define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */ 135 #define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */ 136 137 #define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */ 138 #define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */ 139 140 #define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */ 141 #define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */ 142 143 #define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */ 144 #define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */ 145 146 #define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */ 147 #define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */ 148 149 #define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */ 150 #define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */ 151 152 #define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */ 153 #define WDT_CTL_TOUTSEL_Msk (0xful << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */ 154 155 #define WDT_CTL_SYNC_Pos (30) /*!< WDT_T::CTL: SYNC Position */ 156 #define WDT_CTL_SYNC_Msk (0x1ul << WDT_CTL_SYNC_Pos) /*!< WDT_T::CTL: SYNC Mask */ 157 158 #define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */ 159 #define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */ 160 161 #define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */ 162 #define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */ 163 164 #define WDT_RSTCNT_RSTCNT_Pos (0) /*!< WDT_T::RSTCNT: RSTCNT Position */ 165 #define WDT_RSTCNT_RSTCNT_Msk (0xfffffffful << WDT_RSTCNT_RSTCNT_Pos) /*!< WDT_T::RSTCNT: RSTCNT Mask */ 166 167 168 /**@}*/ /* WDT_CONST */ 169 /**@}*/ /* end of WDT register group */ 170 /**@}*/ /* end of REGISTER group */ 171 172 #if defined ( __CC_ARM ) 173 #pragma no_anon_unions 174 #endif 175 176 #endif /* __WDT_REG_H__ */ 177
