1 /**************************************************************************//** 2 * @file fmc_reg.h 3 * @version V1.00 4 * @brief FMC register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __FMC_REG_H__ 10 #define __FMC_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup FMC Flash Memory Controller (FMC) 23 Memory Mapped Structure for FMC Controller 24 @{ */ 25 26 typedef struct 27 { 28 /** 29 * @var FMC_T::ISPCTL 30 * Offset: 0x00 ISP Control Register 31 * --------------------------------------------------------------------------------------------------- 32 * |Bits |Field |Descriptions 33 * | :----: | :----: | :---- | 34 * |[0] |ISPEN |ISP Enable Bit (Write Protect) 35 * | | |ISP function enable bit. Set this bit to enable ISP function. 36 * | | |0 = ISP function Disabled. 37 * | | |1 = ISP function Enabled. 38 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 39 * |[1] |BS |Boot Select (Write Protect) 40 * | | |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively 41 * | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from 42 * | | |This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened 43 * | | |0 = Booting from APROM when MBS (CONFIG0[5]) is 1. 44 * | | |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1. 45 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 46 * |[3] |APUEN |APROM Update Enable Bit (Write Protect) 47 * | | |0 = APROM cannot be updated when the chip runs in APROM. 48 * | | |1 = APROM can be updated when the chip runs in APROM. 49 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 50 * |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect) 51 * | | |0 = CONFIG cannot be updated. 52 * | | |1 = CONFIG can be updated. 53 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 54 * |[5] |LDUEN |LDROM Update Enable Bit (Write Protect) 55 * | | |LDROM update enable bit. 56 * | | |0 = LDROM cannot be updated. 57 * | | |1 = LDROM can be updated. 58 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 59 * |[6] |ISPFF |ISP Fail Flag (Write Protect) 60 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: 61 * | | |This bit needs to be cleared by writing 1 to it. 62 * | | |(1) APROM writes to itself if APUEN is set to 0. 63 * | | |(2) LDROM writes to itself if LDUEN is set to 0. 64 * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. 65 * | | |(4) SPROM is erased/programmed if SPUEN is set to 0 66 * | | |(5) SPROM is programmed at SPROM secured mode. 67 * | | |(6) Page Erase command at LOCK mode with ICE connection 68 * | | |(7) Erase or Program command at brown-out detected 69 * | | |(8) Destination address is illegal, such as over an available range. 70 * | | |(9) Invalid ISP commands 71 * | | |(10) Vector address is mapping to SPROM region 72 * | | |(11) KPROM is erased/programmed if KEYLOCK is set to 1 73 * | | |(12) APROM(except for Data Flash) is erased/programmed if KEYLOCK is set to 1 74 * | | |(13) LDROM is erased/programmed if KEYLOCK is set to 1 75 * | | |(14) SPROM is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1. 76 * | | |(15) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1 77 * | | |(16) Invalid operations (except for chip erase) with ICE connection if SBLOCK is not 0x5A 78 * | | |(17) Read any content of boot loader with ICE connection 79 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 80 * |[16] |BL |Boot Loader Booting (Write Protect) 81 * | | |This bit is initiated with the inversed value of MBS (CONFIG0[5]) 82 * | | |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded 83 * | | |This bit is used to check chip boot from Boot Loader or not 84 * | | |User should keep original value of this bit when updating FMC_ISPCTL register. 85 * | | |0 = Booting from APROM or LDROM. 86 * | | |1 = Booting from Boot Loader. 87 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 88 * @var FMC_T::ISPADDR 89 * Offset: 0x04 ISP Address Register 90 * --------------------------------------------------------------------------------------------------- 91 * |Bits |Field |Descriptions 92 * | :----: | :----: | :---- | 93 * |[31:0] |ISPADDR |ISP Address 94 * | | |The NuMicro M480 series is equipped with embedded flash 95 * | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation 96 * | | |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation. 97 * | | |For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 4 Kbytes alignment is necessary for CRC32 checksum calculation. 98 * | | |For FLASH 32-bit Program, ISP address needs word alignment (4-byte) 99 * | | |For FLASH 64-bit Program, ISP address needs double word alignment (8-byte). 100 * @var FMC_T::ISPDAT 101 * Offset: 0x08 ISP Data Register 102 * --------------------------------------------------------------------------------------------------- 103 * |Bits |Field |Descriptions 104 * | :----: | :----: | :---- | 105 * |[31:0] |ISPDAT |ISP Data 106 * | | |Write data to this register before ISP program operation. 107 * | | |Read data from this register after ISP read operation. 108 * | | |When ISPFF (FMC_ISPCTL[6]) is 1, ISPDAT = 0xffff_ffff 109 * | | |For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 4 Kbytes alignment 110 * | | |For ISP Read CRC32 Checksum command, ISPDAT is the checksum result 111 * | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect 112 * @var FMC_T::ISPCMD 113 * Offset: 0x0C ISP Command Register 114 * --------------------------------------------------------------------------------------------------- 115 * |Bits |Field |Descriptions 116 * | :----: | :----: | :---- | 117 * |[6:0] |CMD |ISP Command 118 * | | |ISP command table is shown below: 119 * | | |0x00= FLASH Read. 120 * | | |0x04= Read Unique ID. 121 * | | |0x08= Read Flash All-One Result. 122 * | | |0x0B= Read Company ID. 123 * | | |0x0C= Read Device ID. 124 * | | |0x0D= Read Checksum. 125 * | | |0x21= FLASH 32-bit Program. 126 * | | |0x22= FLASH Page Erase. Erase any page in two banks, except for OTP. 127 * | | |0x23= FLASH Bank Erase. Erase all pages of APROM in BANK0 or BANK1. 128 * | | |0x27= FLASH Multi-Word Program. 129 * | | |0x28= Run Flash All-One Verification. 130 * | | |0x2C= Bank Remap. 131 * | | |0x2D= Run Checksum Calculation. 132 * | | |0x2E= Vector Remap. 133 * | | |0x40= FLASH 64-bit Read. 134 * | | |0x61= FLASH 64-bit Program. 135 * | | |The other commands are invalid. 136 * @var FMC_T::ISPTRG 137 * Offset: 0x10 ISP Trigger Control Register 138 * --------------------------------------------------------------------------------------------------- 139 * |Bits |Field |Descriptions 140 * | :----: | :----: | :---- | 141 * |[0] |ISPGO |ISP Start Trigger (Write Protect) 142 * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. 143 * | | |0 = ISP operation is finished. 144 * | | |1 = ISP is progressed. 145 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 146 * @var FMC_T::DFBA 147 * Offset: 0x14 Data Flash Base Address 148 * --------------------------------------------------------------------------------------------------- 149 * |Bits |Field |Descriptions 150 * | :----: | :----: | :---- | 151 * |[31:0] |DFBA |Data Flash Base Address 152 * | | |This register indicates Data Flash start address. It is a read only register. 153 * | | |The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1 154 * | | |This register is valid when DFEN (CONFIG0[0]) =0 . 155 * @var FMC_T::ISPSTS 156 * Offset: 0x40 ISP Status Register 157 * --------------------------------------------------------------------------------------------------- 158 * |Bits |Field |Descriptions 159 * | :----: | :----: | :---- | 160 * |[0] |ISPBUSY |ISP Busy Flag (Read Only) 161 * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. 162 * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]). 163 * | | |0 = ISP operation is finished. 164 * | | |1 = ISP is progressed. 165 * |[2:1] |CBS |Boot Selection of CONFIG (Read Only) 166 * | | |This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened. 167 * | | |The following function is valid when MBS (FMC_ISPSTS[3])= 1. 168 * | | |00 = LDROM with IAP mode. 169 * | | |01 = LDROM without IAP mode. 170 * | | |10 = APROM with IAP mode. 171 * | | |11 = APROM without IAP mode. 172 * |[3] |MBS |Boot From Boot Loader Selection Flag (Read Only) 173 * | | |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened 174 * | | |0 = Booting from Boot Loader. 175 * | | |1 = Booting from LDROM/APROM.(.see CBS bit setting) 176 * |[5] |PGFF |Flash Program with Fast Verification Flag (Read Only) 177 * | | |This bit is set if data is mismatched at ISP programming verification 178 * | | |This bit is clear by performing ISP flash erase or ISP read CID operation 179 * | | |0 = Flash Program is success. 180 * | | |1 = Flash Program is fail. Program data is different with data in the flash memory 181 * |[6] |ISPFF |ISP Fail Flag (Write Protect) 182 * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] 183 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: 184 * | | |(1) APROM writes to itself if APUEN is set to 0. 185 * | | |(2) LDROM writes to itself if LDUEN is set to 0. 186 * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. 187 * | | |(4) SPROM is erased/programmed if SPUEN is set to 0 188 * | | |(5) SPROM is programmed at SPROM secured mode. 189 * | | |(6) Page Erase command at LOCK mode with ICE connection 190 * | | |(7) Erase or Program command at brown-out detected 191 * | | |(8) Destination address is illegal, such as over an available range. 192 * | | |(9) Invalid ISP commands 193 * | | |(10) Vector address is mapping to SPROM region. 194 * | | |(11) KPROM is erased/programmed if KEYLOCK is set to 1 195 * | | |(12) APROM(except for Data Flash) is erased/programmed if KEYLOCK is set to 1 196 * | | |(13) LDROM is erased/programmed if KEYLOCK is set to 1 197 * | | |(14) SPROM is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1. 198 * | | |(15) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[1:0] are 1. 199 * | | |(16) Invalid operations (except for chip erase) with ICE connection if SBLOCK is not 0x5A 200 * | | |(17) Read any content of boot loader with ICE connection 201 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 202 * |[7] |ALLONE |Flash All-one Verification Flag 203 * | | |This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after "Run Flash All-One Verification" complete; this bit also can be clear by writing 1 204 * | | |0 = All of flash bits are 1 after "Run Flash All-One Verification" complete. 205 * | | |1 = Flash bits are not all 1 after "Run Flash All-One Verification" complete. 206 * |[23:9] |VECMAP |Vector Page Mapping Address (Read Only) 207 * | | |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9u2019h000} ~ {VECMAP[14:0], 9u2019h1FF} 208 * |[24] |INTFLAG |ISP Interrupt Flag 209 * | | |0 = ISP Not Finished. 210 * | | |1 = ISP done or ISPFF set. 211 * | | |Note: This function needs to be enabled by FMC_ISPCTRL[24]. 212 * |[28] |ISPCERR |ISP Conflict Error 213 * | | |This bit shows when FMC is doing ISP operation. User cannot access FMC_ISP_ADDR,FMC_ISPDAT,FMC_ISPCMD,FMC_ISPTRG. It would cause ISPFF. 214 * |[30] |FBS |Flash Bank Selection 215 * | | |This bit indicate which bank is selected to boot. 216 * | | |0 = Booting from BANK0. 217 * | | |1 = Booting from BANK1. 218 * @var FMC_T::CYCCTL 219 * Offset: 0x4C Flash Access Cycle Control Register 220 * --------------------------------------------------------------------------------------------------- 221 * |Bits |Field |Descriptions 222 * | :----: | :----: | :---- | 223 * |[3:0] |CYCLE |Flash Access Cycle Control (Write Protect) 224 * | | |0001 = CPU access with one wait cycle if cache miss; flash access cycle is 1;. 225 * | | |The HCLK working frequency range range is<27MHz 226 * | | |0010 = CPU access with two wait cycles if cache miss; flash access cycle is 2;. 227 * | | | The optimized HCLK working frequency range is 27~54 MHz 228 * | | |0011 = CPU access with three wait cycles if cache miss; flash access cycle is 3;. 229 * | | |The optimized HCLK working frequency range is 54~81MHz 230 * | | |0100 = CPU access with four wait cycles if cache miss; flash access cycle is 4;. 231 * | | | The optimized HCLK working frequency range is81~108MHz 232 * | | |0101 = CPU access with five wait cycles if cache miss; flash access cycle is 5;. 233 * | | |The optimized HCLK working frequency range is 108~135MHz 234 * | | |0110 = CPU access with six wait cycles if cache miss; flash access cycle is 6;. 235 * | | | The optimized HCLK working frequency range is 135~162MHz 236 * | | |0111 = CPU access with seven wait cycles if cache miss; flash access cycle is 7;. 237 * | | | The optimized HCLK working frequency range is 162~192MHz 238 * | | |1000 = CPU access with eight wait cycles if cache miss; flash access cycle is 8;. 239 * | | |The optimized HCLK working frequency range is >192MHz 240 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 241 * @var FMC_T::MPDAT0 242 * Offset: 0x80 ISP Data0 Register 243 * --------------------------------------------------------------------------------------------------- 244 * |Bits |Field |Descriptions 245 * | :----: | :----: | :---- | 246 * |[31:0] |ISPDAT0 |ISP Data 0 247 * | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data 248 * @var FMC_T::MPDAT1 249 * Offset: 0x84 ISP Data1 Register 250 * --------------------------------------------------------------------------------------------------- 251 * |Bits |Field |Descriptions 252 * | :----: | :----: | :---- | 253 * |[31:0] |ISPDAT1 |ISP Data 1 254 * | | |This register is the second 32-bit data for 64-bit/multi-word programming. 255 * @var FMC_T::MPDAT2 256 * Offset: 0x88 ISP Data2 Register 257 * --------------------------------------------------------------------------------------------------- 258 * |Bits |Field |Descriptions 259 * | :----: | :----: | :---- | 260 * |[31:0] |ISPDAT2 |ISP Data 2 261 * | | |This register is the third 32-bit data for multi-word programming. 262 * @var FMC_T::MPDAT3 263 * Offset: 0x8C ISP Data3 Register 264 * --------------------------------------------------------------------------------------------------- 265 * |Bits |Field |Descriptions 266 * | :----: | :----: | :---- | 267 * |[31:0] |ISPDAT3 |ISP Data 3 268 * | | |This register is the fourth 32-bit data for multi-word programming. 269 * @var FMC_T::MPSTS 270 * Offset: 0xC0 ISP Multi-Program Status Register 271 * --------------------------------------------------------------------------------------------------- 272 * |Bits |Field |Descriptions 273 * | :----: | :----: | :---- | 274 * |[0] |MPBUSY |ISP Multi-word Program Busy Flag (Read Only) 275 * | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished. 276 * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]). 277 * | | |0 = ISP Multi-Word program operation is finished. 278 * | | |1 = ISP Multi-Word program operation is progressed. 279 * |[1] |PPGO |ISP Multi-program Status (Read Only) 280 * | | |0 = ISP multi-word program operation is not active. 281 * | | |1 = ISP multi-word program operation is in progress. 282 * |[2] |ISPFF |ISP Fail Flag (Read Only) 283 * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] 284 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: 285 * | | |(1) APROM writes to itself if APUEN is set to 0. 286 * | | |(2) LDROM writes to itself if LDUEN is set to 0. 287 * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. 288 * | | |(4) SPROM is erased/programmed if SPUEN is set to 0 289 * | | |(5) SPROM is programmed at SPROM secured mode. 290 * | | |(6) Page Erase command at LOCK mode with ICE connection 291 * | | |(7) Erase or Program command at brown-out detected 292 * | | |(8) Destination address is illegal, such as over an available range. 293 * | | |(9) Invalid ISP commands 294 * | | |(10) Vector address is mapping to SPROM region. 295 * |[4] |D0 |ISP DATA 0 Flag (Read Only) 296 * | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete. 297 * | | |0 = FMC_MPDAT0 register is empty, or program to flash complete. 298 * | | |1 = FMC_MPDAT0 register has been written, and not program to flash complete. 299 * |[5] |D1 |ISP DATA 1 Flag (Read Only) 300 * | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete. 301 * | | |0 = FMC_MPDAT1 register is empty, or program to flash complete. 302 * | | |1 = FMC_MPDAT1 register has been written, and not program to flash complete. 303 * |[6] |D2 |ISP DATA 2 Flag (Read Only) 304 * | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete. 305 * | | |0 = FMC_MPDAT2 register is empty, or program to flash complete. 306 * | | |1 = FMC_MPDAT2 register has been written, and not program to flash complete. 307 * |[7] |D3 |ISP DATA 3 Flag (Read Only) 308 * | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete. 309 * | | |0 = FMC_MPDAT3 register is empty, or program to flash complete. 310 * | | |1 = FMC_MPDAT3 register has been written, and not program to flash complete. 311 * @var FMC_T::MPADDR 312 * Offset: 0xC4 ISP Multi-Program Address Register 313 * --------------------------------------------------------------------------------------------------- 314 * |Bits |Field |Descriptions 315 * | :----: | :----: | :---- | 316 * |[31:0] |MPADDR |ISP Multi-word Program Address 317 * | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1. 318 * | | |MPADDR will keep the final ISP address when ISP multi-word program is complete. 319 * @var FMC_T::XOMR0STS 320 * Offset: 0xD0 XOM Region 0 Status Register 321 * --------------------------------------------------------------------------------------------------- 322 * |Bits |Field |Descriptions 323 * | :----: | :----: | :---- | 324 * |[7:0] |SIZE |XOM Region 0 Size (Page-aligned) 325 * | | |SIZE is the page number of XOM Region 0. 326 * |[31:8] |BASE |XOM Region 0 Base Address (Page-aligned) 327 * | | |BASE is the base address of XOM Region 0. 328 * @var FMC_T::XOMR1STS 329 * Offset: 0xD4 XOM Region 1 Status Register 330 * --------------------------------------------------------------------------------------------------- 331 * |Bits |Field |Descriptions 332 * | :----: | :----: | :---- | 333 * |[7:0] |SIZE |XOM Region 1 Size (Page-aligned) 334 * | | |SIZE is the page number of XOM Region 1. 335 * |[31:8] |BASE |XOM Region 1 Base Address (Page-aligned) 336 * | | |BASE is the base address of XOM Region 1. 337 * @var FMC_T::XOMR2STS 338 * Offset: 0xD8 XOM Region 2 Status Register 339 * --------------------------------------------------------------------------------------------------- 340 * |Bits |Field |Descriptions 341 * | :----: | :----: | :---- | 342 * |[7:0] |SIZE |XOM Region 2 Size (Page-aligned) 343 * | | |SIZE is the page number of XOM Region 2. 344 * |[31:8] |BASE |XOM Region 2 Base Address (Page-aligned) 345 * | | |BASE is the base address of XOM Region 2. 346 * @var FMC_T::XOMR3STS 347 * Offset: 0xDC XOM Region 3 Status Register 348 * --------------------------------------------------------------------------------------------------- 349 * |Bits |Field |Descriptions 350 * | :----: | :----: | :---- | 351 * |[7:0] |SIZE |XOM Region 3 Size (Page-aligned) 352 * | | |SIZE is the page number of XOM Region 3. 353 * |[31:8] |BASE |XOM Region 3 Base Address (Page-aligned) 354 * | | |BASE is the base address of XOM Region 3. 355 * @var FMC_T::XOMSTS 356 * Offset: 0xE0 XOM Status Register 357 * --------------------------------------------------------------------------------------------------- 358 * |Bits |Field |Descriptions 359 * | :----: | :----: | :---- | 360 * |[0] |XOMR0ON |XOM Region 0 On 361 * | | |XOM Region 0 active status. 362 * | | |0 = No active. 363 * | | |1 = XOM region 0 is active. 364 * |[1] |XOMR1ON |XOM Region 1 On 365 * | | |XOM Region 1 active status. 366 * | | |0 = No active. 367 * | | |1 = XOM region 1 is active. 368 * |[2] |XOMR2ON |XOM Region 2 On 369 * | | |XOM Region 2 active status. 370 * | | |0 = No active. 371 * | | |1 = XOM region 2 is active. 372 * |[3] |XOMR3ON |XOM Region 3 On 373 * | | |XOM Region 3 active status. 374 * | | |0 = No active. 375 * | | |1 = XOM region 3 is active. 376 * |[4] |XOMPEF |XOM Page Erase Function Fail 377 * | | |XOM page erase function status. If XOMPEF is set to 1, user needs to erase XOM region again. 378 * | | |0 = Success. 379 * | | |1 = Fail. 380 * @var FMC_T::APPROT 381 * Offset: 0x110 APROM Protect Register 382 * --------------------------------------------------------------------------------------------------- 383 * |Bits |Field |Descriptions 384 * | :----: | :----: | :---- | 385 * |[n] |APPROENn |APROM Proect enable 386 * | n=0,1..| |This bit indicates which APROM region is protected. 387 * | ..31 | |0 = APROM region n is not protected. 388 * | | |1 = APROM region n is protected. 389 * | | |Note: APROM protect region is 0x0 + n*(0x8000) to 0x7fff + n*(0x8000) 390 */ 391 392 __IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */ 393 __IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */ 394 __IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */ 395 __IO uint32_t ISPCMD; /*!< [0x000c] ISP Command Register */ 396 __IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */ 397 __I uint32_t DFBA; /*!< [0x0014] Data Flash Base Address */ 398 /// @cond HIDDEN_SYMBOLS 399 __I uint32_t RESERVE0[10]; 400 /// @endcond //HIDDEN_SYMBOLS 401 __IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */ 402 /// @cond HIDDEN_SYMBOLS 403 __I uint32_t RESERVE1[2]; 404 /// @endcond //HIDDEN_SYMBOLS 405 __IO uint32_t CYCCTL; /*!< [0x004c] Flash Access Cycle Control Register */ 406 /// @cond HIDDEN_SYMBOLS 407 __I uint32_t RESERVE2[12]; 408 /// @endcond //HIDDEN_SYMBOLS 409 __IO uint32_t MPDAT0; /*!< [0x0080] ISP Data0 Register */ 410 __IO uint32_t MPDAT1; /*!< [0x0084] ISP Data1 Register */ 411 __IO uint32_t MPDAT2; /*!< [0x0088] ISP Data2 Register */ 412 __IO uint32_t MPDAT3; /*!< [0x008c] ISP Data3 Register */ 413 /// @cond HIDDEN_SYMBOLS 414 __I uint32_t RESERVE3[12]; 415 /// @endcond //HIDDEN_SYMBOLS 416 __I uint32_t MPSTS; /*!< [0x00c0] ISP Multi-Program Status Register */ 417 __I uint32_t MPADDR; /*!< [0x00c4] ISP Multi-Program Address Register */ 418 /// @cond HIDDEN_SYMBOLS 419 __I uint32_t RESERVE4[2]; 420 /// @endcond //HIDDEN_SYMBOLS 421 __I uint32_t XOMR0STS; /*!< [0x00d0] XOM Region 0 Status Register */ 422 __I uint32_t XOMR1STS; /*!< [0x00d4] XOM Region 1 Status Register */ 423 __I uint32_t XOMR2STS; /*!< [0x00d8] XOM Region 2 Status Register */ 424 __I uint32_t XOMR3STS; /*!< [0x00dc] XOM Region 3 Status Register */ 425 __I uint32_t XOMSTS; /*!< [0x00e0] XOM Status Register */ 426 __I uint32_t RESERVE5[11]; 427 __IO uint32_t APPROT; /*!< [0x0110] XOM Status Register */ 428 429 } FMC_T; 430 431 /** 432 @addtogroup FMC_CONST FMC Bit Field Definition 433 Constant Definitions for FMC Controller 434 @{ */ 435 436 #define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */ 437 #define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */ 438 439 #define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */ 440 #define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */ 441 442 #define FMC_ISPCTL_SPUEN_Pos (2) /*!< FMC_T::ISPCTL: SPUEN Position */ 443 #define FMC_ISPCTL_SPUEN_Msk (0x1ul << FMC_ISPCTL_SPUEN_Pos) /*!< FMC_T::ISPCTL: SPUEN Mask */ 444 445 #define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */ 446 #define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */ 447 448 #define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */ 449 #define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */ 450 451 #define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */ 452 #define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */ 453 454 #define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */ 455 #define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */ 456 457 #define FMC_ISPCTL_BL_Pos (16) /*!< FMC_T::ISPCTL: BL Position */ 458 #define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos) /*!< FMC_T::ISPCTL: BL Mask */ 459 460 #define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */ 461 #define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */ 462 463 #define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */ 464 #define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */ 465 466 #define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */ 467 #define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */ 468 469 #define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */ 470 #define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */ 471 472 #define FMC_DFBA_DFBA_Pos (0) /*!< FMC_T::DFBA: DFBA Position */ 473 #define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) /*!< FMC_T::DFBA: DFBA Mask */ 474 475 #define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */ 476 #define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */ 477 478 #define FMC_ISPSTS_CBS_Pos (1) /*!< FMC_T::ISPSTS: CBS Position */ 479 #define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */ 480 481 #define FMC_ISPSTS_MBS_Pos (3) /*!< FMC_T::ISPSTS: MBS Position */ 482 #define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) /*!< FMC_T::ISPSTS: MBS Mask */ 483 484 #define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */ 485 #define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */ 486 487 #define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */ 488 #define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */ 489 490 #define FMC_ISPSTS_ALLONE_Pos (7) /*!< FMC_T::ISPSTS: ALLONE Position */ 491 #define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) /*!< FMC_T::ISPSTS: ALLONE Mask */ 492 493 #define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */ 494 #define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */ 495 496 #define FMC_ISPSTS_INTFLAG_Pos (24) /*!< FMC_T::ISPSTS: INTFLAG Position */ 497 #define FMC_ISPSTS_INTFLAG_Msk (0x01ul << FMC_ISPSTS_INTFLAG_Pos) /*!< FMC_T::ISPSTS: INTFLAG Position */ 498 499 #define FMC_ISPSTS_ISPCERR_Pos (28) /*!< FMC_T::ISPSTS: ISPCERR Position */ 500 #define FMC_ISPSTS_ISPCERR_Msk (0x01ul << FMC_ISPSTS_ISPCERR_Pos) /*!< FMC_T::ISPSTS: ISPCERR Position */ 501 502 #define FMC_ISPSTS_FBS_Pos (30) /*!< FMC_T::ISPSTS: FBS Position */ 503 #define FMC_ISPSTS_FBS_Msk (0x1ul << FMC_ISPSTS_FBS_Pos) /*!< FMC_T::ISPSTS: FBS Msk */ 504 505 #define FMC_CYCCTL_CYCLE_Pos (0) /*!< FMC_T::CYCCTL: CYCLE Position */ 506 #define FMC_CYCCTL_CYCLE_Msk (0xful << FMC_CYCCTL_CYCLE_Pos) /*!< FMC_T::CYCCTL: CYCLE Mask */ 507 508 #define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */ 509 #define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */ 510 511 #define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */ 512 #define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */ 513 514 #define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */ 515 #define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */ 516 517 #define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */ 518 #define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */ 519 520 #define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */ 521 #define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */ 522 523 #define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */ 524 #define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */ 525 526 #define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */ 527 #define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */ 528 529 #define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */ 530 #define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */ 531 532 #define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */ 533 #define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */ 534 535 #define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */ 536 #define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */ 537 538 #define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */ 539 #define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */ 540 541 #define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */ 542 #define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */ 543 544 #define FMC_XOMR0STS_SIZE_Pos (0) /*!< FMC_T::XOMR0STS: SIZE Position */ 545 #define FMC_XOMR0STS_SIZE_Msk (0xfful << FMC_XOMR0STS_SIZE_Pos) /*!< FMC_T::XOMR0STS: SIZE Mask */ 546 547 #define FMC_XOMR0STS_BASE_Pos (8) /*!< FMC_T::XOMR0STS: BASE Position */ 548 #define FMC_XOMR0STS_BASE_Msk (0xfffffful << FMC_XOMR0STS_BASE_Pos) /*!< FMC_T::XOMR0STS: BASE Mask */ 549 550 #define FMC_XOMR1STS_SIZE_Pos (0) /*!< FMC_T::XOMR1STS: SIZE Position */ 551 #define FMC_XOMR1STS_SIZE_Msk (0xfful << FMC_XOMR1STS_SIZE_Pos) /*!< FMC_T::XOMR1STS: SIZE Mask */ 552 553 #define FMC_XOMR1STS_BASE_Pos (8) /*!< FMC_T::XOMR1STS: BASE Position */ 554 #define FMC_XOMR1STS_BASE_Msk (0xfffffful << FMC_XOMR1STS_BASE_Pos) /*!< FMC_T::XOMR1STS: BASE Mask */ 555 556 #define FMC_XOMR2STS_SIZE_Pos (0) /*!< FMC_T::XOMR2STS: SIZE Position */ 557 #define FMC_XOMR2STS_SIZE_Msk (0xfful << FMC_XOMR2STS_SIZE_Pos) /*!< FMC_T::XOMR2STS: SIZE Mask */ 558 559 #define FMC_XOMR2STS_BASE_Pos (8) /*!< FMC_T::XOMR2STS: BASE Position */ 560 #define FMC_XOMR2STS_BASE_Msk (0xfffffful << FMC_XOM20STS_BASE_Pos) /*!< FMC_T::XOMR2STS: BASE Mask */ 561 562 #define FMC_XOMR3STS_SIZE_Pos (0) /*!< FMC_T::XOMR3STS: SIZE Position */ 563 #define FMC_XOMR3STS_SIZE_Msk (0xfful << FMC_XOMR3STS_SIZE_Pos) /*!< FMC_T::XOMR3STS: SIZE Mask */ 564 565 #define FMC_XOMR3STS_BASE_Pos (8) /*!< FMC_T::XOMR3STS: BASE Position */ 566 #define FMC_XOMR3STS_BASE_Msk (0xfffffful << FMC_XOMR3STS_BASE_Pos) /*!< FMC_T::XOMR3STS: BASE Mask */ 567 568 #define FMC_XOMSTS_XOMR0ON_Pos (0) /*!< FMC_T::XOMSTS: XOMR0ON Position */ 569 #define FMC_XOMSTS_XOMR0ON_Msk (0x1ul << FMC_XOMSTS_XOMR0ON_Pos) /*!< FMC_T::XOMSTS: XOMR0ON Mask */ 570 571 #define FMC_XOMSTS_XOMR1ON_Pos (1) /*!< FMC_T::XOMSTS: XOMR1ON Position */ 572 #define FMC_XOMSTS_XOMR1ON_Msk (0x1ul << FMC_XOMSTS_XOMR1ON_Pos) /*!< FMC_T::XOMSTS: XOMR1ON Mask */ 573 574 #define FMC_XOMSTS_XOMR2ON_Pos (2) /*!< FMC_T::XOMSTS: XOMR2ON Position */ 575 #define FMC_XOMSTS_XOMR2ON_Msk (0x1ul << FMC_XOMSTS_XOMR2ON_Pos) /*!< FMC_T::XOMSTS: XOMR2ON Mask */ 576 577 #define FMC_XOMSTS_XOMR3ON_Pos (3) /*!< FMC_T::XOMSTS: XOMR3ON Position */ 578 #define FMC_XOMSTS_XOMR3ON_Msk (0x1ul << FMC_XOMSTS_XOMR3ON_Pos) /*!< FMC_T::XOMSTS: XOMR3ON Mask */ 579 580 #define FMC_XOMSTS_XOMPEF_Pos (4) /*!< FMC_T::XOMSTS: XOMPEF Position */ 581 #define FMC_XOMSTS_XOMPEF_Msk (0x1ul << FMC_XOMSTS_XOMPEF_Pos) /*!< FMC_T::XOMSTS: XOMPEF Mask */ 582 583 #define FMC_APPROT_APPROEN0_Pos (0) /*!< FMC_T::APPROT: APPROEN0 Position */ 584 #define FMC_APPROT_APPROEN0_Msk (0x1ul << FMC_APPROT_APPROEN0_Pos) /*!< FMC_T::APPROT: APPROEN0 Mask */ 585 586 #define FMC_APPROT_APPROEN1_Pos (1) /*!< FMC_T::APPROT: APPROEN1 Position */ 587 #define FMC_APPROT_APPROEN1_Msk (0x1ul << FMC_APPROT_APPROEN1_Pos) /*!< FMC_T::APPROT: APPROEN1 Mask */ 588 589 #define FMC_APPROT_APPROEN2_Pos (2) /*!< FMC_T::APPROT: APPROEN2 Position */ 590 #define FMC_APPROT_APPROEN2_Msk (0x1ul << FMC_APPROT_APPROEN2_Pos) /*!< FMC_T::APPROT: APPROEN2 Mask */ 591 592 #define FMC_APPROT_APPROEN3_Pos (3) /*!< FMC_T::APPROT: APPROEN3 Position */ 593 #define FMC_APPROT_APPROEN3_Msk (0x1ul << FMC_APPROT_APPROEN3_Pos) /*!< FMC_T::APPROT: APPROEN3 Mask */ 594 595 #define FMC_APPROT_APPROEN4_Pos (4) /*!< FMC_T::APPROT: APPROEN4 Position */ 596 #define FMC_APPROT_APPROEN4_Msk (0x1ul << FMC_APPROT_APPROEN4_Pos) /*!< FMC_T::APPROT: APPROEN4 Mask */ 597 598 #define FMC_APPROT_APPROEN5_Pos (5) /*!< FMC_T::APPROT: APPROEN5 Position */ 599 #define FMC_APPROT_APPROEN5_Msk (0x1ul << FMC_APPROT_APPROEN5_Pos) /*!< FMC_T::APPROT: APPROEN5 Mask */ 600 601 #define FMC_APPROT_APPROEN6_Pos (6) /*!< FMC_T::APPROT: APPROEN6 Position */ 602 #define FMC_APPROT_APPROEN6_Msk (0x1ul << FMC_APPROT_APPROEN6_Pos) /*!< FMC_T::APPROT: APPROEN6 Mask */ 603 604 #define FMC_APPROT_APPROEN7_Pos (7) /*!< FMC_T::APPROT: APPROEN7 Position */ 605 #define FMC_APPROT_APPROEN7_Msk (0x1ul << FMC_APPROT_APPROEN7_Pos) /*!< FMC_T::APPROT: APPROEN7 Mask */ 606 607 #define FMC_APPROT_APPROEN8_Pos (8) /*!< FMC_T::APPROT: APPROEN8 Position */ 608 #define FMC_APPROT_APPROEN8_Msk (0x1ul << FMC_APPROT_APPROEN8_Pos) /*!< FMC_T::APPROT: APPROEN8 Mask */ 609 610 #define FMC_APPROT_APPROEN9_Pos (9) /*!< FMC_T::APPROT: APPROEN9 Position */ 611 #define FMC_APPROT_APPROEN9_Msk (0x1ul << FMC_APPROT_APPROEN9_Pos) /*!< FMC_T::APPROT: APPROEN9 Mask */ 612 613 #define FMC_APPROT_APPROEN10_Pos (10) /*!< FMC_T::APPROT: APPROEN10 Position */ 614 #define FMC_APPROT_APPROEN10_Msk (0x1ul << FMC_APPROT_APPROEN10_Pos) /*!< FMC_T::APPROT: APPROEN10 Mask */ 615 616 #define FMC_APPROT_APPROEN11_Pos (11) /*!< FMC_T::APPROT: APPROEN11 Position */ 617 #define FMC_APPROT_APPROEN11_Msk (0x1ul << FMC_APPROT_APPROEN11_Pos) /*!< FMC_T::APPROT: APPROEN11 Mask */ 618 619 #define FMC_APPROT_APPROEN12_Pos (12) /*!< FMC_T::APPROT: APPROEN12 Position */ 620 #define FMC_APPROT_APPROEN12_Msk (0x1ul << FMC_APPROT_APPROEN12_Pos) /*!< FMC_T::APPROT: APPROEN12 Mask */ 621 622 #define FMC_APPROT_APPROEN13_Pos (13) /*!< FMC_T::APPROT: APPROEN13 Position */ 623 #define FMC_APPROT_APPROEN13_Msk (0x1ul << FMC_APPROT_APPROEN13_Pos) /*!< FMC_T::APPROT: APPROEN13 Mask */ 624 625 #define FMC_APPROT_APPROEN14_Pos (14) /*!< FMC_T::APPROT: APPROEN14 Position */ 626 #define FMC_APPROT_APPROEN14_Msk (0x1ul << FMC_APPROT_APPROEN14_Pos) /*!< FMC_T::APPROT: APPROEN14 Mask */ 627 628 #define FMC_APPROT_APPROEN15_Pos (15) /*!< FMC_T::APPROT: APPROEN15 Position */ 629 #define FMC_APPROT_APPROEN15_Msk (0x1ul << FMC_APPROT_APPROEN15_Pos) /*!< FMC_T::APPROT: APPROEN15 Mask */ 630 631 #define FMC_APPROT_APPROEN16_Pos (16) /*!< FMC_T::APPROT: APPROEN16 Position */ 632 #define FMC_APPROT_APPROEN16_Msk (0x1ul << FMC_APPROT_APPROEN16_Pos) /*!< FMC_T::APPROT: APPROEN16 Mask */ 633 634 #define FMC_APPROT_APPROEN17_Pos (17) /*!< FMC_T::APPROT: APPROEN17 Position */ 635 #define FMC_APPROT_APPROEN17_Msk (0x1ul << FMC_APPROT_APPROEN17_Pos) /*!< FMC_T::APPROT: APPROEN17 Mask */ 636 637 #define FMC_APPROT_APPROEN18_Pos (18) /*!< FMC_T::APPROT: APPROEN18 Position */ 638 #define FMC_APPROT_APPROEN18_Msk (0x1ul << FMC_APPROT_APPROEN18_Pos) /*!< FMC_T::APPROT: APPROEN18 Mask */ 639 640 #define FMC_APPROT_APPROEN19_Pos (19) /*!< FMC_T::APPROT: APPROEN19 Position */ 641 #define FMC_APPROT_APPROEN19_Msk (0x1ul << FMC_APPROT_APPROEN19_Pos) /*!< FMC_T::APPROT: APPROEN19 Mask */ 642 643 #define FMC_APPROT_APPROEN20_Pos (20) /*!< FMC_T::APPROT: APPROEN20 Position */ 644 #define FMC_APPROT_APPROEN20_Msk (0x1ul << FMC_APPROT_APPROEN20_Pos) /*!< FMC_T::APPROT: APPROEN20 Mask */ 645 646 #define FMC_APPROT_APPROEN21_Pos (21) /*!< FMC_T::APPROT: APPROEN21 Position */ 647 #define FMC_APPROT_APPROEN21_Msk (0x1ul << FMC_APPROT_APPROEN21_Pos) /*!< FMC_T::APPROT: APPROEN21 Mask */ 648 649 #define FMC_APPROT_APPROEN22_Pos (22) /*!< FMC_T::APPROT: APPROEN22 Position */ 650 #define FMC_APPROT_APPROEN22_Msk (0x1ul << FMC_APPROT_APPROEN22_Pos) /*!< FMC_T::APPROT: APPROEN22 Mask */ 651 652 #define FMC_APPROT_APPROEN23_Pos (23) /*!< FMC_T::APPROT: APPROEN23 Position */ 653 #define FMC_APPROT_APPROEN23_Msk (0x1ul << FMC_APPROT_APPROEN23_Pos) /*!< FMC_T::APPROT: APPROEN23 Mask */ 654 655 #define FMC_APPROT_APPROEN24_Pos (24) /*!< FMC_T::APPROT: APPROEN24 Position */ 656 #define FMC_APPROT_APPROEN24_Msk (0x1ul << FMC_APPROT_APPROEN24_Pos) /*!< FMC_T::APPROT: APPROEN24 Mask */ 657 658 #define FMC_APPROT_APPROEN25_Pos (25) /*!< FMC_T::APPROT: APPROEN25 Position */ 659 #define FMC_APPROT_APPROEN25_Msk (0x1ul << FMC_APPROT_APPROEN25_Pos) /*!< FMC_T::APPROT: APPROEN25 Mask */ 660 661 #define FMC_APPROT_APPROEN26_Pos (26) /*!< FMC_T::APPROT: APPROEN26 Position */ 662 #define FMC_APPROT_APPROEN26_Msk (0x1ul << FMC_APPROT_APPROEN26_Pos) /*!< FMC_T::APPROT: APPROEN26 Mask */ 663 664 #define FMC_APPROT_APPROEN27_Pos (27) /*!< FMC_T::APPROT: APPROEN27 Position */ 665 #define FMC_APPROT_APPROEN27_Msk (0x1ul << FMC_APPROT_APPROEN27_Pos) /*!< FMC_T::APPROT: APPROEN27 Mask */ 666 667 #define FMC_APPROT_APPROEN28_Pos (28) /*!< FMC_T::APPROT: APPROEN28 Position */ 668 #define FMC_APPROT_APPROEN28_Msk (0x1ul << FMC_APPROT_APPROEN28_Pos) /*!< FMC_T::APPROT: APPROEN28 Mask */ 669 670 #define FMC_APPROT_APPROEN29_Pos (29) /*!< FMC_T::APPROT: APPROEN29 Position */ 671 #define FMC_APPROT_APPROEN29_Msk (0x1ul << FMC_APPROT_APPROEN29_Pos) /*!< FMC_T::APPROT: APPROEN29 Mask */ 672 673 #define FMC_APPROT_APPROEN30_Pos (30) /*!< FMC_T::APPROT: APPROEN30 Position */ 674 #define FMC_APPROT_APPROEN30_Msk (0x1ul << FMC_APPROT_APPROEN30_Pos) /*!< FMC_T::APPROT: APPROEN30 Mask */ 675 676 #define FMC_APPROT_APPROEN31_Pos (31) /*!< FMC_T::APPROT: APPROEN31 Position */ 677 #define FMC_APPROT_APPROEN31_Msk (0x1ul << FMC_APPROT_APPROEN31_Pos) /*!< FMC_T::APPROT: APPROEN31 Mask */ 678 679 /**@}*/ /* FMC_CONST */ 680 /**@}*/ /* end of FMC register group */ 681 /**@}*/ /* end of REGISTER group */ 682 683 #if defined ( __CC_ARM ) 684 #pragma no_anon_unions 685 #endif 686 687 #endif /* __FMC_REG_H__ */ 688
