1 /**************************************************************************//** 2 * @file qei_reg.h 3 * @version V1.00 4 * @brief EQEI register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __EQEI_REG_H__ 10 #define __EQEI_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup EQEI Quadrature Encoder Interface (EQEI) 23 Memory Mapped Structure for EQEI Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var EQEI_T::CNT 32 * Offset: 0x00 EQEI Counter Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[31:0] |CNT |Quadrature Encoder Interface Counter 37 * | | |A 32-bit up/down counter 38 * | | |When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (EQEI_STATUS[8]) is one or decreased by one if the bit DIRF(EQEI_STATUS[8]) is zero 39 * | | |This register performs an integrator which count value is proportional to the encoder position 40 * | | |The pulse counter may be initialized to a predetermined value by one of three events occurs: 41 * | | |1. Software is written if EQEIEN (EQEI_CTL[29]) = 0. 42 * | | |2. Compare-match event if EQEIEN(EQEI_CTL[29])=1 and EQEI is in compare-counting mode. 43 * | | |3. Index signal change if EQEIEN(EQEI_CTL[29])=1 and IDXRLDEN (EQEI_CTL[27])=1. 44 * @var EQEI_T::CNTHOLD 45 * Offset: 0x04 EQEI Counter Hold Register 46 * --------------------------------------------------------------------------------------------------- 47 * |Bits |Field |Descriptions 48 * | :----: | :----: | :---- | 49 * |[31:0] |CNTHOLD |Quadrature Encoder Interface Counter Hold 50 * | | |When bit HOLDCNT (EQEI_CTL[24]) goes from low to high, the CNT(EQEI_CNT[31:0]) is copied into CNTHOLD (EQEI_CNTHOLD[31:0]) register. 51 * @var EQEI_T::CNTLATCH 52 * Offset: 0x08 EQEI Counter Index Latch Register 53 * --------------------------------------------------------------------------------------------------- 54 * |Bits |Field |Descriptions 55 * | :----: | :----: | :---- | 56 * |[31:0] |CNTLATCH |Quadrature Encoder Interface Counter Index Latch 57 * | | |When the IDXF (EQEI_STATUS[0]) bit is set, the CNT(EQEI_CNT[31:0]) is copied into CNTLATCH (EQEI_CNTLATCH[31:0]) register. 58 * @var EQEI_T::CNTCMP 59 * Offset: 0x0C EQEI Counter Compare Register 60 * --------------------------------------------------------------------------------------------------- 61 * |Bits |Field |Descriptions 62 * | :----: | :----: | :---- | 63 * |[31:0] |CNTCMP |Quadrature Encoder Interface Counter Compare 64 * | | |If the EQEI controller is in the compare-counting mode CMPEN (EQEI_CTL[28]) =1, when the value of CNT(EQEI_CNT[31:0]) matches CNTCMP(EQEI_CNTCMP[31:0]), CMPF will be set 65 * | | |This register is software writable. 66 * @var EQEI_T::CNTMAX 67 * Offset: 0x14 EQEI Pre-set Maximum Count Register 68 * --------------------------------------------------------------------------------------------------- 69 * |Bits |Field |Descriptions 70 * | :----: | :----: | :---- | 71 * |[31:0] |CNTMAX |Quadrature Encoder Interface Preset Maximum Count 72 * | | |This register value determined by user stores the maximum value which may be the number of the EQEI counter for the EQEI controller compare-counting mode 73 * @var EQEI_T::CTL 74 * Offset: 0x18 EQEI Controller Control Register 75 * --------------------------------------------------------------------------------------------------- 76 * |Bits |Field |Descriptions 77 * | :----: | :----: | :---- | 78 * |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection 79 * | | |To determine the sampling frequency of the Noise Filter clock . 80 * | | |000 = EQEI_CLK. 81 * | | |001 = EQEI_CLK/2. 82 * | | |010 = EQEI_CLK/4. 83 * | | |011 = EQEI_CLK/16. 84 * | | |100 = EQEI_CLK/32. 85 * | | |101 = EQEI_CLK/64. 86 * |[3] |NFDIS |QEI Controller Input Noise Filter Disable Bit 87 * | | |0 = The noise filter of EQEI controller Enabled. 88 * | | |1 = The noise filter of EQEI controller Disabled. 89 * |[4] |CHAEN |QEA Input to EQEI Controller Enable Bit 90 * | | |0 = QEA input to EQEI Controller Disabled. 91 * | | |1 = QEA input to EQEI Controller Enabled. 92 * |[5] |CHBEN |QEB Input to EQEI Controller Enable Bit 93 * | | |0 = QEB input to EQEI Controller Disabled. 94 * | | |1 = QEB input to EQEI Controller Enabled. 95 * |[6] |IDXEN |IDX Input to EQEI Controller Enable Bit 96 * | | |0 = IDX input to EQEI Controller Disabled. 97 * | | |1 = IDX input to EQEI Controller Enabled. 98 * |[7] |IDXRSTEN |IDX Reset EQEI Position Counter Enable Bit 99 * | | |0 = Reset EQEI position counter in every time IDX signal. 100 * | | |1 = Reset EQEI position counter in first time IDX signal. 101 * | | |Note: IDXRLDEN(EQEI_CTL[27]) should be set 1. 102 * |[10:8] |MODE |QEI Counting Mode Selection 103 * | | |There are seven quadrature encoder pulse counter operation modes. 104 * | | |000 = X4 Free-counting Mode. 105 * | | |001 = X2 Free-counting Mode. 106 * | | |010 = X4 Compare-counting Mode. 107 * | | |011 = X2 Compare-counting Mode. 108 * | | |100 = Phase Counting Mode Type 1. (PCMT1). 109 * | | |101 = Phase Counting Mode Type 2. (PCMT2). 110 * | | |110 = Directional Counting Mode. 111 * | | |111 = Reserved. 112 * | | |Note: User needs to set DIRSRC(EQEI_CTL2[5:4]) when MODE(EQEI_CTL[10:8]) selects to directional counting mode. 113 * |[12] |CHAINV |Inverse QEA Input Polarity 114 * | | |0 = Not inverse QEA input polarity. 115 * | | |1 = QEA input polarity is inversed to EQEI controller. 116 * |[13] |CHBINV |Inverse QEB Input Polarity 117 * | | |0 = Not inverse QEB input polarity. 118 * | | |1 = QEB input polarity is inversed to EQEI controller. 119 * |[14] |IDXINV |Inverse IDX Input Polarity 120 * | | |0 = Not inverse IDX input polarity. 121 * | | |1 = IDX input polarity is inversed to EQEI controller. 122 * |[15] |IDXRSTEV |IDX Signal Resets Enable Bit in First IDX Reset Event (Write Only) 123 * | | |0 = The next IDX level high signal reset function is disabled. 124 * | | |1 = The next IDX level high signal reset function is enabled. 125 * | | |Note: This bit only effective when IDXRSTEN (EQEI_CTL[7])=1 and IDXRLDEN (EQEI_CTL[27])=1. 126 * |[16] |OVUNIEN |OVUNF Trigger EQEI Interrupt Enable Bit 127 * | | |0 = OVUNF can trigger EQEI controller interrupt Disabled. 128 * | | |1 = OVUNF can trigger EQEI controller interrupt Enabled. 129 * |[17] |DIRIEN |DIRCHGF Trigger EQEI Interrupt Enable Bit 130 * | | |0 = DIRCHGF can trigger EQEI controller interrupt Disabled. 131 * | | |1 = DIRCHGF can trigger EQEI controller interrupt Enabled. 132 * |[18] |CMPIEN |CMPF Trigger EQEI Interrupt Enable Bit 133 * | | |0 = CMPF can trigger EQEI controller interrupt Disabled. 134 * | | |1 = CMPF can trigger EQEI controller interrupt Enabled. 135 * |[19] |IDXIEN |IDXF Trigger EQEI Interrupt Enable Bit 136 * | | |0 = The IDXF can trigger EQEI interrupt Disabled. 137 * | | |1 = The IDXF can trigger EQEI interrupt Enabled. 138 * |[20] |HOLDTMR0 |Hold EQEI_CNT by Timer 0 139 * | | |0 = TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT. 140 * | | |1 = A rising edge of bit TIF(TIMER0_INTSTS[0]) in timer 0 sets HOLDCNT to 1. 141 * |[21] |HOLDTMR1 |Hold EQEI_CNT by Timer 1 142 * | | |0 = TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT. 143 * | | |1 = A rising edge of bit TIF (TIMER1_INTSTS[0]) in timer 1 sets HOLDCNT to 1. 144 * |[22] |HOLDTMR2 |Hold EQEI_CNT by Timer 2 145 * | | |0 = TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT. 146 * | | |1 = A rising edge of bit TIF(TIMER2_INTSTS[0]) in timer 2 sets HOLDCNT to 1. 147 * |[23] |HOLDTMR3 |Hold EQEI_CNT by Timer 3 148 * | | |0 = TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT. 149 * | | |1 = A rising edge of bit TIF(TIMER3_INTSTS[0]) in timer 3 sets HOLDCNT to 1. 150 * |[24] |HOLDCNT |Hold EQEI_CNT Control 151 * | | |When this bit is set from low to high, the CNT(EQEI_CNT[31:0]) is copied into CNTHOLD(EQEI_CNTHOLD[31:0]) 152 * | | |This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]). 153 * | | |0 = No operation. 154 * | | |1 = EQEI_CNT content is captured and stored in CNTHOLD(EQEI_CNTHOLD[31:0]). 155 * | | |Note: This bit is automatically cleared after EQEI_CNTHOLD holds EQEI_CNT value. 156 * |[25] |IDXLATEN |Index Latch EQEI_CNT Enable Bit 157 * | | |If this bit is set to high, the CNT(EQEI_CNT[31:0]) content will be latched into CNTLATCH (EQEI_CNTLATCH[31:0]) at every rising on signal CHX. 158 * | | |0 = The index signal latch EQEI counter function Disabled. 159 * | | |1 = The index signal latch EQEI counter function Enabled. 160 * |[27] |IDXRLDEN |Index Trigger EQEI_CNT Reload Enable Bit 161 * | | |When this bit is high and a rising edge comes on signal CHX, the CNT(EQEI_CNT[31:0]) will be reset to zero if the counter is in up-counting type (DIRF(EQEI_STATUS[8]) = 1); while the CNT(EQEI_CNT[31:0]) will be reloaded with CNTMAX (EQEI_CNTMAX[31:0]) content if the counter is in down-counting type (DIRF(EQEI_STATUS[8]) = 0). 162 * | | |0 = Reload function Disabled. 163 * | | |1 = EQEI_CNT re-initialized by Index signal Enabled. 164 * |[28] |CMPEN |The Compare Function Enable Bit 165 * | | |The compare function in EQEI controller is to compare the dynamic counting EQEI_CNT with the compare register CNTCMP( EQEI_CNTCMP[31:0]), if CNT(EQEI_CNT[31:0]) reaches CNTCMP( EQEI_CNTCMP[31:0]), the flag CMPF will be set. 166 * | | |0 = Compare function Disabled. 167 * | | |1 = Compare function Enabled. 168 * |[29] |EQEIEN |Enhanced Quadrature Encoder Interface Controller Enable Bit 169 * | | |0 = EQEI controller function Disabled. 170 * | | |1 = EQEI controller function Enabled. 171 * @var EQEI_T::CTL2 172 * Offset: 0x1C EQEI Controller Control Register2 173 * --------------------------------------------------------------------------------------------------- 174 * |Bits |Field |Descriptions 175 * | :----: | :----: | :---- | 176 * |[0] |SWAPEN |Swap Function Enable Bit 177 * | | |0 = EQEI swap function Disabled. 178 * | | |1 = EQEI swap function Enabled. 179 * |[2:1] |CRS |Clock Rate Setting without Quadrature Mode 180 * | | |00 = EQEI counter only counts the falling edge. 181 * | | |01 = EQEI counter only counts the rising edge. 182 * | | |10 = EQEI counter counts the rising and falling edge. 183 * | | |11 = reserved. 184 * |[5:4] |DIRSRC |Direction Signal Source Select 185 * | | |00 = Direction signal is determined from EQEI system calculation. 186 * | | |01 = reserved. 187 * | | |10 = Direction signal is tied 1 only for direction up count mode. 188 * | | |11 = Direction signal is tied 0 only for down count mode. 189 * |[8] |UTEN |Unit Timer Function Enable Bit 190 * | | |0 = EQEI unit timer function is disable. 191 * | | |1 = EQEI unit timer function is enable. 192 * |[9] |UTHOLDEN |Unit Timer Counter Hold Enable Bit 193 * | | |0 = No operation. 194 * | | |1 = EQEI_CNT content is captured and stored in CNTHOLD(EQEI_CNTHOLD[31:0]) when UTCNT matches UTCMP(EQEI_UTCMP[31:0]). 195 * |[10] |UTEVTRST |Enable Bit to Reset EQEI Position Counter by Unit Timer Event 196 * | | |0 = Disable to reset EQEI position counter feature when unit timer counter event occurs. 197 * | | |1 = Enable to reset EQEI position counter feature when unit timer counter event occurs. 198 * |[11] |IDXRSTUTS |IDX Resets Unit Timer Select Bit 199 * | | |0 = Unit timer will not be reset when IDX reset event happens. 200 * | | |1 = Resets unit timer or not will follow EQEI_CNT when IDX reset event happens. 201 * |[16] |PHEIEN |PHEF Trigger EQEI Interrupt Enable Bit 202 * | | |0 = PHEF can trigger EQEI controller interrupt Disabled. 203 * | | |1 = PHEF can trigger EQEI controller interrupt Enabled. 204 * |[17] |UTIEIEN |UTIEF Trigger EQEI Interrupt Enable Bit 205 * | | |0 = UTIEF can trigger EQEI controller interrupt Disabled. 206 * | | |1 = UTIEF can trigger EQEI controller interrupt Enabled. 207 * @var EQEI_T::UTCNT 208 * Offset: 0x20 EQEI Unit Timer Counter Register 209 * --------------------------------------------------------------------------------------------------- 210 * |Bits |Field |Descriptions 211 * | :----: | :----: | :---- | 212 * |[31:0] |UTCNT |Unit Timer Counter 213 * | | |A 32-bit unit timer counter which may be reset to an initial value when any of the following events occur: 214 * | | |1. Software is written if UTEN (EQEI_CTL2[8]) = 0. 215 * | | |2. UT_EN (EQEI_CTL2[8]) =1, and the unit timer counter value matches UTCMP(EQEI_UTCMP[31:0]). 216 * | | |3. IDXRLDEN(EQEI_CTL[27]) =1 and IDXRSTUTS(EQEI_CTL2[11]=1, determine the unit timer to be reset or not will follow EQEI_CNT when IDX reset event happens. 217 * @var EQEI_T::UTCMP 218 * Offset: 0x24 EQEI Unit Timer Compare Register 219 * --------------------------------------------------------------------------------------------------- 220 * |Bits |Field |Descriptions 221 * | :----: | :----: | :---- | 222 * |[31:0] |UTCMP |Unit Timer Counter Compare 223 * | | |If the EQEI unit timer is enable (EQEI_CTL2[8]) =1, and the unit timer counter value also matches UTCMP(EQEI_UTCMP[31:0]), then UTIEF (EQEI_STATUS[10]) will be set. This register is software writable. 224 * @var EQEI_T::STATUS 225 * Offset: 0x2C EQEI Controller Status Register 226 * --------------------------------------------------------------------------------------------------- 227 * |Bits |Field |Descriptions 228 * | :----: | :----: | :---- | 229 * |[0] |IDXF |IDX Detected Flag 230 * | | |When the EQEI controller detects a rising edge on signal CHX it will set flag IDXF to high. 231 * | | |0 = No rising edge detected on signal CHX. 232 * | | |1 = A rising edge occurs on signal CHX. 233 * | | |Note: This bit is only cleared by writing 1 to it. 234 * |[1] |CMPF |Compare-match Flag 235 * | | |If the EQEI compare function is enabled, the flag is set by hardware while EQEI counter up or down counts and reach to the CNTCMP(EQEI_CNTCMP[31:0]). 236 * | | |0 = EQEI counter does not match with CNTCMP(EQEI_CNTCMP[31:0]). 237 * | | |1 = EQEI counter counts to the same as CNTCMP(EQEI_CNTCMP[31:0]). 238 * | | |Note: This bit is only cleared by writing 1 to it. 239 * |[2] |OVUNF |QEI Counter Overflow or Underflow Flag 240 * | | |Flag is set by hardware while CNT(EQEI_CNT[31:0]) overflows from 0xFFFF_FFFF to zero in free-counting mode or from the CNTMAX (EQEI_CNTMAX[31:0]) to zero in compare-counting mode 241 * | | |Similarly, the flag is set while EQEI counter underflows from zero to 0xFFFF_FFFF or CNTMAX (EQEI_CNTMAX[31:0]). 242 * | | |0 = No overflow or underflow occurs in EQEI counter. 243 * | | |1 = EQEI counter occurs counting overflow or underflow. 244 * | | |Note: This bit is only cleared by writing 1 to it. 245 * |[3] |DIRCHGF |Direction Change Flag 246 * | | |Flag is set by hardware while EQEI counter counting direction is changed. 247 * | | |Software can clear this bit by writing 1 to it. 248 * | | |0 = No change in EQEI counter counting direction. 249 * | | |1 = EQEI counter counting direction is changed. 250 * | | |Note: This bit is only cleared by writing 1 to it. 251 * |[8] |DIRF |QEI Counter Counting Direction Indication 252 * | | |0 = EQEI Counter is in down-counting. 253 * | | |1 = EQEI Counter is in up-counting. 254 * | | |Note: This bit is set/reset by hardware according to the phase detection between CHA and CHB. 255 * |[9] |FIDXEF |First IDX Signal Reset Event Flag (Read Only) 256 * | | |0 = The first IDX reset event has not happened yet. 257 * | | |1 = The first IDX reset event has happened. 258 * | | |Note: This bit only effective when IDXRSTEN (EQEI_CTL[7])=1 and IDXRLDEN (EQEI_CTL[27])=1. 259 * |[16] |PHEF EQEI |Phase Error Flag 260 * | | |0 = No Phase error occurs in EQEI CHA and CHB. 261 * | | |1 = Phase error occurs in EQEI CHA and CHB. 262 * | | |Note: This bit is only cleared by writing 1 to it. 263 * |[17] |UTIEF |EQEI Unit Timer Event Flag 264 * | | |0 = No timer event occurs in EQEI unit timer counter. 265 * | | |1 = Unit timer event occurs in EQEI unit timer counter. 266 * | | |Note: This bit is only cleared by writing 1 to it. 267 */ 268 __IO uint32_t CNT; /*!< [0x0000] EQEI Counter Register */ 269 __IO uint32_t CNTHOLD; /*!< [0x0004] EQEI Counter Hold Register */ 270 __IO uint32_t CNTLATCH; /*!< [0x0008] EQEI Counter Index Latch Register */ 271 __IO uint32_t CNTCMP; /*!< [0x000c] EQEI Counter Compare Register */ 272 /// @cond HIDDEN_SYMBOLS 273 __I uint32_t RESERVE0[1]; 274 /// @endcond //HIDDEN_SYMBOLS 275 __IO uint32_t CNTMAX; /*!< [0x0014] EQEI Pre-set Maximum Count Register */ 276 __IO uint32_t CTL; /*!< [0x0018] EQEI Controller Control Register */ 277 __IO uint32_t CTL2; /*!< [0x001C] EQEI Controller Control Register2 */ 278 __IO uint32_t UTCNT; /*!< [0x0020] EQEI Unit Timer Counter Register */ 279 __IO uint32_t UTCMP; /*!< [0x0024] EQEI Unit Timer Compare Register */ 280 /// @cond HIDDEN_SYMBOLS 281 __I uint32_t RESERVE1[1]; 282 /// @endcond //HIDDEN_SYMBOLS 283 __IO uint32_t STATUS; /*!< [0x002c] EQEI Controller Status Register */ 284 285 } EQEI_T; 286 287 /** 288 @addtogroup EQEI_CONST EQEI Bit Field Definition 289 Constant Definitions for EQEI Controller 290 @{ */ 291 292 #define EQEI_CNT_CNT_Pos (0) /*!< EQEI_T::CNT: CNT Position */ 293 #define EQEI_CNT_CNT_Msk (0xfffffffful << EQEI_CNT_CNT_Pos) /*!< EQEI_T::CNT: CNT Mask */ 294 295 #define EQEI_CNTHOLD_CNTHOLD_Pos (0) /*!< EQEI_T::CNTHOLD: CNTHOLD Position */ 296 #define EQEI_CNTHOLD_CNTHOLD_Msk (0xfffffffful << EQEI_CNTHOLD_CNTHOLD_Pos) /*!< EQEI_T::CNTHOLD: CNTHOLD Mask */ 297 298 #define EQEI_CNTLATCH_CNTLATCH_Pos (0) /*!< EQEI_T::CNTLATCH: CNTLATCH Position */ 299 #define EQEI_CNTLATCH_CNTLATCH_Msk (0xfffffffful << EQEI_CNTLATCH_CNTLATCH_Pos) /*!< EQEI_T::CNTLATCH: CNTLATCH Mask */ 300 301 #define EQEI_CNTCMP_CNTCMP_Pos (0) /*!< EQEI_T::CNTCMP: CNTCMP Position */ 302 #define EQEI_CNTCMP_CNTCMP_Msk (0xfffffffful << EQEI_CNTCMP_CNTCMP_Pos) /*!< EQEI_T::CNTCMP: CNTCMP Mask */ 303 304 #define EQEI_CNTMAX_CNTMAX_Pos (0) /*!< EQEI_T::CNTMAX: CNTMAX Position */ 305 #define EQEI_CNTMAX_CNTMAX_Msk (0xfffffffful << EQEI_CNTMAX_CNTMAX_Pos) /*!< EQEI_T::CNTMAX: CNTMAX Mask */ 306 307 #define EQEI_CTL_NFCLKSEL_Pos (0) /*!< EQEI_T::CTL: NFCLKSEL Position */ 308 #define EQEI_CTL_NFCLKSEL_Msk (0x7ul << EQEI_CTL_NFCLKSEL_Pos) /*!< EQEI_T::CTL: NFCLKSEL Mask */ 309 310 #define EQEI_CTL_NFDIS_Pos (3) /*!< EQEI_T::CTL: NFDIS Position */ 311 #define EQEI_CTL_NFDIS_Msk (0x1ul << EQEI_CTL_NFDIS_Pos) /*!< EQEI_T::CTL: NFDIS Mask */ 312 313 #define EQEI_CTL_CHAEN_Pos (4) /*!< EQEI_T::CTL: CHAEN Position */ 314 #define EQEI_CTL_CHAEN_Msk (0x1ul << EQEI_CTL_CHAEN_Pos) /*!< EQEI_T::CTL: CHAEN Mask */ 315 316 #define EQEI_CTL_CHBEN_Pos (5) /*!< EQEI_T::CTL: CHBEN Position */ 317 #define EQEI_CTL_CHBEN_Msk (0x1ul << EQEI_CTL_CHBEN_Pos) /*!< EQEI_T::CTL: CHBEN Mask */ 318 319 #define EQEI_CTL_IDXEN_Pos (6) /*!< EQEI_T::CTL: IDXEN Position */ 320 #define EQEI_CTL_IDXEN_Msk (0x1ul << EQEI_CTL_IDXEN_Pos) /*!< EQEI_T::CTL: IDXEN Mask */ 321 322 #define EQEI_CTL_IDXRSTEN_Pos (7) /*!< EQEI_T::CTL: IDXRSTEN Position */ 323 #define EQEI_CTL_IDXRSTEN_Msk (0x1ul << EQEI_CTL_IDXRSTEN_Pos) /*!< EQEI_T::CTL: IDXRSTEN Mask */ 324 325 #define EQEI_CTL_MODE_Pos (8) /*!< EQEI_T::CTL: MODE Position */ 326 #define EQEI_CTL_MODE_Msk (0x7ul << EQEI_CTL_MODE_Pos) /*!< EQEI_T::CTL: MODE Mask */ 327 328 #define EQEI_CTL_CHAINV_Pos (12) /*!< EQEI_T::CTL: CHAINV Position */ 329 #define EQEI_CTL_CHAINV_Msk (0x1ul << EQEI_CTL_CHAINV_Pos) /*!< EQEI_T::CTL: CHAINV Mask */ 330 331 #define EQEI_CTL_CHBINV_Pos (13) /*!< EQEI_T::CTL: CHBINV Position */ 332 #define EQEI_CTL_CHBINV_Msk (0x1ul << EQEI_CTL_CHBINV_Pos) /*!< EQEI_T::CTL: CHBINV Mask */ 333 334 #define EQEI_CTL_IDXINV_Pos (14) /*!< EQEI_T::CTL: IDXINV Position */ 335 #define EQEI_CTL_IDXINV_Msk (0x1ul << EQEI_CTL_IDXINV_Pos) /*!< EQEI_T::CTL: IDXINV Mask */ 336 337 #define EQEI_CTL_IDXRSTEV_Pos (15) /*!< EQEI_T::CTL: IDXRSTEV Position */ 338 #define EQEI_CTL_IDXRSTEV_Msk (0x1ul << EQEI_CTL_IDXRSTEV_Pos) /*!< EQEI_T::CTL: IDXRSTEV Mask */ 339 340 #define EQEI_CTL_OVUNIEN_Pos (16) /*!< EQEI_T::CTL: OVUNIEN Position */ 341 #define EQEI_CTL_OVUNIEN_Msk (0x1ul << EQEI_CTL_OVUNIEN_Pos) /*!< EQEI_T::CTL: OVUNIEN Mask */ 342 343 #define EQEI_CTL_DIRIEN_Pos (17) /*!< EQEI_T::CTL: DIRIEN Position */ 344 #define EQEI_CTL_DIRIEN_Msk (0x1ul << EQEI_CTL_DIRIEN_Pos) /*!< EQEI_T::CTL: DIRIEN Mask */ 345 346 #define EQEI_CTL_CMPIEN_Pos (18) /*!< EQEI_T::CTL: CMPIEN Position */ 347 #define EQEI_CTL_CMPIEN_Msk (0x1ul << EQEI_CTL_CMPIEN_Pos) /*!< EQEI_T::CTL: CMPIEN Mask */ 348 349 #define EQEI_CTL_IDXIEN_Pos (19) /*!< EQEI_T::CTL: IDXIEN Position */ 350 #define EQEI_CTL_IDXIEN_Msk (0x1ul << EQEI_CTL_IDXIEN_Pos) /*!< EQEI_T::CTL: IDXIEN Mask */ 351 352 #define EQEI_CTL_HOLDTMR0_Pos (20) /*!< EQEI_T::CTL: HOLDTMR0 Position */ 353 #define EQEI_CTL_HOLDTMR0_Msk (0x1ul << EQEI_CTL_HOLDTMR0_Pos) /*!< EQEI_T::CTL: HOLDTMR0 Mask */ 354 355 #define EQEI_CTL_HOLDTMR1_Pos (21) /*!< EQEI_T::CTL: HOLDTMR1 Position */ 356 #define EQEI_CTL_HOLDTMR1_Msk (0x1ul << EQEI_CTL_HOLDTMR1_Pos) /*!< EQEI_T::CTL: HOLDTMR1 Mask */ 357 358 #define EQEI_CTL_HOLDTMR2_Pos (22) /*!< EQEI_T::CTL: HOLDTMR2 Position */ 359 #define EQEI_CTL_HOLDTMR2_Msk (0x1ul << EQEI_CTL_HOLDTMR2_Pos) /*!< EQEI_T::CTL: HOLDTMR2 Mask */ 360 361 #define EQEI_CTL_HOLDTMR3_Pos (23) /*!< EQEI_T::CTL: HOLDTMR3 Position */ 362 #define EQEI_CTL_HOLDTMR3_Msk (0x1ul << EQEI_CTL_HOLDTMR3_Pos) /*!< EQEI_T::CTL: HOLDTMR3 Mask */ 363 364 #define EQEI_CTL_HOLDCNT_Pos (24) /*!< EQEI_T::CTL: HOLDCNT Position */ 365 #define EQEI_CTL_HOLDCNT_Msk (0x1ul << EQEI_CTL_HOLDCNT_Pos) /*!< EQEI_T::CTL: HOLDCNT Mask */ 366 367 #define EQEI_CTL_IDXLATEN_Pos (25) /*!< EQEI_T::CTL: IDXLATEN Position */ 368 #define EQEI_CTL_IDXLATEN_Msk (0x1ul << EQEI_CTL_IDXLATEN_Pos) /*!< EQEI_T::CTL: IDXLATEN Mask */ 369 370 #define EQEI_CTL_IDXRLDEN_Pos (27) /*!< EQEI_T::CTL: IDXRLDEN Position */ 371 #define EQEI_CTL_IDXRLDEN_Msk (0x1ul << EQEI_CTL_IDXRLDEN_Pos) /*!< EQEI_T::CTL: IDXRLDEN Mask */ 372 373 #define EQEI_CTL_CMPEN_Pos (28) /*!< EQEI_T::CTL: CMPEN Position */ 374 #define EQEI_CTL_CMPEN_Msk (0x1ul << EQEI_CTL_CMPEN_Pos) /*!< EQEI_T::CTL: CMPEN Mask */ 375 376 #define EQEI_CTL_QEIEN_Pos (29) /*!< EQEI_T::CTL: EQEIEN Position */ 377 #define EQEI_CTL_QEIEN_Msk (0x1ul << EQEI_CTL_QEIEN_Pos) /*!< EQEI_T::CTL: EQEIEN Mask */ 378 379 #define EQEI_CTL2_SWAPEN_Pos (0) /*!< EQEI_T::CTL2: SWAPEN Position */ 380 #define EQEI_CTL2_SWAPEN_Msk (0x1ul << EQEI_CTL2_SWAPEN_Pos) /*!< EQEI_T::CTL2: SWAPEN Mask */ 381 382 #define EQEI_CTL2_CRS_Pos (1) /*!< EQEI_T::CTL2: CRS Position */ 383 #define EQEI_CTL2_CRS_Msk (0x3ul << EQEI_CTL2_CRS_Pos) /*!< EQEI_T::CTL2: CRS Mask */ 384 385 #define EQEI_CTL2_DIRSRC_Pos (4) /*!< EQEI_T::CTL2: DIRSRC Position */ 386 #define EQEI_CTL2_DIRSRC_Msk (0x3ul << EQEI_CTL2_DIRSRC_Pos) /*!< EQEI_T::CTL2: DIRSRC Mask */ 387 388 #define EQEI_CTL2_UTEN_Pos (8) /*!< EQEI_T::CTL2: UTEN Position */ 389 #define EQEI_CTL2_UTEN_Msk (0x1ul << EQEI_CTL2_UTEN_Pos) /*!< EQEI_T::CTL2: UTEN Mask */ 390 391 #define EQEI_CTL2_UTHOLDEN_Pos (9) /*!< EQEI_T::CTL2: UTHOLDEN Position */ 392 #define EQEI_CTL2_UTHOLDEN_Msk (0x1ul << EQEI_CTL2_UTHOLDEN_Pos) /*!< EQEI_T::CTL2: UTHOLDEN Mask */ 393 394 #define EQEI_CTL2_UTEVTRST_Pos (10) /*!< EQEI_T::CTL2: UTEVTRST Position */ 395 #define EQEI_CTL2_UTEVTRST_Msk (0x1ul << EQEI_CTL2_UTEVTRST_Pos) /*!< EQEI_T::CTL2: UTEVTRST Mask */ 396 397 #define EQEI_CTL2_IDXRSTUTS_Pos (11) /*!< EQEI_T::CTL2: IDXRSTUTS Position */ 398 #define EQEI_CTL2_IDXRSTUTS_Msk (0x1ul << EQEI_CTL2_IDXRSTUTS_Pos) /*!< EQEI_T::CTL2: IDXRSTUTS Mask */ 399 400 #define EQEI_CTL2_PHEIEN_Pos (16) /*!< EQEI_T::CTL2: PHEIEN Position */ 401 #define EQEI_CTL2_PHEIEN_Msk (0x1ul << EQEI_CTL2_PHEIEN_Pos) /*!< EQEI_T::CTL2: PHEIEN Mask */ 402 403 #define EQEI_CTL2_UTIEIEN_Pos (17) /*!< EQEI_T::CTL2: UTIEIEN Position */ 404 #define EQEI_CTL2_UTIEIEN_Msk (0x1ul << EQEI_CTL2_UTIEIEN_Pos) /*!< EQEI_T::CTL2: UTIEIEN Mask */ 405 406 #define EQEI_UTCNT_UTCNT_Pos (0) /*!< EQEI_T::UTCNT: UTCNT Position */ 407 #define EQEI_UTCNT_UTCNT_Msk (0xfffffffful << EQEI_UTCNT_UTCNT_Pos) /*!< EQEI_T::UTCNT: UTCNT Mask */ 408 409 #define EQEI_UTCMP_UTCMP_Pos (0) /*!< EQEI_T::UTCMP: UTCMP Position */ 410 #define EQEI_UTCMP_UTCMP_Msk (0xfffffffful << EQEI_UTCMP_UTCMP_Pos) /*!< EQEI_T::UTCMP: UTCMP Mask */ 411 412 #define EQEI_STATUS_IDXF_Pos (0) /*!< EQEI_T::STATUS: IDXF Position */ 413 #define EQEI_STATUS_IDXF_Msk (0x1ul << EQEI_STATUS_IDXF_Pos) /*!< EQEI_T::STATUS: IDXF Mask */ 414 415 #define EQEI_STATUS_CMPF_Pos (1) /*!< EQEI_T::STATUS: CMPF Position */ 416 #define EQEI_STATUS_CMPF_Msk (0x1ul << EQEI_STATUS_CMPF_Pos) /*!< EQEI_T::STATUS: CMPF Mask */ 417 418 #define EQEI_STATUS_OVUNF_Pos (2) /*!< EQEI_T::STATUS: OVUNF Position */ 419 #define EQEI_STATUS_OVUNF_Msk (0x1ul << EQEI_STATUS_OVUNF_Pos) /*!< EQEI_T::STATUS: OVUNF Mask */ 420 421 #define EQEI_STATUS_DIRCHGF_Pos (3) /*!< EQEI_T::STATUS: DIRCHGF Position */ 422 #define EQEI_STATUS_DIRCHGF_Msk (0x1ul << EQEI_STATUS_DIRCHGF_Pos) /*!< EQEI_T::STATUS: DIRCHGF Mask */ 423 424 #define EQEI_STATUS_DIRF_Pos (8) /*!< EQEI_T::STATUS: DIRF Position */ 425 #define EQEI_STATUS_DIRF_Msk (0x1ul << EQEI_STATUS_DIRF_Pos) /*!< EQEI_T::STATUS: DIRF Mask */ 426 427 #define EQEI_STATUS_FIDXEF_Pos (9) /*!< EQEI_T::STATUS: FIDXEF Position */ 428 #define EQEI_STATUS_FIDXEF_Msk (0x1ul << EQEI_STATUS_FIDXEF_Pos) /*!< EQEI_T::STATUS: FIDXEF Mask */ 429 430 #define EQEI_STATUS_PHEF_Pos (16) /*!< EQEI_T::STATUS: PHEF Position */ 431 #define EQEI_STATUS_PHEF_Msk (0x1ul << EQEI_STATUS_PHEF_Pos) /*!< EQEI_T::STATUS: PHEF Mask */ 432 433 #define EQEI_STATUS_UTIEF_Pos (17) /*!< EQEI_T::STATUS: UTIEF Position */ 434 #define EQEI_STATUS_UTIEF_Msk (0x1ul << EQEI_STATUS_UTIEF_Pos) /*!< EQEI_T::STATUS: UTIEF Mask */ 435 436 437 /**@}*/ /* EQEI_CONST */ 438 /**@}*/ /* end of EQEI register group */ 439 /**@}*/ /* end of REGISTER group */ 440 441 #if defined ( __CC_ARM ) 442 #pragma no_anon_unions 443 #endif 444 445 #endif /* __EQEI_REG_H__ */ 446
