1 /**************************************************************************//** 2 * @file eadc_reg.h 3 * @version V1.00 4 * @brief EADC register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __EADC_REG_H__ 10 #define __EADC_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /*---------------------- Enhanced Analog to Digital Converter -------------------------*/ 22 /** 23 @addtogroup EADC Enhanced Analog to Digital Converter (EADC) 24 Memory Mapped Structure for EADC Controller 25 @{ */ 26 27 typedef struct 28 { 29 30 31 /** 32 * @var EADC_T::DAT[19] 33 * Offset: 0x00 EADC Data Register 0~18 for Sample Module 0~18 34 * --------------------------------------------------------------------------------------------------- 35 * |Bits |Field |Descriptions 36 * | :----: | :----: | :---- | 37 * |[15:0] |RESULT |EADC Conversion Result 38 * | | |This field contains 12 bits conversion result. 39 * | | |The 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]. 40 * | | |Note: When operating in oversampling mode, RESULT[15:0] can represent oversampling results. 41 * |[16] |OV |Overrun Flag 42 * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. 43 * | | |0 = Data in RESULT[11:0] is recent conversion result. 44 * | | |1 = Data in RESULT[11:0] is overwrite. 45 * | | |Note: It is cleared by hardware after EADC_DAT register is read. 46 * |[17] |VALID |Valid Flag 47 * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. 48 * | | |0 = Data in RESULT[11:0] bits is not valid. 49 * | | |1 = Data in RESULT[11:0] bits is valid. 50 * @var EADC_T::CURDAT 51 * Offset: 0x4C ADC PDMA Current Transfer Data Register 52 * --------------------------------------------------------------------------------------------------- 53 * |Bits |Field |Descriptions 54 * | :----: | :----: | :---- | 55 * |[18:0] |CURDAT |EADC PDMA Current Transfer Data (Read Only) 56 * | | |This register is a shadow register of EADC_DATn (n=0~18) for PDMA support. 57 * @var EADC_T::CTL 58 * Offset: 0x50 EADC Control Register 59 * --------------------------------------------------------------------------------------------------- 60 * |Bits |Field |Descriptions 61 * | :----: | :----: | :---- | 62 * |[0] |ADCEN |EADC Converter Enable Bit 63 * | | |0 = EADC Disabled. 64 * | | |1 = EADC Enabled. 65 * | | |Note: Before starting EADC conversion function, this bit should be set to 1 66 * | | |Clear it to 0 to disable EADC converter analog circuit power consumption. 67 * |[1] |ADCRST |EADC Converter Control Circuits Reset 68 * | | |0 = No effect. 69 * | | |1 = Cause EADC control circuits reset to initial state, but not change the EADC registers value. 70 * | | |Note: EADCRST bit remains 1 during EADC reset, when EADC reset end, the EADCRST bit is automatically cleared to 0. 71 * |[2] |ADCIEN0 |Specific Sample Module EADC ADINT0 Interrupt Enable Bit 72 * | | |The EADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module EADC conversion 73 * | | |If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated. 74 * | | |0 = Specific sample module EADC ADINT0 interrupt function Disabled. 75 * | | |1 = Specific sample module EADC ADINT0 interrupt function Enabled. 76 * |[3] |ADCIEN1 |Specific Sample Module EADC ADINT1 Interrupt Enable Bit 77 * | | |The EADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module EADC conversion 78 * | | |If EADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated. 79 * | | |0 = Specific sample module EADC ADINT1 interrupt function Disabled. 80 * | | |1 = Specific sample module EADC ADINT1 interrupt function Enabled. 81 * |[4] |ADCIEN2 |Specific Sample Module EADC ADINT2 Interrupt Enable Bit 82 * | | |The EADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module EADC conversion 83 * | | |If EADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated. 84 * | | |0 = Specific sample module EADC ADINT2 interrupt function Disabled. 85 * | | |1 = Specific sample module EADC ADINT2 interrupt function Enabled. 86 * |[5] |ADCIEN3 |Specific Sample Module EADC ADINT3 Interrupt Enable Bit 87 * | | |The EADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module EADC conversion 88 * | | |If EADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated. 89 * | | |0 = Specific sample module EADC ADINT3 interrupt function Disabled. 90 * | | |1 = Specific sample module EADC ADINT3 interrupt function Enabled. 91 * |[8] |DIFFEN |Differential Analog Input Mode Enable Bit 92 * | | |0 = Single-end analog input mode. 93 * | | |1 = Differential analog input mode. 94 * | | |Note: In the differential mode, the input channel pair must be configured to EADC_CHx, EADC_CHx+1 , x=0,2,4,6,8,10,12,14. 95 * |[9] |DMOF |ADC Differential Input Mode Output Format 96 * | | |0 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0], where n= 0 ~18) with unsigned format. 97 * | | |1 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0], where n= 0 ~18) with 2'complement format. 98 * |[19:16] |INTDELAY0 |ADC Start Of Conversion ADINT0 Delay Cycle Selection 99 * | | |Start of conversion interrupt ADINT0 will delay INTDELAY0 PCLK cycles to generate interrupt 100 * | | |The function supports delay 1 PCLK to 15 PCLK cycles 101 * | | |User can select one of the options according to the relationship of PCLK and ADC _CLK selected. 102 * | | |4u2019h0 = No delay cycle. 103 * | | |4u2019h1 = Start of conversion interrupt ADINT0 delay 1 PCLK cycle. 104 * | | |4u2019h2 = Start of conversion interrupt ADINT0 delay 2 PCLK cycles. 105 * | | |4u2019h3 = Start of conversion interrupt ADINT0 delay 3 PCLK cycles. 106 * | | |4u2019h4 = Start of conversion interrupt ADINT0 delay 4 PCLK cycles. 107 * | | |4u2019h5 = Start of conversion interrupt ADINT0 delay 5 PCLK cycles. 108 * | | |4u2019h6 = Start of conversion interrupt ADINT0 delay 6 PCLK cycles. 109 * | | |4u2019h7 = Start of conversion interrupt ADINT0 delay 7 PCLK cycles. 110 * | | |4u2019h8 = Start of conversion interrupt ADINT0 delay 8 PCLK cycles. 111 * | | |4u2019h9 = Start of conversion interrupt ADINT0 delay 9 PCLK cycles. 112 * | | |4u2019ha = Start of conversion interrupt ADINT0 delay 10 PCLK cycles. 113 * | | |4u2019hb = Start of conversion interrupt ADINT0 delay 11 PCLK cycles. 114 * | | |4u2019hc = Start of conversion interrupt ADINT0 delay 12 PCLK cycles. 115 * | | |4u2019hd = Start of conversion interrupt ADINT0 delay 13 PCLK cycles. 116 * | | |4u2019he = Start of conversion interrupt ADINT0 delay 14 PCLK cycles. 117 * | | |4u2019hf = Start of conversion interrupt ADINT0 delay 15 PCLK cycles. 118 * | | |Note 1: This function is workable only when any one of INTPOS (EADC_SCTLx[5]), x=0~15 is set. 119 * | | |Note 2: It is noted that the delayed interrupt ADINT0 must occur before the next ADINT0 generated when using the same sample module to control EADC conversion. 120 * |[23:20] |INTDELAY1 |ADC Start Of Conversion ADINT1 Delay Cycle Selection 121 * | | |Start of conversion interrupt ADINT1 will delay INTDELAY1 PCLK cycles to generate interrupt 122 * | | |The function supports delay 1 PCLK to 15 PCLK cycles 123 * | | |User can select one of the options according to the relationship of PCLK and ADC _CLK selected. 124 * | | |4u2019h0 = No delay cycle. 125 * | | |4u2019h1 = Start of conversion interrupt ADINT1 delay 1 PCLK cycle. 126 * | | |4u2019h2 = Start of conversion interrupt ADINT1 delay 2 PCLK cycles. 127 * | | |4u2019h3 = Start of conversion interrupt ADINT1 delay 3 PCLK cycles. 128 * | | |4u2019h4 = Start of conversion interrupt ADINT1 delay 4 PCLK cycles. 129 * | | |4u2019h5 = Start of conversion interrupt ADINT1 delay 5 PCLK cycles. 130 * | | |4u2019h6 = Start of conversion interrupt ADINT1 delay 6 PCLK cycles. 131 * | | |4u2019h7 = Start of conversion interrupt ADINT1 delay 7 PCLK cycles. 132 * | | |4u2019h8 = Start of conversion interrupt ADINT1 delay 8 PCLK cycles. 133 * | | |4u2019h9 = Start of conversion interrupt ADINT1 delay 9 PCLK cycles. 134 * | | |4u2019ha = Start of conversion interrupt ADINT1 delay 10 PCLK cycles. 135 * | | |4u2019hb = Start of conversion interrupt ADINT1 delay 11 PCLK cycles. 136 * | | |4u2019hc = Start of conversion interrupt ADINT1 delay 12 PCLK cycles. 137 * | | |4u2019hd = Start of conversion interrupt ADINT1 delay 13 PCLK cycles. 138 * | | |4u2019he = Start of conversion interrupt ADINT1 delay 14 PCLK cycles. 139 * | | |4u2019hf = Start of conversion interrupt ADINT1 delay 15 PCLK cycles. 140 * | | |Note 1: This function is workable only when any one of INTPOS (EADC_SCTLx[5]), x=0~15 is set. 141 * | | |Note 2: It is noted that the delayed interrupt ADINT1 must occur before the next ADINT1 generated when using the same sample module to control EADC conversion. 142 * |[27:24] |INTDELAY2 |ADC Start Of Conversion ADINT2 Delay Cycle Selection 143 * | | |Start of conversion interrupt ADINT2 will delay INTDELAY2 PCLK cycles to generate interrupt 144 * | | |The function supports delay 1 PCLK to 15 PCLK cycles 145 * | | |User can select one of the options according to the relationship of PCLK and ADC _CLK selected. 146 * | | |4u2019h0 = No delay cycle. 147 * | | |4u2019h1 = Start of conversion interrupt ADINT2 delay 1 PCLK cycle. 148 * | | |4u2019h2 = Start of conversion interrupt ADINT2 delay 2 PCLK cycles. 149 * | | |4u2019h3 = Start of conversion interrupt ADINT2 delay 3 PCLK cycles. 150 * | | |4u2019h4 = Start of conversion interrupt ADINT2 delay 4 PCLK cycles. 151 * | | |4u2019h5 = Start of conversion interrupt ADINT2 delay 5 PCLK cycles. 152 * | | |4u2019h6 = Start of conversion interrupt ADINT2 delay 6 PCLK cycles. 153 * | | |4u2019h7 = Start of conversion interrupt ADINT2 delay 7 PCLK cycles. 154 * | | |4u2019h8 = Start of conversion interrupt ADINT2 delay 8 PCLK cycles. 155 * | | |4u2019h9 = Start of conversion interrupt ADINT2 delay 9 PCLK cycles. 156 * | | |4u2019ha = Start of conversion interrupt ADINT2 delay 10 PCLK cycles. 157 * | | |4u2019hb = Start of conversion interrupt ADINT2 delay 11 PCLK cycles. 158 * | | |4u2019hc = Start of conversion interrupt ADINT2 delay 12 PCLK cycles. 159 * | | |4u2019hd = Start of conversion interrupt ADINT2 delay 13 PCLK cycles. 160 * | | |4u2019he = Start of conversion interrupt ADINT2 delay 14 PCLK cycles. 161 * | | |4u2019hf = Start of conversion interrupt ADINT2 delay 15 PCLK cycles. 162 * | | |Note 1: This function is workable only when any one of INTPOS (EADC_SCTLx[5]), x=0~15 is set. 163 * | | |Note 2: It is noted that the delayed interrupt ADINT2 must occur before the next ADINT2 generated when using the same sample module to control EADC conversion. 164 * |[31:28] |INTDELAY3 |ADC Start Of Conversion ADINT3 Delay Cycle Selection 165 * | | |Start of conversion interrupt ADINT3 will delay INTDELAY3 PCLK cycles to generate interrupt 166 * | | |The function supports delay 1 PCLK to 15 PCLK cycles 167 * | | |User can select one of the options according to the relationship of PCLK and ADC _CLK selected. 168 * | | |4u2019h0 = No delay cycle. 169 * | | |4u2019h1 = Start of conversion interrupt ADINT3 delay 1 PCLK cycle. 170 * | | |4u2019h2 = Start of conversion interrupt ADINT3 delay 2 PCLK cycles. 171 * | | |4u2019h3 = Start of conversion interrupt ADINT3 delay 3 PCLK cycles. 172 * | | |4u2019h4 = Start of conversion interrupt ADINT3 delay 4 PCLK cycles. 173 * | | |4u2019h5 = Start of conversion interrupt ADINT3 delay 5 PCLK cycles. 174 * | | |4u2019h6 = Start of conversion interrupt ADINT3 delay 6 PCLK cycles. 175 * | | |4u2019h7 = Start of conversion interrupt ADINT3 delay 7 PCLK cycles. 176 * | | |4u2019h8 = Start of conversion interrupt ADINT3 delay 8 PCLK cycles. 177 * | | |4u2019h9 = Start of conversion interrupt ADINT3 delay 9 PCLK cycles. 178 * | | |4u2019ha = Start of conversion interrupt ADINT3 delay 10 PCLK cycles. 179 * | | |4u2019hb = Start of conversion interrupt ADINT3 delay 11 PCLK cycles. 180 * | | |4u2019hc = Start of conversion interrupt ADINT3 delay 12 PCLK cycles. 181 * | | |4u2019hd = Start of conversion interrupt ADINT3 delay 13 PCLK cycles. 182 * | | |4u2019he = Start of conversion interrupt ADINT3 delay 14 PCLK cycles. 183 * | | |4u2019hf = Start of conversion interrupt ADINT3 delay 15 PCLK cycles. 184 * | | |Note 1: This function is workable only when any one of INTPOS (EADC_SCTLx[5]), x=0~15 is set. 185 * | | |Note 2: It is noted that the delayed interrupt ADINT3 must occur before the next ADINT3 generated when using the same sample module to control EADC conversion. 186 * @var EADC_T::SWTRG 187 * Offset: 0x54 ADC Sample Module Software Start Register 188 * --------------------------------------------------------------------------------------------------- 189 * |Bits |Field |Descriptions 190 * | :----: | :----: | :---- | 191 * |[18:0] |SWTRG |EADC Sample Module 0~18 Software Force to Start EADC Conversion 192 * | | |0 = No effect. 193 * | | |1 = Cause an EADC conversion when the priority is given to sample module. 194 * | | |Note: After writing this register to start EADC conversion, the EADC_PENDSTS register will show which sample module will conversion 195 * | | |If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. 196 * @var EADC_T::PENDSTS 197 * Offset: 0x58 EADC Start of Conversion Pending Flag Register 198 * --------------------------------------------------------------------------------------------------- 199 * |Bits |Field |Descriptions 200 * | :----: | :----: | :---- | 201 * |[18:0] |STPF |EADC Sample Module 0~18 Start of Conversion Pending Flag 202 * | | |Read Operation: 203 * | | |0 = There is no pending conversion for sample module. 204 * | | |1 = Sample module EADC start of conversion is pending. 205 * | | |Write Operation: 206 * | | |1 = Clear pending flag & cancel the conversion for sample module. 207 * | | |Note: This bit remains 1 during pending state when the respective EADC conversion is ended 208 * | | |The STPFn (n=0~18) bit is automatically cleared to 0 209 * @var EADC_T::OVSTS 210 * Offset: 0x5C EADC Sample Module Start of Conversion Overrun Flag Register 211 * --------------------------------------------------------------------------------------------------- 212 * |Bits |Field |Descriptions 213 * | :----: | :----: | :---- | 214 * |[18:0] |SPOVF |EADC SAMPLE0~18 Overrun Flag 215 * | | |0 = No sample module event overrun. 216 * | | |1 = Indicates a new sample module event is generated while an old one event is pending. 217 * | | |Note: This bit is cleared by writing 1 to it. 218 * @var EADC_T::CTL1 219 * Offset: 0x60 EADC Control1 Register 220 * --------------------------------------------------------------------------------------------------- 221 * |Bits |Field |Descriptions 222 * | :----: | :----: | :---- | 223 * |[5:4] |RESSEL |Resolution Select Bits 224 * | | |00 = ADC resolution 12 bits. 225 * | | |01 = ADC resolution 10 bits. 226 * | | |10 = ADC resolution 8 bits. 227 * | | |11 = Reserved. 228 * |[12] |ULPEN |Ultra Low Power Mode Enable Bit 229 * | | |0 = Ultra low power mode Disabled. 230 * | | |1 = Ultra low power mode Enabled. 231 * |[15:13] |ULPDIV |Ultra Low Power Mode Prescalar selection 232 * | | |000= ADC_CLK divided by 1. 233 * | | |001= ADC_CLK divided by 2. 234 * | | |010= ADC_CLK divided by 4. 235 * | | |011= ADC_CLK divided by 8. 236 * | | |100= ADC_CLK divided by 16. 237 * | | |Others = Reserved. 238 * | | |Note: the function is for internal used, itu2019s not complete function 239 * | | |Note: user set ULPEN and ULPDIV will get divided ADC_CLK only. The conversion time is still the same 240 * |[16] |DECSET |High Speed Oversampling Mode Enable Bit 241 * | | |0 = High speed oversampling mode Disabled. 242 * | | |1 = High speed oversampling mode Enabled. 243 * | | |Note: these bits is for analog RD used 244 * |[20] |CMP0TRG |ADC Comparator 0 Trigger EPWM Brake Enable Bit 245 * | | |0 = Comparator 0 trigger EPWM brake Disabled. 246 * | | |1 = Comparator 0 trigger EPWM brake Enabled. 247 * |[21] |CMP1TRG |ADC Comparator 1 Trigger EPWM Brake Enable Bit 248 * | | |0 = Comparator 1 trigger EPWM brake Disabled. 249 * | | |1 = Comparator 1 trigger EPWM brake Enabled. 250 * |[22] |CMP2TRG |ADC Comparator 2 Trigger EPWM Brake Enable Bit 251 * | | |0 = Comparator 2 trigger EPWM brake Disabled. 252 * | | |1 = Comparator 2 trigger EPWM brake Enabled. 253 * |[23] |CMP3TRG |ADC Comparator 3 Trigger EPWM Brake Enable Bit 254 * | | |0 = Comparator 3 trigger EPWM brake Disabled. 255 * | | |1 = Comparator 3 trigger EPWM brake Enabled. 256 * |[31:24] |OSR |Repeat Conversion Times Select 257 * | | |8u2019b00000000 = ADC converts for 1 time. 258 * | | |8u2019b00000001 = ADC converts for 2 times. 259 * | | |8u2019b00000010 = ADC converts for 3 times. 260 * | | |8u2019b00000011 = ADC converts for 4 times. 261 * | | |8u2019b00000100 = ADC converts for 5 times. 262 * | | |uFF1A 263 * | | |uFF1A 264 * | | |uFF1A 265 * | | |8u2019b11111101 = ADC converts for 254 times. 266 * | | |8u2019b11111110 = ADC converts for 255 times. 267 * | | |Note: The other steps of selection not listed above follow the same rule. 268 * | | |Note: these bits is for analog RD used 269 * @var EADC_T::SCTL[19] 270 * Offset: 0x80 EADC Sample Module 0~18 Control Register 271 * --------------------------------------------------------------------------------------------------- 272 * |Bits |Field |Descriptions 273 * | :----: | :----: | :---- | 274 * |[4:0] |CHSEL |EADC Sample Module Channel Selection 275 * | | |00H = EADC_CH0. 276 * | | |01H = EADC_CH1. 277 * | | |02H = EADC_CH2. 278 * | | |03H = EADC_CH3. 279 * | | |04H = EADC_CH4. 280 * | | |05H = EADC_CH5. 281 * | | |06H = EADC_CH6. 282 * | | |07H = EADC_CH7. 283 * | | |08H = EADC_CH8. 284 * | | |09H = EADC_CH9. 285 * | | |0AH = EADC_CH10. 286 * | | |0BH = EADC_CH11. 287 * | | |0CH = EADC_CH12. 288 * | | |0DH = EADC_CH13. 289 * | | |0EH = EADC_CH14. 290 * | | |0FH = EADC_CH15. 291 * |[5] |INTPOS |Interrupt Flag Position Select 292 * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at EADC end of conversion. 293 * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at EADC start of conversion. 294 * |[7:6] |TRGDLYDIV |EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection 295 * | | |Trigger delay clock frequency: 296 * | | |00 = EADC_CLK/1. 297 * | | |01 = EADC_CLK/2. 298 * | | |10 = EADC_CLK/4. 299 * | | |11 = EADC_CLK/16. 300 * |[15:8] |TRGDLYCNT |EADC Sample Module Start of Conversion Trigger Delay Time 301 * | | |Trigger delay time = TRGDLYCNT x EADC_CLK period x n (n=1,2,4,16 from TRGDLYDIV setting). 302 * |[20:16] |TRGSEL |EADC Sample Module Start of Conversion Trigger Source Selection 303 * | | |0H = Disable trigger. 304 * | | |1H = External trigger from EADC0_ST pin input. 305 * | | |2H = EADC ADINT0 interrupt EOC (End of conversion) pulse trigger. 306 * | | |3H = EADC ADINT1 interrupt EOC (End of conversion) pulse trigger. 307 * | | |4H = Timer0 overflow pulse trigger. 308 * | | |5H = Timer1 overflow pulse trigger. 309 * | | |6H = Timer2 overflow pulse trigger. 310 * | | |7H = Timer3 overflow pulse trigger. 311 * | | |8H = EPWM0TG0. 312 * | | |9H = EPWM0TG1. 313 * | | |AH = EPWM0TG2. 314 * | | |BH = EPWM0TG3. 315 * | | |CH = EPWM0TG4. 316 * | | |DH = EPWM0TG5. 317 * | | |EH = EPWM1TG0. 318 * | | |FH = EPWM1TG1. 319 * | | |10H = EPWM1TG2. 320 * | | |11H = EPWM1TG3. 321 * | | |12H = EPWM1TG4. 322 * | | |13H = EPWM1TG5. 323 * | | |14H = BPWM0TG. 324 * | | |15H = BPWM1TG. 325 * | | |other = Reserved. 326 * |[21] |EXTREN |EADC External Trigger Rising Edge Enable Bit 327 * | | |0 = Rising edge Disabled when EADC selects EADC0_ST as trigger source. 328 * | | |1 = Rising edge Enabled when EADC selects EADC0_ST as trigger source. 329 * |[22] |EXTFEN |EADC External Trigger Falling Edge Enable Bit 330 * | | |0 = Falling edge Disabled when EADC selects EADC0_ST as trigger source. 331 * | | |1 = Falling edge Enabled when EADC selects EADC0_ST as trigger source. 332 * |[23] |DBMEN |Double Buffer Mode Enable Bit 333 * | | |0 = Sample has one sample result register (default). 334 * | | |1 = Sample has two sample result registers. 335 * |[31:24] |EXTSMPT |EADC Sampling Time Extend 336 * | | |When EADC converting at high conversion rate, the sampling time of analog input voltage may not be enough if input channel loading is heavy, and user can extend EADC sampling time after trigger source is coming to get enough sampling time. 337 * | | |The range of start delay time is from 0~255 EADC clock. 338 * @var EADC_T::INTSRC[4] 339 * Offset: 0xD0 EADC interrupt 0~3 Source Enable Control Register. 340 * --------------------------------------------------------------------------------------------------- 341 * |Bits |Field |Descriptions 342 * | :----: | :----: | :---- | 343 * |[0] |SPLIE0 |Sample Module 0 Interrupt Enable Bit 344 * | | |0 = Sample Module 0 interrupt Disabled. 345 * | | |1 = Sample Module 0 interrupt Enabled. 346 * |[1] |SPLIE1 |Sample Module 1 Interrupt Enable Bit 347 * | | |0 = Sample Module 1 interrupt Disabled. 348 * | | |1 = Sample Module 1 interrupt Enabled. 349 * |[2] |SPLIE2 |Sample Module 2 Interrupt Enable Bit 350 * | | |0 = Sample Module 2 interrupt Disabled. 351 * | | |1 = Sample Module 2 interrupt Enabled. 352 * |[3] |SPLIE3 |Sample Module 3 Interrupt Enable Bit 353 * | | |0 = Sample Module 3 interrupt Disabled. 354 * | | |1 = Sample Module 3 interrupt Enabled. 355 * |[4] |SPLIE4 |Sample Module 4 Interrupt Enable Bit 356 * | | |0 = Sample Module 4 interrupt Disabled. 357 * | | |1 = Sample Module 4 interrupt Enabled. 358 * |[5] |SPLIE5 |Sample Module 5 Interrupt Enable Bit 359 * | | |0 = Sample Module 5 interrupt Disabled. 360 * | | |1 = Sample Module 5 interrupt Enabled. 361 * |[6] |SPLIE6 |Sample Module 6 Interrupt Enable Bit 362 * | | |0 = Sample Module 6 interrupt Disabled. 363 * | | |1 = Sample Module 6 interrupt Enabled. 364 * |[7] |SPLIE7 |Sample Module 7 Interrupt Enable Bit 365 * | | |0 = Sample Module 7 interrupt Disabled. 366 * | | |1 = Sample Module 7 interrupt Enabled. 367 * |[8] |SPLIE8 |Sample Module 8 Interrupt Enable Bit 368 * | | |0 = Sample Module 8 interrupt Disabled. 369 * | | |1 = Sample Module 8 interrupt Enabled. 370 * |[9] |SPLIE9 |Sample Module 9 Interrupt Enable Bit 371 * | | |0 = Sample Module 9 interrupt Disabled. 372 * | | |1 = Sample Module 9 interrupt Enabled. 373 * |[10] |SPLIE10 |Sample Module 10 Interrupt Enable Bit 374 * | | |0 = Sample Module 10 interrupt Disabled. 375 * | | |1 = Sample Module 10 interrupt Enabled. 376 * |[11] |SPLIE11 |Sample Module 11 Interrupt Enable Bit 377 * | | |0 = Sample Module 11 interrupt Disabled. 378 * | | |1 = Sample Module 11 interrupt Enabled. 379 * |[12] |SPLIE12 |Sample Module 12 Interrupt Enable Bit 380 * | | |0 = Sample Module 12 interrupt Disabled. 381 * | | |1 = Sample Module 12 interrupt Enabled. 382 * |[13] |SPLIE13 |Sample Module 13 Interrupt Enable Bit 383 * | | |0 = Sample Module 13 interrupt Disabled. 384 * | | |1 = Sample Module 13 interrupt Enabled. 385 * |[14] |SPLIE14 |Sample Module 14 Interrupt Enable Bit 386 * | | |0 = Sample Module 14 interrupt Disabled. 387 * | | |1 = Sample Module 14 interrupt Enabled. 388 * |[15] |SPLIE15 |Sample Module 15 Interrupt Enable Bit 389 * | | |0 = Sample Module 15 interrupt Disabled. 390 * | | |1 = Sample Module 15 interrupt Enabled. 391 * |[16] |SPLIE16 |Sample Module 16 Interrupt Enable Bit 392 * | | |0 = Sample Module 16 interrupt Disabled. 393 * | | |1 = Sample Module 16 interrupt Enabled. 394 * |[17] |SPLIE17 |Sample Module 17 Interrupt Enable Bit 395 * | | |0 = Sample Module 17 interrupt Disabled. 396 * | | |1 = Sample Module 17 interrupt Enabled. 397 * |[18] |SPLIE18 |Sample Module 18 Interrupt Enable Bit 398 * | | |0 = Sample Module 18 interrupt Disabled. 399 * | | |1 = Sample Module 18 interrupt Enabled. 400 * @var EADC_T::CMP[4] 401 * Offset: 0xE0 ADC Result Compare Register 0~3 402 * --------------------------------------------------------------------------------------------------- 403 * |Bits |Field |Descriptions 404 * | :----: | :----: | :---- | 405 * |[0] |ADCMPEN |EADC Result Compare Enable Bit 406 * | | |0 = Compare Disabled. 407 * | | |1 = Compare Enabled. 408 * | | |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register. 409 * |[1] |ADCMPIE |EADC Result Compare Interrupt Enable Bit 410 * | | |0 = Compare function interrupt Disabled. 411 * | | |1 = Compare function interrupt Enabled. 412 * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated. 413 * |[2] |CMPCOND |Compare Condition 414 * | | |0= Set the compare condition as that when a 12-bit EADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. 415 * | | |1= Set the compare condition as that when a 12-bit EADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. 416 * | | |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set. 417 * |[7:3] |CMPSPL |Compare Sample Module Selection 418 * | | |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared. 419 * | | |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared. 420 * | | |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared. 421 * | | |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared. 422 * | | |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared. 423 * | | |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared. 424 * | | |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared. 425 * | | |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared. 426 * | | |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared. 427 * | | |01001 = Sample Module 9 conversion result EADC_DAT9 is selected to be compared. 428 * | | |01010 = Sample Module 10 conversion result EADC_DAT10 is selected to be compared. 429 * | | |01011 = Sample Module 11 conversion result EADC_DAT11 is selected to be compared. 430 * | | |01100 = Sample Module 12 conversion result EADC_DAT12 is selected to be compared. 431 * | | |01101 = Sample Module 13 conversion result EADC_DAT13 is selected to be compared. 432 * | | |01110 = Sample Module 14 conversion result EADC_DAT14 is selected to be compared. 433 * | | |01111 = Sample Module 15 conversion result EADC_DAT15 is selected to be compared. 434 * | | |10000 = Sample Module 16 conversion result EADC_DAT16 is selected to be compared. 435 * | | |10001 = Sample Module 17 conversion result EADC_DAT17 is selected to be compared. 436 * | | |10010 = Sample Module 18 conversion result EADC_DAT18 is selected to be compared. 437 * | | |Others = reserved. 438 * |[11:8] |CMPMCNT |Compare Match Count 439 * | | |When the specified ADC sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1 440 * | | |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0 441 * | | |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set. 442 * |[15] |CMPWEN |Compare Window Mode Enable Bit 443 * | | |0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched 444 * | | |EADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched 445 * | | |1 = EADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched 446 * | | |EADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. 447 * | | |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register. 448 * | | |Note: When in compare window mode, the CMPCNT setting only follow EADC_CMP0, EADC_CMP2 registers 449 * |[27:16] |CMPDAT |Comparison Data 450 * | | |The 12 bits data is used to compare with conversion result of specified sample module 451 * | | |User can use it to monitor the external analog input pin voltage transition without imposing a load on software. 452 * @var EADC_T::STATUS0 453 * Offset: 0xF0 EADC Status Register 0 454 * --------------------------------------------------------------------------------------------------- 455 * |Bits |Field |Descriptions 456 * | :----: | :----: | :---- | 457 * |[15:0] |VALID |EADC_DAT0~15 Data Valid Flag 458 * | | |It is a mirror of VALID bit in sample module EADC result data register EADC_DATn. (n=0~15). 459 * |[31:16] |OV |EADC_DAT0~15 Overrun Flag 460 * | | |It is a mirror to OV bit in sample module EADC result data register EADC_DATn. (n=0~15). 461 * @var EADC_T::STATUS1 462 * Offset: 0xF4 EADC Status Register 1 463 * --------------------------------------------------------------------------------------------------- 464 * |Bits |Field |Descriptions 465 * | :----: | :----: | :---- | 466 * |[2:0] |VALID |EADC_DAT16~18 Data Valid Flag 467 * | | |It is a mirror of VALID bit in sample module EADC result data register EADC_DATn. (n=16~18). 468 * |[18:16] |OV |EADC_DAT16~18 Overrun Flag 469 * | | |It is a mirror to OV bit in sample module EADC result data register EADC_DATn. (n=16~18). 470 * @var EADC_T::STATUS2 471 * Offset: 0xF8 EADC Status Register 2 472 * --------------------------------------------------------------------------------------------------- 473 * |Bits |Field |Descriptions 474 * | :----: | :----: | :---- | 475 * |[0] |ADIF0 |EADC ADINT0 Interrupt Flag 476 * | | |0 = No ADINT0 interrupt pulse received. 477 * | | |1 = ADINT0 interrupt pulse has been received. 478 * | | |Note1: This bit is cleared by writing 1 to it. 479 * | | |Note 2:This bit indicates whether an EADC conversion of specific sample module has been completed 480 * |[1] |ADIF1 |EADC ADINT1 Interrupt Flag 481 * | | |0 = No ADINT1 interrupt pulse received. 482 * | | |1 = ADINT1 interrupt pulse has been received. 483 * | | |Note1: This bit is cleared by writing 1 to it. 484 * | | |Note 2:This bit indicates whether an EADC conversion of specific sample module has been completed 485 * |[2] |ADIF2 |EADC ADINT2 Interrupt Flag 486 * | | |0 = No ADINT2 interrupt pulse received. 487 * | | |1 = ADINT2 interrupt pulse has been received. 488 * | | |Note1: This bit is cleared by writing 1 to it. 489 * | | |Note 2:This bit indicates whether an EADC conversion of specific sample module has been completed 490 * |[3] |ADIF3 |EADC ADINT3 Interrupt Flag 491 * | | |0 = No ADINT3 interrupt pulse received. 492 * | | |1 = ADINT3 interrupt pulse has been received. 493 * | | |Note1: This bit is cleared by writing 1 to it. 494 * | | |Note 2:This bit indicates whether an EADC conversion of specific sample module has been completed 495 * |[4] |ADCMPF0 |EADC Compare 0 Flag 496 * | | |When the specific sample module EADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1. 497 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting. 498 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting. 499 * | | |Note: This bit is cleared by writing 1 to it. 500 * |[5] |ADCMPF1 |EADC Compare 1 Flag 501 * | | |When the specific sample module EADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1. 502 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP1 register setting. 503 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP1 register setting. 504 * | | |Note: This bit is cleared by writing 1 to it. 505 * |[6] |ADCMPF2 |EADC Compare 2 Flag 506 * | | |When the specific sample module EADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1. 507 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP2 register setting. 508 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP2 register setting. 509 * | | |Note: This bit is cleared by writing 1 to it. 510 * |[7] |ADCMPF3 |EADC Compare 3 Flag 511 * | | |When the specific sample module EADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1. 512 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP3 register setting. 513 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP3 register setting. 514 * | | |Note: This bit is cleared by writing 1 to it. 515 * |[8] |ADOVIF0 |EADC ADINT0 Interrupt Flag Overrun 516 * | | |0 = ADINT0 interrupt flag is not overwritten to 1. 517 * | | |1 = ADINT0 interrupt flag is overwritten to 1. 518 * | | |Note: This bit is cleared by writing 1 to it. 519 * |[9] |ADOVIF1 |EADC ADINT1 Interrupt Flag Overrun 520 * | | |0 = ADINT1 interrupt flag is not overwritten to 1. 521 * | | |1 = ADINT1 interrupt flag is overwritten to 1. 522 * | | |Note: This bit is cleared by writing 1 to it. 523 * |[10] |ADOVIF2 |EADC ADINT2 Interrupt Flag Overrun 524 * | | |0 = ADINT2 interrupt flag is not overwritten to 1. 525 * | | |1 = ADINT2 interrupt flag is s overwritten to 1. 526 * | | |Note: This bit is cleared by writing 1 to it. 527 * |[11] |ADOVIF3 |EADC ADINT3 Interrupt Flag Overrun 528 * | | |0 = ADINT3 interrupt flag is not overwritten to 1. 529 * | | |1 = ADINT3 interrupt flag is overwritten to 1. 530 * | | |Note: This bit is cleared by writing 1 to it. 531 * |[12] |ADCMPO0 |EADC Compare 0 Output Status (Read Only) 532 * | | |The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module 533 * | | |User can use it to monitor the external analog input pin voltage status. 534 * | | |0 = Conversion result in EADC_DAT less than CMPDAT0 setting. 535 * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT0 setting. 536 * |[13] |ADCMPO1 |EADC Compare 1 Output Status (Read Only) 537 * | | |The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module 538 * | | |User can use it to monitor the external analog input pin voltage status. 539 * | | |0 = Conversion result in EADC_DAT less than CMPDAT1 setting. 540 * | | |1 = Conversion result in EADC_DAT great than or equal to CMPDAT1 setting. 541 * |[14] |ADCMPO2 |EADC Compare 2 Output Status (Read Only) 542 * | | |The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module 543 * | | |User can use it to monitor the external analog input pin voltage status. 544 * | | |0 = Conversion result in EADC_DAT less than CMPDAT2 setting. 545 * | | |1 = Conversion result in EADC_DAT great than or equal to CMPDAT2 setting. 546 * |[15] |ADCMPO3 |EADC Compare 3 Output Status (Read Only) 547 * | | |The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module 548 * | | |User can use it to monitor the external analog input pin voltage status. 549 * | | |0 = Conversion result in EADC_DAT less than CMPDAT3 setting. 550 * | | |1 = Conversion result in EADC_DAT great than or equal to CMPDAT3 setting. 551 * |[20:16] |CHANNEL |Current Conversion Channel (Read Only) 552 * | | |This filed reflects EADC current conversion channel when BUSY=1. 553 * | | |00H = EADC_CH0. 554 * | | |01H = EADC_CH1. 555 * | | |02H = EADC_CH2. 556 * | | |03H = EADC_CH3. 557 * | | |04H = EADC_CH4. 558 * | | |05H = EADC_CH5. 559 * | | |06H = EADC_CH6. 560 * | | |07H = EADC_CH7. 561 * | | |08H = EADC_CH8. 562 * | | |09H = EADC_CH9. 563 * | | |0AH = EADC_CH10. 564 * | | |0BH = EADC_CH11. 565 * | | |0CH = EADC_CH12. 566 * | | |0DH = EADC_CH13. 567 * | | |0EH = EADC_CH14. 568 * | | |0FH = EADC_CH15. 569 * | | |10H = VBG. 570 * | | |11H = VTEMP. 571 * | | |12H = DAC0_OUT. 572 * |[23] |BUSY |Busy/Idle (Read Only) 573 * | | |0 = EADC is in idle state. 574 * | | |1 = EADC is busy at conversion. 575 * | | |Note: This flag will be high after 4*EADC_CLK cycles when the trigger source is coming. 576 * |[24] |ADOVIF |All EADC Interrupt Flag Overrun Bits Check (Read Only) 577 * | | |n=0~3. 578 * | | |0 = None of ADINT interrupt flag ADOVIFn, n=0~3 is overwritten to 1. 579 * | | |1 = Any one of ADINT interrupt flag ADOVIFn, n=0~3 is overwritten to 1. 580 * | | |Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1. 581 * |[25] |STOVF |for All EADC Sample Module Start of Conversion Overrun Flags Check (Read Only) 582 * | | |n=0~18. 583 * | | |0 = None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. 584 * | | |1 = Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. 585 * | | |Note: This bit will keep 1 when any SPOVFn Flag is equal to 1. 586 * |[26] |AVALID |for All Sample Module EADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only) 587 * | | |n=0~18. 588 * | | |0 = None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. 589 * | | |1 = Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. 590 * | | |Note: This bit will keep 1 when any VALIDn Flag is equal to 1. 591 * |[27] |AOV |for All Sample Module EADC Result Data Register Overrun Flags Check (Read Only) 592 * | | |n=0~18. 593 * | | |0 = None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. 594 * | | |1 = Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. 595 * | | |Note: This bit will keep 1 when any OVn Flag is equal to 1. 596 * @var EADC_T::STATUS3 597 * Offset: 0xFC EADC Status Register 3 598 * --------------------------------------------------------------------------------------------------- 599 * |Bits |Field |Descriptions 600 * | :----: | :----: | :---- | 601 * |[4:0] |CURSPL |EADC Current Sample Module (Read Only) 602 * | | |This register shows the current EADC is controlled by which sample module control logic modules. 603 * | | |If the EADC is Idle, the bit filed will be set to 0x1F. 604 * @var EADC_T::DDAT[4] 605 * Offset: 0x100 EADC Double Data Register 0 for Sample Module 0 606 * --------------------------------------------------------------------------------------------------- 607 * |Bits |Field |Descriptions 608 * | :----: | :----: | :---- | 609 * |[15:0] |RESULT |EADC Conversion Results 610 * | | |This field contains 12 bits conversion results. 611 * | | |The 12-bit EADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]. 612 * |[16] |OV |Overrun Flag 613 * | | |0 = Double Data in RESULT (EADC_DDATn[15:0], n=0~3) is recent conversion result. 614 * | | |1 = Double Data in RESULT (EADC_DDATn[15:0], n=0~3) is overwrite. 615 * | | |If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1 616 * | | |It is cleared by hardware after EADC_DDAT register is read. 617 * |[17] |VALID |Valid Flag 618 * | | |0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid. 619 * | | |1 = Double data in RESULT (EADC_DDATn[15:0]) is valid. 620 * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read 621 * | | |(n=0~3). 622 * @var EADC_T::CALCTL 623 * Offset: 0x114 EADC Calibration Control Register 624 * --------------------------------------------------------------------------------------------------- 625 * |Bits |Field |Descriptions 626 * | :----: | :----: | :---- | 627 * |[0] |CAL |Calibration Enable Bit 628 * | | |0 = = Calibration Disabled. 629 * | | |1 = = Calibration Enabled. 630 * | | |Note: This bit is hardware auto cleared when calibration is done 631 * |[1] |CALIE |Calibration Interrupt Enable Bit 632 * | | |0 = Calibration interrupt Disabled. 633 * | | |1= Calibration interrupt Enabled. 634 * |[2] |CALWR |Calibration Write Operation Bit for debug mode 635 * | | |0 = none. 636 * | | |1 = do calibration write operation. 637 * | | |Note: writing 1 to this bit can write CALWDATA to corresponding address CALADDR. 638 * | | |Note: this bit is hardware cleared 639 * |[3] |CALRD |Calibration Read Operation Bit for debug mode 640 * | | |0 = none. 641 * | | |1 = do calibration read operation. 642 * |[4] |OUTSEL |Calibration Output Mode Selection 643 * |[5] |CALSEL16T |Calibration Select Times Bit 644 * | | |0 = Calibration 1 times. 645 * | | |1 = Calibration 16 times (default). 646 * | | |Note: CALSEL16T shoule keep value = 1 before doing calibration. 647 * |[12:8] |CALADDR |Calibration Data Address 648 * | | |Calibration Data address in the calibration circuit, write CALADDR and corresponding sw write CALWDATA will store into the CALADDR. 649 * |[19:16] |CALSEL |Calibration Select Bits 650 * | | |0 = Calibrate offset.1. 651 * | | |1 = Calibrate MSB. 652 * | | |2 = Calibrate MSB-1. 653 * | | |3 = Calibrate MSB-2. 654 * | | |4 = Calibrate MSB-3. 655 * | | |5 = Calibrate MSB-4. 656 * | | |6 = Reserved. 657 * | | |7 = Calibrate offset.1. 658 * | | |Others = reserved. 659 * |[31:24] |CALWRDATA |Calibration Write Data 660 * | | |SW write 8-bit data into the calibration circuit to debug R/W 661 * @var EADC_T::CALSR 662 * Offset: 0x118 EADC Calibration Status Register 663 * --------------------------------------------------------------------------------------------------- 664 * |Bits |Field |Descriptions 665 * | :----: | :----: | :---- | 666 * |[11:0] |CALRDATA |Calibration Read Data 667 * | | |Read CALRDATA (EADC_CALSR[11:0]) will get CALWRDATA (EADC_CALCTL[31:24]) in the corresponding CALADDR setting . 668 * | | |Note: CALRDATA is read only 669 * | | |Note: when perform read operation, CALADDR, OUTSEL setting must be the same when perform write operation 670 * |[16] |CALIF |Calibration Finish Interrupt Flag 671 * | | |If calibration is finished, this flag will be set to 1. It is cleared by writing 1 to it. 672 * @var EADC_T::PDMACTL 673 * Offset: 0x130 EADC PDMA Control Register 674 * --------------------------------------------------------------------------------------------------- 675 * |Bits |Field |Descriptions 676 * | :----: | :----: | :---- | 677 * |[18:0] |PDMATEN |PDMA Transfer Enable Bit 678 * | | |When EADC conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request. 679 * | | |0 = PDMA data transfer Disabled. 680 * | | |1 = PDMA data transfer Enabled. 681 * | | |Note:When setting this bit field to 1, user must set ADCIENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt. 682 * @var EADC_T::M0CTL1 683 * Offset: 0x140 EADC Sample Module0 Control Register 1 684 * --------------------------------------------------------------------------------------------------- 685 * |Bits |Field |Descriptions 686 * | :----: | :----: | :---- | 687 * |[0] |ALIGN |Alignment Selection 688 * | | |0 = The conversion result will be right aligned in data register. 689 * | | |1 = The conversion result will be left aligned in data register. 690 * |[1] |AVG |Average Mode Selection 691 * | | |0 = Conversion results will be stored in data register without averaging. 692 * | | |1 = Conversion results in data register will be averaged. 693 * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). 694 * |[7:4] |ACU |Number of Accumulated Conversion Results Selection 695 * | | |0000 = 1 conversion result will be accumulated. 696 * | | |0001 = 2 conversion result will be accumulated. 697 * | | |0010 = 4 conversion result will be accumulated. 698 * | | |0011 = 8 conversion result will be accumulated. 699 * | | |0100 = 16 conversion result will be accumulated. 700 * | | |0101 = 32 conversion result will be accumulated. 701 * | | |0110 = 64 conversion result will be accumulated. 702 * | | |0111 = 128 conversion result will be accumulated. 703 * | | |1000 = 256 conversion result will be accumulated. 704 * | | |Others = Reserved. 705 * @var EADC_T::M1CTL1 706 * Offset: 0x144 EADC Sample Module1 Control Register 1 707 * --------------------------------------------------------------------------------------------------- 708 * |Bits |Field |Descriptions 709 * | :----: | :----: | :---- | 710 * |[0] |ALIGN |Alignment Selection 711 * | | |0 = The conversion result will be right aligned in data register. 712 * | | |1 = The conversion result will be left aligned in data register. 713 * |[1] |AVG |Average Mode Selection 714 * | | |0 = Conversion results will be stored in data register without averaging. 715 * | | |1 = Conversion results in data register will be averaged. 716 * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). 717 * |[7:4] |ACU |Number of Accumulated Conversion Results Selection 718 * | | |0000 = 1 conversion result will be accumulated. 719 * | | |0001 = 2 conversion result will be accumulated. 720 * | | |0010 = 4 conversion result will be accumulated. 721 * | | |0011 = 8 conversion result will be accumulated. 722 * | | |0100 = 16 conversion result will be accumulated. 723 * | | |0101 = 32 conversion result will be accumulated. 724 * | | |0110 = 64 conversion result will be accumulated. 725 * | | |0111 = 128 conversion result will be accumulated. 726 * | | |1000 = 256 conversion result will be accumulated. 727 * | | |Others = Reserved. 728 * @var EADC_T::M2CTL1 729 * Offset: 0x148 EADC Sample Module2 Control Register 1 730 * --------------------------------------------------------------------------------------------------- 731 * |Bits |Field |Descriptions 732 * | :----: | :----: | :---- | 733 * |[0] |ALIGN |Alignment Selection 734 * | | |0 = The conversion result will be right aligned in data register. 735 * | | |1 = The conversion result will be left aligned in data register. 736 * |[1] |AVG |Average Mode Selection 737 * | | |0 = Conversion results will be stored in data register without averaging. 738 * | | |1 = Conversion results in data register will be averaged. 739 * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). 740 * |[7:4] |ACU |Number of Accumulated Conversion Results Selection 741 * | | |0000 = 1 conversion result will be accumulated. 742 * | | |0001 = 2 conversion result will be accumulated. 743 * | | |0010 = 4 conversion result will be accumulated. 744 * | | |0011 = 8 conversion result will be accumulated. 745 * | | |0100 = 16 conversion result will be accumulated. 746 * | | |0101 = 32 conversion result will be accumulated. 747 * | | |0110 = 64 conversion result will be accumulated. 748 * | | |0111 = 128 conversion result will be accumulated. 749 * | | |1000 = 256 conversion result will be accumulated. 750 * | | |Others = Reserved. 751 * @var EADC_T::M3CTL1 752 * Offset: 0x14C EADC Sample Module3 Control Register 1 753 * --------------------------------------------------------------------------------------------------- 754 * |Bits |Field |Descriptions 755 * | :----: | :----: | :---- | 756 * |[0] |ALIGN |Alignment Selection 757 * | | |0 = The conversion result will be right aligned in data register. 758 * | | |1 = The conversion result will be left aligned in data register. 759 * |[1] |AVG |Average Mode Selection 760 * | | |0 = Conversion results will be stored in data register without averaging. 761 * | | |1 = Conversion results in data register will be averaged. 762 * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). 763 * |[7:4] |ACU |Number of Accumulated Conversion Results Selection 764 * | | |0000 = 1 conversion result will be accumulated. 765 * | | |0001 = 2 conversion result will be accumulated. 766 * | | |0010 = 4 conversion result will be accumulated. 767 * | | |0011 = 8 conversion result will be accumulated. 768 * | | |0100 = 16 conversion result will be accumulated. 769 * | | |0101 = 32 conversion result will be accumulated. 770 * | | |0110 = 64 conversion result will be accumulated. 771 * | | |0111 = 128 conversion result will be accumulated. 772 * | | |1000 = 256 conversion result will be accumulated. 773 * | | |Others = Reserved. 774 * @var EADC_T::M4CTL1 775 * Offset: 0x150 EADC Sample Module4 Control Register 1 776 * --------------------------------------------------------------------------------------------------- 777 * |Bits |Field |Descriptions 778 * | :----: | :----: | :---- | 779 * |[0] |ALIGN |Alignment Selection 780 * | | |0 = The conversion result will be right aligned in data register. 781 * | | |1 = The conversion result will be left aligned in data register. 782 * |[1] |AVG |Average Mode Selection 783 * | | |0 = Conversion results will be stored in data register without averaging. 784 * | | |1 = Conversion results in data register will be averaged. 785 * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). 786 * |[7:4] |ACU |Number of Accumulated Conversion Results Selection 787 * | | |0000 = 1 conversion result will be accumulated. 788 * | | |0001 = 2 conversion result will be accumulated. 789 * | | |0010 = 4 conversion result will be accumulated. 790 * | | |0011 = 8 conversion result will be accumulated. 791 * | | |0100 = 16 conversion result will be accumulated. 792 * | | |0101 = 32 conversion result will be accumulated. 793 * | | |0110 = 64 conversion result will be accumulated. 794 * | | |0111 = 128 conversion result will be accumulated. 795 * | | |1000 = 256 conversion result will be accumulated. 796 * | | |Others = Reserved. 797 * @var EADC_T::M5CTL1 798 * Offset: 0x154 EADC Sample Module5 Control Register 1 799 * --------------------------------------------------------------------------------------------------- 800 * |Bits |Field |Descriptions 801 * | :----: | :----: | :---- | 802 * |[0] |ALIGN |Alignment Selection 803 * | | |0 = The conversion result will be right aligned in data register. 804 * | | |1 = The conversion result will be left aligned in data register. 805 * |[1] |AVG |Average Mode Selection 806 * | | |0 = Conversion results will be stored in data register without averaging. 807 * | | |1 = Conversion results in data register will be averaged. 808 * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). 809 * |[7:4] |ACU |Number of Accumulated Conversion Results Selection 810 * | | |0000 = 1 conversion result will be accumulated. 811 * | | |0001 = 2 conversion result will be accumulated. 812 * | | |0010 = 4 conversion result will be accumulated. 813 * | | |0011 = 8 conversion result will be accumulated. 814 * | | |0100 = 16 conversion result will be accumulated. 815 * | | |0101 = 32 conversion result will be accumulated. 816 * | | |0110 = 64 conversion result will be accumulated. 817 * | | |0111 = 128 conversion result will be accumulated. 818 * | | |1000 = 256 conversion result will be accumulated. 819 * | | |Others = Reserved. 820 * @var EADC_T::M6CTL1 821 * Offset: 0x158 EADC Sample Module6 Control Register 1 822 * --------------------------------------------------------------------------------------------------- 823 * |Bits |Field |Descriptions 824 * | :----: | :----: | :---- | 825 * |[0] |ALIGN |Alignment Selection 826 * | | |0 = The conversion result will be right aligned in data register. 827 * | | |1 = The conversion result will be left aligned in data register. 828 * |[1] |AVG |Average Mode Selection 829 * | | |0 = Conversion results will be stored in data register without averaging. 830 * | | |1 = Conversion results in data register will be averaged. 831 * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). 832 * |[7:4] |ACU |Number of Accumulated Conversion Results Selection 833 * | | |0000 = 1 conversion result will be accumulated. 834 * | | |0001 = 2 conversion result will be accumulated. 835 * | | |0010 = 4 conversion result will be accumulated. 836 * | | |0011 = 8 conversion result will be accumulated. 837 * | | |0100 = 16 conversion result will be accumulated. 838 * | | |0101 = 32 conversion result will be accumulated. 839 * | | |0110 = 64 conversion result will be accumulated. 840 * | | |0111 = 128 conversion result will be accumulated. 841 * | | |1000 = 256 conversion result will be accumulated. 842 * | | |Others = Reserved. 843 * @var EADC_T::M7CTL1 844 * Offset: 0x15C EADC Sample Module7 Control Register 1 845 * --------------------------------------------------------------------------------------------------- 846 * |Bits |Field |Descriptions 847 * | :----: | :----: | :---- | 848 * |[0] |ALIGN |Alignment Selection 849 * | | |0 = The conversion result will be right aligned in data register. 850 * | | |1 = The conversion result will be left aligned in data register. 851 * |[1] |AVG |Average Mode Selection 852 * | | |0 = Conversion results will be stored in data register without averaging. 853 * | | |1 = Conversion results in data register will be averaged. 854 * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). 855 * |[7:4] |ACU |Number of Accumulated Conversion Results Selection 856 * | | |0000 = 1 conversion result will be accumulated. 857 * | | |0001 = 2 conversion result will be accumulated. 858 * | | |0010 = 4 conversion result will be accumulated. 859 * | | |0011 = 8 conversion result will be accumulated. 860 * | | |0100 = 16 conversion result will be accumulated. 861 * | | |0101 = 32 conversion result will be accumulated. 862 * | | |0110 = 64 conversion result will be accumulated. 863 * | | |0111 = 128 conversion result will be accumulated. 864 * | | |1000 = 256 conversion result will be accumulated. 865 * | | |Others = Reserved. 866 * @var EADC_T::M8CTL1 867 * Offset: 0x160 EADC Sample Module8 Control Register 1 868 * --------------------------------------------------------------------------------------------------- 869 * |Bits |Field |Descriptions 870 * | :----: | :----: | :---- | 871 * |[0] |ALIGN |Alignment Selection 872 * | | |0 = The conversion result will be right aligned in data register. 873 * | | |1 = The conversion result will be left aligned in data register. 874 * |[1] |AVG |Average Mode Selection 875 * | | |0 = Conversion results will be stored in data register without averaging. 876 * | | |1 = Conversion results in data register will be averaged. 877 * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). 878 * |[7:4] |ACU |Number of Accumulated Conversion Results Selection 879 * | | |0000 = 1 conversion result will be accumulated. 880 * | | |0001 = 2 conversion result will be accumulated. 881 * | | |0010 = 4 conversion result will be accumulated. 882 * | | |0011 = 8 conversion result will be accumulated. 883 * | | |0100 = 16 conversion result will be accumulated. 884 * | | |0101 = 32 conversion result will be accumulated. 885 * | | |0110 = 64 conversion result will be accumulated. 886 * | | |0111 = 128 conversion result will be accumulated. 887 * | | |1000 = 256 conversion result will be accumulated. 888 * | | |Others = Reserved. 889 * @var EADC_T::M9CTL1 890 * Offset: 0x164 EADC Sample Module9 Control Register 1 891 * --------------------------------------------------------------------------------------------------- 892 * |Bits |Field |Descriptions 893 * | :----: | :----: | :---- | 894 * |[0] |ALIGN |Alignment Selection 895 * | | |0 = The conversion result will be right aligned in data register. 896 * | | |1 = The conversion result will be left aligned in data register. 897 * |[1] |AVG |Average Mode Selection 898 * | | |0 = Conversion results will be stored in data register without averaging. 899 * | | |1 = Conversion results in data register will be averaged. 900 * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). 901 * |[7:4] |ACU |Number of Accumulated Conversion Results Selection 902 * | | |0000 = 1 conversion result will be accumulated. 903 * | | |0001 = 2 conversion result will be accumulated. 904 * | | |0010 = 4 conversion result will be accumulated. 905 * | | |0011 = 8 conversion result will be accumulated. 906 * | | |0100 = 16 conversion result will be accumulated. 907 * | | |0101 = 32 conversion result will be accumulated. 908 * | | |0110 = 64 conversion result will be accumulated. 909 * | | |0111 = 128 conversion result will be accumulated. 910 * | | |1000 = 256 conversion result will be accumulated. 911 * | | |Others = Reserved. 912 * @var EADC_T::M10CTL1 913 * Offset: 0x168 EADC Sample Module10 Control Register 1 914 * --------------------------------------------------------------------------------------------------- 915 * |Bits |Field |Descriptions 916 * | :----: | :----: | :---- | 917 * |[0] |ALIGN |Alignment Selection 918 * | | |0 = The conversion result will be right aligned in data register. 919 * | | |1 = The conversion result will be left aligned in data register. 920 * |[1] |AVG |Average Mode Selection 921 * | | |0 = Conversion results will be stored in data register without averaging. 922 * | | |1 = Conversion results in data register will be averaged. 923 * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). 924 * |[7:4] |ACU |Number of Accumulated Conversion Results Selection 925 * | | |0000 = 1 conversion result will be accumulated. 926 * | | |0001 = 2 conversion result will be accumulated. 927 * | | |0010 = 4 conversion result will be accumulated. 928 * | | |0011 = 8 conversion result will be accumulated. 929 * | | |0100 = 16 conversion result will be accumulated. 930 * | | |0101 = 32 conversion result will be accumulated. 931 * | | |0110 = 64 conversion result will be accumulated. 932 * | | |0111 = 128 conversion result will be accumulated. 933 * | | |1000 = 256 conversion result will be accumulated. 934 * | | |Others = Reserved. 935 * @var EADC_T::M11CTL1 936 * Offset: 0x16C EADC Sample Module11 Control Register 1 937 * --------------------------------------------------------------------------------------------------- 938 * |Bits |Field |Descriptions 939 * | :----: | :----: | :---- | 940 * |[0] |ALIGN |Alignment Selection 941 * | | |0 = The conversion result will be right aligned in data register. 942 * | | |1 = The conversion result will be left aligned in data register. 943 * |[1] |AVG |Average Mode Selection 944 * | | |0 = Conversion results will be stored in data register without averaging. 945 * | | |1 = Conversion results in data register will be averaged. 946 * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). 947 * |[7:4] |ACU |Number of Accumulated Conversion Results Selection 948 * | | |0000 = 1 conversion result will be accumulated. 949 * | | |0001 = 2 conversion result will be accumulated. 950 * | | |0010 = 4 conversion result will be accumulated. 951 * | | |0011 = 8 conversion result will be accumulated. 952 * | | |0100 = 16 conversion result will be accumulated. 953 * | | |0101 = 32 conversion result will be accumulated. 954 * | | |0110 = 64 conversion result will be accumulated. 955 * | | |0111 = 128 conversion result will be accumulated. 956 * | | |1000 = 256 conversion result will be accumulated. 957 * | | |Others = Reserved. 958 * @var EADC_T::M12CTL1 959 * Offset: 0x170 EADC Sample Module12 Control Register 1 960 * --------------------------------------------------------------------------------------------------- 961 * |Bits |Field |Descriptions 962 * | :----: | :----: | :---- | 963 * |[0] |ALIGN |Alignment Selection 964 * | | |0 = The conversion result will be right aligned in data register. 965 * | | |1 = The conversion result will be left aligned in data register. 966 * |[1] |AVG |Average Mode Selection 967 * | | |0 = Conversion results will be stored in data register without averaging. 968 * | | |1 = Conversion results in data register will be averaged. 969 * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). 970 * |[7:4] |ACU |Number of Accumulated Conversion Results Selection 971 * | | |0000 = 1 conversion result will be accumulated. 972 * | | |0001 = 2 conversion result will be accumulated. 973 * | | |0010 = 4 conversion result will be accumulated. 974 * | | |0011 = 8 conversion result will be accumulated. 975 * | | |0100 = 16 conversion result will be accumulated. 976 * | | |0101 = 32 conversion result will be accumulated. 977 * | | |0110 = 64 conversion result will be accumulated. 978 * | | |0111 = 128 conversion result will be accumulated. 979 * | | |1000 = 256 conversion result will be accumulated. 980 * | | |Others = Reserved. 981 * @var EADC_T::M13CTL1 982 * Offset: 0x174 EADC Sample Module13 Control Register 1 983 * --------------------------------------------------------------------------------------------------- 984 * |Bits |Field |Descriptions 985 * | :----: | :----: | :---- | 986 * |[0] |ALIGN |Alignment Selection 987 * | | |0 = The conversion result will be right aligned in data register. 988 * | | |1 = The conversion result will be left aligned in data register. 989 * |[1] |AVG |Average Mode Selection 990 * | | |0 = Conversion results will be stored in data register without averaging. 991 * | | |1 = Conversion results in data register will be averaged. 992 * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). 993 * |[7:4] |ACU |Number of Accumulated Conversion Results Selection 994 * | | |0000 = 1 conversion result will be accumulated. 995 * | | |0001 = 2 conversion result will be accumulated. 996 * | | |0010 = 4 conversion result will be accumulated. 997 * | | |0011 = 8 conversion result will be accumulated. 998 * | | |0100 = 16 conversion result will be accumulated. 999 * | | |0101 = 32 conversion result will be accumulated. 1000 * | | |0110 = 64 conversion result will be accumulated. 1001 * | | |0111 = 128 conversion result will be accumulated. 1002 * | | |1000 = 256 conversion result will be accumulated. 1003 * | | |Others = Reserved. 1004 * @var EADC_T::M14CTL1 1005 * Offset: 0x178 EADC Sample Module14 Control Register 1 1006 * --------------------------------------------------------------------------------------------------- 1007 * |Bits |Field |Descriptions 1008 * | :----: | :----: | :---- | 1009 * |[0] |ALIGN |Alignment Selection 1010 * | | |0 = The conversion result will be right aligned in data register. 1011 * | | |1 = The conversion result will be left aligned in data register. 1012 * |[1] |AVG |Average Mode Selection 1013 * | | |0 = Conversion results will be stored in data register without averaging. 1014 * | | |1 = Conversion results in data register will be averaged. 1015 * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). 1016 * |[7:4] |ACU |Number of Accumulated Conversion Results Selection 1017 * | | |0000 = 1 conversion result will be accumulated. 1018 * | | |0001 = 2 conversion result will be accumulated. 1019 * | | |0010 = 4 conversion result will be accumulated. 1020 * | | |0011 = 8 conversion result will be accumulated. 1021 * | | |0100 = 16 conversion result will be accumulated. 1022 * | | |0101 = 32 conversion result will be accumulated. 1023 * | | |0110 = 64 conversion result will be accumulated. 1024 * | | |0111 = 128 conversion result will be accumulated. 1025 * | | |1000 = 256 conversion result will be accumulated. 1026 * | | |Others = Reserved. 1027 * @var EADC_T::M15CTL1 1028 * Offset: 0x17C EADC Sample Module15 Control Register 1 1029 * --------------------------------------------------------------------------------------------------- 1030 * |Bits |Field |Descriptions 1031 * | :----: | :----: | :---- | 1032 * |[0] |ALIGN |Alignment Selection 1033 * | | |0 = The conversion result will be right aligned in data register. 1034 * | | |1 = The conversion result will be left aligned in data register. 1035 * |[1] |AVG |Average Mode Selection 1036 * | | |0 = Conversion results will be stored in data register without averaging. 1037 * | | |1 = Conversion results in data register will be averaged. 1038 * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~23). 1039 * |[7:4] |ACU |Number of Accumulated Conversion Results Selection 1040 * | | |0000 = 1 conversion result will be accumulated. 1041 * | | |0001 = 2 conversion result will be accumulated. 1042 * | | |0010 = 4 conversion result will be accumulated. 1043 * | | |0011 = 8 conversion result will be accumulated. 1044 * | | |0100 = 16 conversion result will be accumulated. 1045 * | | |0101 = 32 conversion result will be accumulated. 1046 * | | |0110 = 64 conversion result will be accumulated. 1047 * | | |0111 = 128 conversion result will be accumulated. 1048 * | | |1000 = 256 conversion result will be accumulated. 1049 * | | |Others = Reserved. 1050 */ 1051 __I uint32_t DAT[19]; /*!< [0x0000] EADC Data Register 0~18 for Sample Module 0~18 */ 1052 __I uint32_t CURDAT; /*!< [0x004c] EADC PDMA Current Transfer Data Register */ 1053 __IO uint32_t CTL; /*!< [0x0050] EADC Control Register */ 1054 __O uint32_t SWTRG; /*!< [0x0054] EADC Sample Module Software Start Register */ 1055 __IO uint32_t PENDSTS; /*!< [0x0058] EADC Start of Conversion Pending Flag Register */ 1056 __IO uint32_t OVSTS; /*!< [0x005c] EADC Sample Module Start of Conversion Overrun Flag Register */ 1057 __IO uint32_t CTL1; /*!< [0x0060] EADC Control1 Register */ 1058 /// @cond HIDDEN_SYMBOLS 1059 __I uint32_t RESERVE0[7]; 1060 /// @endcond //HIDDEN_SYMBOLS 1061 __IO uint32_t SCTL[19]; /*!< [0x0080] EADC Sample Module 0~18 Control Register */ 1062 /// @cond HIDDEN_SYMBOLS 1063 __I uint32_t RESERVE1[1]; 1064 /// @endcond //HIDDEN_SYMBOLS 1065 __IO uint32_t INTSRC[4]; /*!< [0x00d0] EADC interrupt 0~3 Source Enable Control Register. */ 1066 __IO uint32_t CMP[4]; /*!< [0x00e0] EADC Result Compare Register 0~3 */ 1067 __I uint32_t STATUS0; /*!< [0x00f0] EADC Status Register 0 */ 1068 __I uint32_t STATUS1; /*!< [0x00f4] EADC Status Register 1 */ 1069 __IO uint32_t STATUS2; /*!< [0x00f8] EADC Status Register 2 */ 1070 __I uint32_t STATUS3; /*!< [0x00fc] EADC Status Register 3 */ 1071 __I uint32_t DDAT[4]; /*!< [0x0100] EADC Double Data Register 0~3 for Sample Module 0~3 */ 1072 /// @cond HIDDEN_SYMBOLS 1073 __I uint32_t RESERVE2[1]; 1074 /// @endcond //HIDDEN_SYMBOLS 1075 __IO uint32_t CALCTL; /*!< [0x0114] EADC Calibration Control Register */ 1076 __IO uint32_t CALSR; /*!< [0x0118] EADC Calibration Status Register */ 1077 /// @cond HIDDEN_SYMBOLS 1078 __I uint32_t RESERVE3[5]; 1079 /// @endcond //HIDDEN_SYMBOLS 1080 __IO uint32_t PDMACTL; /*!< [0x0130] EADC PDMA Control Register */ 1081 /// @cond HIDDEN_SYMBOLS 1082 __I uint32_t RESERVE4[3]; 1083 /// @endcond //HIDDEN_SYMBOLS 1084 __IO uint32_t MCTL1[15]; /*!< [0x0140 - 0x017c] EADC Sample Module 0~15 Control Register */ 1085 } EADC_T; 1086 1087 /** 1088 @addtogroup EADC_CONST EADC Bit Field Definition 1089 Constant Definitions for EADC Controller 1090 @{ */ 1091 1092 #define EADC_DAT_RESULT_Pos (0) /*!< EADC_T::DAT: RESULT Position */ 1093 #define EADC_DAT_RESULT_Msk (0xfffful << EADC_DAT_RESULT_Pos) /*!< EADC_T::DAT: RESULT Mask */ 1094 1095 #define EADC_DAT_OV_Pos (16) /*!< EADC_T::DAT: OV Position */ 1096 #define EADC_DAT_OV_Msk (0x1ul << EADC_DAT_OV_Pos) /*!< EADC_T::DAT: OV Mask */ 1097 1098 #define EADC_DAT_VALID_Pos (17) /*!< EADC_T::DAT: VALID Position */ 1099 #define EADC_DAT_VALID_Msk (0x1ul << EADC_DAT_VALID_Pos) /*!< EADC_T::DAT: VALID Mask */ 1100 1101 #define EADC_DAT0_RESULT_Pos (0) /*!< EADC_T::DAT0: RESULT Position */ 1102 #define EADC_DAT0_RESULT_Msk (0xfffful << EADC_DAT0_RESULT_Pos) /*!< EADC_T::DAT0: RESULT Mask */ 1103 1104 #define EADC_DAT0_OV_Pos (16) /*!< EADC_T::DAT0: OV Position */ 1105 #define EADC_DAT0_OV_Msk (0x1ul << EADC_DAT0_OV_Pos) /*!< EADC_T::DAT0: OV Mask */ 1106 1107 #define EADC_DAT0_VALID_Pos (17) /*!< EADC_T::DAT0: VALID Position */ 1108 #define EADC_DAT0_VALID_Msk (0x1ul << EADC_DAT0_VALID_Pos) /*!< EADC_T::DAT0: VALID Mask */ 1109 1110 #define EADC_DAT1_RESULT_Pos (0) /*!< EADC_T::DAT1: RESULT Position */ 1111 #define EADC_DAT1_RESULT_Msk (0xfffful << EADC_DAT1_RESULT_Pos) /*!< EADC_T::DAT1: RESULT Mask */ 1112 1113 #define EADC_DAT1_OV_Pos (16) /*!< EADC_T::DAT1: OV Position */ 1114 #define EADC_DAT1_OV_Msk (0x1ul << EADC_DAT1_OV_Pos) /*!< EADC_T::DAT1: OV Mask */ 1115 1116 #define EADC_DAT1_VALID_Pos (17) /*!< EADC_T::DAT1: VALID Position */ 1117 #define EADC_DAT1_VALID_Msk (0x1ul << EADC_DAT1_VALID_Pos) /*!< EADC_T::DAT1: VALID Mask */ 1118 1119 #define EADC_DAT2_RESULT_Pos (0) /*!< EADC_T::DAT2: RESULT Position */ 1120 #define EADC_DAT2_RESULT_Msk (0xfffful << EADC_DAT2_RESULT_Pos) /*!< EADC_T::DAT2: RESULT Mask */ 1121 1122 #define EADC_DAT2_OV_Pos (16) /*!< EADC_T::DAT2: OV Position */ 1123 #define EADC_DAT2_OV_Msk (0x1ul << EADC_DAT2_OV_Pos) /*!< EADC_T::DAT2: OV Mask */ 1124 1125 #define EADC_DAT2_VALID_Pos (17) /*!< EADC_T::DAT2: VALID Position */ 1126 #define EADC_DAT2_VALID_Msk (0x1ul << EADC_DAT2_VALID_Pos) /*!< EADC_T::DAT2: VALID Mask */ 1127 1128 #define EADC_DAT3_RESULT_Pos (0) /*!< EADC_T::DAT3: RESULT Position */ 1129 #define EADC_DAT3_RESULT_Msk (0xfffful << EADC_DAT3_RESULT_Pos) /*!< EADC_T::DAT3: RESULT Mask */ 1130 1131 #define EADC_DAT3_OV_Pos (16) /*!< EADC_T::DAT3: OV Position */ 1132 #define EADC_DAT3_OV_Msk (0x1ul << EADC_DAT3_OV_Pos) /*!< EADC_T::DAT3: OV Mask */ 1133 1134 #define EADC_DAT3_VALID_Pos (17) /*!< EADC_T::DAT3: VALID Position */ 1135 #define EADC_DAT3_VALID_Msk (0x1ul << EADC_DAT3_VALID_Pos) /*!< EADC_T::DAT3: VALID Mask */ 1136 1137 #define EADC_DAT4_RESULT_Pos (0) /*!< EADC_T::DAT4: RESULT Position */ 1138 #define EADC_DAT4_RESULT_Msk (0xfffful << EADC_DAT4_RESULT_Pos) /*!< EADC_T::DAT4: RESULT Mask */ 1139 1140 #define EADC_DAT4_OV_Pos (16) /*!< EADC_T::DAT4: OV Position */ 1141 #define EADC_DAT4_OV_Msk (0x1ul << EADC_DAT4_OV_Pos) /*!< EADC_T::DAT4: OV Mask */ 1142 1143 #define EADC_DAT4_VALID_Pos (17) /*!< EADC_T::DAT4: VALID Position */ 1144 #define EADC_DAT4_VALID_Msk (0x1ul << EADC_DAT4_VALID_Pos) /*!< EADC_T::DAT4: VALID Mask */ 1145 1146 #define EADC_DAT5_RESULT_Pos (0) /*!< EADC_T::DAT5: RESULT Position */ 1147 #define EADC_DAT5_RESULT_Msk (0xfffful << EADC_DAT5_RESULT_Pos) /*!< EADC_T::DAT5: RESULT Mask */ 1148 1149 #define EADC_DAT5_OV_Pos (16) /*!< EADC_T::DAT5: OV Position */ 1150 #define EADC_DAT5_OV_Msk (0x1ul << EADC_DAT5_OV_Pos) /*!< EADC_T::DAT5: OV Mask */ 1151 1152 #define EADC_DAT5_VALID_Pos (17) /*!< EADC_T::DAT5: VALID Position */ 1153 #define EADC_DAT5_VALID_Msk (0x1ul << EADC_DAT5_VALID_Pos) /*!< EADC_T::DAT5: VALID Mask */ 1154 1155 #define EADC_DAT6_RESULT_Pos (0) /*!< EADC_T::DAT6: RESULT Position */ 1156 #define EADC_DAT6_RESULT_Msk (0xfffful << EADC_DAT6_RESULT_Pos) /*!< EADC_T::DAT6: RESULT Mask */ 1157 1158 #define EADC_DAT6_OV_Pos (16) /*!< EADC_T::DAT6: OV Position */ 1159 #define EADC_DAT6_OV_Msk (0x1ul << EADC_DAT6_OV_Pos) /*!< EADC_T::DAT6: OV Mask */ 1160 1161 #define EADC_DAT6_VALID_Pos (17) /*!< EADC_T::DAT6: VALID Position */ 1162 #define EADC_DAT6_VALID_Msk (0x1ul << EADC_DAT6_VALID_Pos) /*!< EADC_T::DAT6: VALID Mask */ 1163 1164 #define EADC_DAT7_RESULT_Pos (0) /*!< EADC_T::DAT7: RESULT Position */ 1165 #define EADC_DAT7_RESULT_Msk (0xfffful << EADC_DAT7_RESULT_Pos) /*!< EADC_T::DAT7: RESULT Mask */ 1166 1167 #define EADC_DAT7_OV_Pos (16) /*!< EADC_T::DAT7: OV Position */ 1168 #define EADC_DAT7_OV_Msk (0x1ul << EADC_DAT7_OV_Pos) /*!< EADC_T::DAT7: OV Mask */ 1169 1170 #define EADC_DAT7_VALID_Pos (17) /*!< EADC_T::DAT7: VALID Position */ 1171 #define EADC_DAT7_VALID_Msk (0x1ul << EADC_DAT7_VALID_Pos) /*!< EADC_T::DAT7: VALID Mask */ 1172 1173 #define EADC_DAT8_RESULT_Pos (0) /*!< EADC_T::DAT8: RESULT Position */ 1174 #define EADC_DAT8_RESULT_Msk (0xfffful << EADC_DAT8_RESULT_Pos) /*!< EADC_T::DAT8: RESULT Mask */ 1175 1176 #define EADC_DAT8_OV_Pos (16) /*!< EADC_T::DAT8: OV Position */ 1177 #define EADC_DAT8_OV_Msk (0x1ul << EADC_DAT8_OV_Pos) /*!< EADC_T::DAT8: OV Mask */ 1178 1179 #define EADC_DAT8_VALID_Pos (17) /*!< EADC_T::DAT8: VALID Position */ 1180 #define EADC_DAT8_VALID_Msk (0x1ul << EADC_DAT8_VALID_Pos) /*!< EADC_T::DAT8: VALID Mask */ 1181 1182 #define EADC_DAT9_RESULT_Pos (0) /*!< EADC_T::DAT9: RESULT Position */ 1183 #define EADC_DAT9_RESULT_Msk (0xfffful << EADC_DAT9_RESULT_Pos) /*!< EADC_T::DAT9: RESULT Mask */ 1184 1185 #define EADC_DAT9_OV_Pos (16) /*!< EADC_T::DAT9: OV Position */ 1186 #define EADC_DAT9_OV_Msk (0x1ul << EADC_DAT9_OV_Pos) /*!< EADC_T::DAT9: OV Mask */ 1187 1188 #define EADC_DAT9_VALID_Pos (17) /*!< EADC_T::DAT9: VALID Position */ 1189 #define EADC_DAT9_VALID_Msk (0x1ul << EADC_DAT9_VALID_Pos) /*!< EADC_T::DAT9: VALID Mask */ 1190 1191 #define EADC_DAT10_RESULT_Pos (0) /*!< EADC_T::DAT10: RESULT Position */ 1192 #define EADC_DAT10_RESULT_Msk (0xfffful << EADC_DAT10_RESULT_Pos) /*!< EADC_T::DAT10: RESULT Mask */ 1193 1194 #define EADC_DAT10_OV_Pos (16) /*!< EADC_T::DAT10: OV Position */ 1195 #define EADC_DAT10_OV_Msk (0x1ul << EADC_DAT10_OV_Pos) /*!< EADC_T::DAT10: OV Mask */ 1196 1197 #define EADC_DAT10_VALID_Pos (17) /*!< EADC_T::DAT10: VALID Position */ 1198 #define EADC_DAT10_VALID_Msk (0x1ul << EADC_DAT10_VALID_Pos) /*!< EADC_T::DAT10: VALID Mask */ 1199 1200 #define EADC_DAT11_RESULT_Pos (0) /*!< EADC_T::DAT11: RESULT Position */ 1201 #define EADC_DAT11_RESULT_Msk (0xfffful << EADC_DAT11_RESULT_Pos) /*!< EADC_T::DAT11: RESULT Mask */ 1202 1203 #define EADC_DAT11_OV_Pos (16) /*!< EADC_T::DAT11: OV Position */ 1204 #define EADC_DAT11_OV_Msk (0x1ul << EADC_DAT11_OV_Pos) /*!< EADC_T::DAT11: OV Mask */ 1205 1206 #define EADC_DAT11_VALID_Pos (17) /*!< EADC_T::DAT11: VALID Position */ 1207 #define EADC_DAT11_VALID_Msk (0x1ul << EADC_DAT11_VALID_Pos) /*!< EADC_T::DAT11: VALID Mask */ 1208 1209 #define EADC_DAT12_RESULT_Pos (0) /*!< EADC_T::DAT12: RESULT Position */ 1210 #define EADC_DAT12_RESULT_Msk (0xfffful << EADC_DAT12_RESULT_Pos) /*!< EADC_T::DAT12: RESULT Mask */ 1211 1212 #define EADC_DAT12_OV_Pos (16) /*!< EADC_T::DAT12: OV Position */ 1213 #define EADC_DAT12_OV_Msk (0x1ul << EADC_DAT12_OV_Pos) /*!< EADC_T::DAT12: OV Mask */ 1214 1215 #define EADC_DAT12_VALID_Pos (17) /*!< EADC_T::DAT12: VALID Position */ 1216 #define EADC_DAT12_VALID_Msk (0x1ul << EADC_DAT12_VALID_Pos) /*!< EADC_T::DAT12: VALID Mask */ 1217 1218 #define EADC_DAT13_RESULT_Pos (0) /*!< EADC_T::DAT13: RESULT Position */ 1219 #define EADC_DAT13_RESULT_Msk (0xfffful << EADC_DAT13_RESULT_Pos) /*!< EADC_T::DAT13: RESULT Mask */ 1220 1221 #define EADC_DAT13_OV_Pos (16) /*!< EADC_T::DAT13: OV Position */ 1222 #define EADC_DAT13_OV_Msk (0x1ul << EADC_DAT13_OV_Pos) /*!< EADC_T::DAT13: OV Mask */ 1223 1224 #define EADC_DAT13_VALID_Pos (17) /*!< EADC_T::DAT13: VALID Position */ 1225 #define EADC_DAT13_VALID_Msk (0x1ul << EADC_DAT13_VALID_Pos) /*!< EADC_T::DAT13: VALID Mask */ 1226 1227 #define EADC_DAT14_RESULT_Pos (0) /*!< EADC_T::DAT14: RESULT Position */ 1228 #define EADC_DAT14_RESULT_Msk (0xfffful << EADC_DAT14_RESULT_Pos) /*!< EADC_T::DAT14: RESULT Mask */ 1229 1230 #define EADC_DAT14_OV_Pos (16) /*!< EADC_T::DAT14: OV Position */ 1231 #define EADC_DAT14_OV_Msk (0x1ul << EADC_DAT14_OV_Pos) /*!< EADC_T::DAT14: OV Mask */ 1232 1233 #define EADC_DAT14_VALID_Pos (17) /*!< EADC_T::DAT14: VALID Position */ 1234 #define EADC_DAT14_VALID_Msk (0x1ul << EADC_DAT14_VALID_Pos) /*!< EADC_T::DAT14: VALID Mask */ 1235 1236 #define EADC_DAT15_RESULT_Pos (0) /*!< EADC_T::DAT15: RESULT Position */ 1237 #define EADC_DAT15_RESULT_Msk (0xfffful << EADC_DAT15_RESULT_Pos) /*!< EADC_T::DAT15: RESULT Mask */ 1238 1239 #define EADC_DAT15_OV_Pos (16) /*!< EADC_T::DAT15: OV Position */ 1240 #define EADC_DAT15_OV_Msk (0x1ul << EADC_DAT15_OV_Pos) /*!< EADC_T::DAT15: OV Mask */ 1241 1242 #define EADC_DAT15_VALID_Pos (17) /*!< EADC_T::DAT15: VALID Position */ 1243 #define EADC_DAT15_VALID_Msk (0x1ul << EADC_DAT15_VALID_Pos) /*!< EADC_T::DAT15: VALID Mask */ 1244 1245 #define EADC_DAT16_RESULT_Pos (0) /*!< EADC_T::DAT16: RESULT Position */ 1246 #define EADC_DAT16_RESULT_Msk (0xfffful << EADC_DAT16_RESULT_Pos) /*!< EADC_T::DAT16: RESULT Mask */ 1247 1248 #define EADC_DAT16_OV_Pos (16) /*!< EADC_T::DAT16: OV Position */ 1249 #define EADC_DAT16_OV_Msk (0x1ul << EADC_DAT16_OV_Pos) /*!< EADC_T::DAT16: OV Mask */ 1250 1251 #define EADC_DAT16_VALID_Pos (17) /*!< EADC_T::DAT16: VALID Position */ 1252 #define EADC_DAT16_VALID_Msk (0x1ul << EADC_DAT16_VALID_Pos) /*!< EADC_T::DAT16: VALID Mask */ 1253 1254 #define EADC_DAT17_RESULT_Pos (0) /*!< EADC_T::DAT17: RESULT Position */ 1255 #define EADC_DAT17_RESULT_Msk (0xfffful << EADC_DAT17_RESULT_Pos) /*!< EADC_T::DAT17: RESULT Mask */ 1256 1257 #define EADC_DAT17_OV_Pos (16) /*!< EADC_T::DAT17: OV Position */ 1258 #define EADC_DAT17_OV_Msk (0x1ul << EADC_DAT17_OV_Pos) /*!< EADC_T::DAT17: OV Mask */ 1259 1260 #define EADC_DAT17_VALID_Pos (17) /*!< EADC_T::DAT17: VALID Position */ 1261 #define EADC_DAT17_VALID_Msk (0x1ul << EADC_DAT17_VALID_Pos) /*!< EADC_T::DAT17: VALID Mask */ 1262 1263 #define EADC_DAT18_RESULT_Pos (0) /*!< EADC_T::DAT18: RESULT Position */ 1264 #define EADC_DAT18_RESULT_Msk (0xfffful << EADC_DAT18_RESULT_Pos) /*!< EADC_T::DAT18: RESULT Mask */ 1265 1266 #define EADC_DAT18_OV_Pos (16) /*!< EADC_T::DAT18: OV Position */ 1267 #define EADC_DAT18_OV_Msk (0x1ul << EADC_DAT18_OV_Pos) /*!< EADC_T::DAT18: OV Mask */ 1268 1269 #define EADC_DAT18_VALID_Pos (17) /*!< EADC_T::DAT18: VALID Position */ 1270 #define EADC_DAT18_VALID_Msk (0x1ul << EADC_DAT18_VALID_Pos) /*!< EADC_T::DAT18: VALID Mask */ 1271 1272 #define EADC_CURDAT_CURDAT_Pos (0) /*!< EADC_T::CURDAT: CURDAT Position */ 1273 #define EADC_CURDAT_CURDAT_Msk (0x7fffful << EADC_CURDAT_CURDAT_Pos) /*!< EADC_T::CURDAT: CURDAT Mask */ 1274 1275 #define EADC_CTL_ADCEN_Pos (0) /*!< EADC_T::CTL: ADCEN Position */ 1276 #define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) /*!< EADC_T::CTL: ADCEN Mask */ 1277 1278 #define EADC_CTL_ADCRST_Pos (1) /*!< EADC_T::CTL: ADCRST Position */ 1279 #define EADC_CTL_ADCRST_Msk (0x1ul << EADC_CTL_ADCRST_Pos) /*!< EADC_T::CTL: ADCRST Mask */ 1280 1281 #define EADC_CTL_ADCIEN0_Pos (2) /*!< EADC_T::CTL: ADCIEN0 Position */ 1282 #define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) /*!< EADC_T::CTL: ADCIEN0 Mask */ 1283 1284 #define EADC_CTL_ADCIEN1_Pos (3) /*!< EADC_T::CTL: ADCIEN1 Position */ 1285 #define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) /*!< EADC_T::CTL: ADCIEN1 Mask */ 1286 1287 #define EADC_CTL_ADCIEN2_Pos (4) /*!< EADC_T::CTL: ADCIEN2 Position */ 1288 #define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) /*!< EADC_T::CTL: ADCIEN2 Mask */ 1289 1290 #define EADC_CTL_ADCIEN3_Pos (5) /*!< EADC_T::CTL: ADCIEN3 Position */ 1291 #define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) /*!< EADC_T::CTL: ADCIEN3 Mask */ 1292 1293 #define EADC_CTL_DIFFEN_Pos (8) /*!< EADC_T::CTL: DIFFEN Position */ 1294 #define EADC_CTL_DIFFEN_Msk (0x1ul << EADC_CTL_DIFFEN_Pos) /*!< EADC_T::CTL: DIFFEN Mask */ 1295 1296 #define EADC_CTL_DMOF_Pos (9) /*!< EADC_T::CTL: DMOF Position */ 1297 #define EADC_CTL_DMOF_Msk (0x1ul << EADC_CTL_DMOF_Pos) /*!< EADC_T::CTL: DMOF Mask */ 1298 1299 #define EADC_CTL_INTDELAY0_Pos (16) /*!< EADC_T::CTL: INTDELAY0 Position */ 1300 #define EADC_CTL_INTDELAY0_Msk (0xful << EADC_CTL_INTDELAY0_Pos) /*!< EADC_T::CTL: INTDELAY0 Mask */ 1301 1302 #define EADC_CTL_INTDELAY1_Pos (20) /*!< EADC_T::CTL: INTDELAY1 Position */ 1303 #define EADC_CTL_INTDELAY1_Msk (0xful << EADC_CTL_INTDELAY1_Pos) /*!< EADC_T::CTL: INTDELAY1 Mask */ 1304 1305 #define EADC_CTL_INTDELAY2_Pos (24) /*!< EADC_T::CTL: INTDELAY2 Position */ 1306 #define EADC_CTL_INTDELAY2_Msk (0xful << EADC_CTL_INTDELAY2_Pos) /*!< EADC_T::CTL: INTDELAY2 Mask */ 1307 1308 #define EADC_CTL_INTDELAY3_Pos (28) /*!< EADC_T::CTL: INTDELAY3 Position */ 1309 #define EADC_CTL_INTDELAY3_Msk (0xful << EADC_CTL_INTDELAY3_Pos) /*!< EADC_T::CTL: INTDELAY3 Mask */ 1310 1311 #define EADC_SWTRG_SWTRG_Pos (0) /*!< EADC_T::SWTRG: SWTRG Position */ 1312 #define EADC_SWTRG_SWTRG_Msk (0x7fffful << EADC_SWTRG_SWTRG_Pos) /*!< EADC_T::SWTRG: SWTRG Mask */ 1313 1314 #define EADC_PENDSTS_STPF_Pos (0) /*!< EADC_T::PENDSTS: STPF Position */ 1315 #define EADC_PENDSTS_STPF_Msk (0x7fffful << EADC_PENDSTS_STPF_Pos) /*!< EADC_T::PENDSTS: STPF Mask */ 1316 1317 #define EADC_OVSTS_SPOVF_Pos (0) /*!< EADC_T::OVSTS: SPOVF Position */ 1318 #define EADC_OVSTS_SPOVF_Msk (0x7fffful << EADC_OVSTS_SPOVF_Pos) /*!< EADC_T::OVSTS: SPOVF Mask */ 1319 1320 #define EADC_CTL1_RESSEL_Pos (4) /*!< EADC_T::CTL1: RESSEL Position */ 1321 #define EADC_CTL1_RESSEL_Msk (0x3ul << EADC_CTL1_RESSEL_Pos) /*!< EADC_T::CTL1: RESSEL Mask */ 1322 1323 #define EADC_CTL1_CMP0TRG_Pos (20) /*!< EADC_T::CTL1: CMP0TRG Position */ 1324 #define EADC_CTL1_CMP0TRG_Msk (0x1ul << EADC_CTL1_CMP0TRG_Pos) /*!< EADC_T::CTL1: CMP0TRG Mask */ 1325 1326 #define EADC_CTL1_CMP1TRG_Pos (21) /*!< EADC_T::CTL1: CMP1TRG Position */ 1327 #define EADC_CTL1_CMP1TRG_Msk (0x1ul << EADC_CTL1_CMP1TRG_Pos) /*!< EADC_T::CTL1: CMP1TRG Mask */ 1328 1329 #define EADC_CTL1_CMP2TRG_Pos (22) /*!< EADC_T::CTL1: CMP2TRG Position */ 1330 #define EADC_CTL1_CMP2TRG_Msk (0x1ul << EADC_CTL1_CMP2TRG_Pos) /*!< EADC_T::CTL1: CMP2TRG Mask */ 1331 1332 #define EADC_CTL1_CMP3TRG_Pos (23) /*!< EADC_T::CTL1: CMP3TRG Position */ 1333 #define EADC_CTL1_CMP3TRG_Msk (0x1ul << EADC_CTL1_CMP3TRG_Pos) /*!< EADC_T::CTL1: CMP3TRG Mask */ 1334 1335 #define EADC_SCTL_CHSEL_Pos (0) /*!< EADC_T::SCTL: CHSEL Position */ 1336 #define EADC_SCTL_CHSEL_Msk (0x1ful << EADC_SCTL_CHSEL_Pos) /*!< EADC_T::SCTL: CHSEL Mask */ 1337 1338 #define EADC_SCTL_INTPOS_Pos (5) /*!< EADC_T::SCTL: INTPOS Position */ 1339 #define EADC_SCTL_INTPOS_Msk (0x1ul << EADC_SCTL_INTPOS_Pos) /*!< EADC_T::SCTL: INTPOS Mask */ 1340 1341 #define EADC_SCTL_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL: TRGDLYDIV Position */ 1342 #define EADC_SCTL_TRGDLYDIV_Msk (0x3ul << EADC_SCTL_TRGDLYDIV_Pos) /*!< EADC_T::SCTL: TRGDLYDIV Mask */ 1343 1344 #define EADC_SCTL_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL: TRGDLYCNT Position */ 1345 #define EADC_SCTL_TRGDLYCNT_Msk (0xfful << EADC_SCTL_TRGDLYCNT_Pos) /*!< EADC_T::SCTL: TRGDLYCNT Mask */ 1346 1347 #define EADC_SCTL_TRGSEL_Pos (16) /*!< EADC_T::SCTL: TRGSEL Position */ 1348 #define EADC_SCTL_TRGSEL_Msk (0x1ful << EADC_SCTL_TRGSEL_Pos) /*!< EADC_T::SCTL: TRGSEL Mask */ 1349 1350 #define EADC_SCTL_EXTREN_Pos (21) /*!< EADC_T::SCTL: EXTREN Position */ 1351 #define EADC_SCTL_EXTREN_Msk (0x1ul << EADC_SCTL_EXTREN_Pos) /*!< EADC_T::SCTL: EXTREN Mask */ 1352 1353 #define EADC_SCTL_EXTFEN_Pos (22) /*!< EADC_T::SCTL: EXTFEN Position */ 1354 #define EADC_SCTL_EXTFEN_Msk (0x1ul << EADC_SCTL_EXTFEN_Pos) /*!< EADC_T::SCTL: EXTFEN Mask */ 1355 1356 #define EADC_SCTL_DBMEN_Pos (23) /*!< EADC_T::SCTL: DBMEN Position */ 1357 #define EADC_SCTL_DBMEN_Msk (0x1ul << EADC_SCTL_DBMEN_Pos) /*!< EADC_T::SCTL: DBMEN Mask */ 1358 1359 #define EADC_SCTL_EXTSMPT_Pos (24) /*!< EADC_T::SCTL: EXTSMPT Position */ 1360 #define EADC_SCTL_EXTSMPT_Msk (0xfful << EADC_SCTL_EXTSMPT_Pos) /*!< EADC_T::SCTL: EXTSMPT Mask */ 1361 1362 #define EADC_SCTL0_CHSEL_Pos (0) /*!< EADC_T::SCTL0: CHSEL Position */ 1363 #define EADC_SCTL0_CHSEL_Msk (0x1ful << EADC_SCTL0_CHSEL_Pos) /*!< EADC_T::SCTL0: CHSEL Mask */ 1364 1365 #define EADC_SCTL0_INTPOS_Pos (5) /*!< EADC_T::SCTL0: INTPOS Position */ 1366 #define EADC_SCTL0_INTPOS_Msk (0x1ul << EADC_SCTL0_INTPOS_Pos) /*!< EADC_T::SCTL0: INTPOS Mask */ 1367 1368 #define EADC_SCTL0_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL0: TRGDLYDIV Position */ 1369 #define EADC_SCTL0_TRGDLYDIV_Msk (0x3ul << EADC_SCTL0_TRGDLYDIV_Pos) /*!< EADC_T::SCTL0: TRGDLYDIV Mask */ 1370 1371 #define EADC_SCTL0_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL0: TRGDLYCNT Position */ 1372 #define EADC_SCTL0_TRGDLYCNT_Msk (0xfful << EADC_SCTL0_TRGDLYCNT_Pos) /*!< EADC_T::SCTL0: TRGDLYCNT Mask */ 1373 1374 #define EADC_SCTL0_TRGSEL_Pos (16) /*!< EADC_T::SCTL0: TRGSEL Position */ 1375 #define EADC_SCTL0_TRGSEL_Msk (0x1ful << EADC_SCTL0_TRGSEL_Pos) /*!< EADC_T::SCTL0: TRGSEL Mask */ 1376 1377 #define EADC_SCTL0_EXTREN_Pos (21) /*!< EADC_T::SCTL0: EXTREN Position */ 1378 #define EADC_SCTL0_EXTREN_Msk (0x1ul << EADC_SCTL0_EXTREN_Pos) /*!< EADC_T::SCTL0: EXTREN Mask */ 1379 1380 #define EADC_SCTL0_EXTFEN_Pos (22) /*!< EADC_T::SCTL0: EXTFEN Position */ 1381 #define EADC_SCTL0_EXTFEN_Msk (0x1ul << EADC_SCTL0_EXTFEN_Pos) /*!< EADC_T::SCTL0: EXTFEN Mask */ 1382 1383 #define EADC_SCTL0_DBMEN_Pos (23) /*!< EADC_T::SCTL0: DBMEN Position */ 1384 #define EADC_SCTL0_DBMEN_Msk (0x1ul << EADC_SCTL0_DBMEN_Pos) /*!< EADC_T::SCTL0: DBMEN Mask */ 1385 1386 #define EADC_SCTL0_EXTSMPT_Pos (24) /*!< EADC_T::SCTL0: EXTSMPT Position */ 1387 #define EADC_SCTL0_EXTSMPT_Msk (0xfful << EADC_SCTL0_EXTSMPT_Pos) /*!< EADC_T::SCTL0: EXTSMPT Mask */ 1388 1389 #define EADC_SCTL1_CHSEL_Pos (0) /*!< EADC_T::SCTL1: CHSEL Position */ 1390 #define EADC_SCTL1_CHSEL_Msk (0x1ful << EADC_SCTL1_CHSEL_Pos) /*!< EADC_T::SCTL1: CHSEL Mask */ 1391 1392 #define EADC_SCTL1_INTPOS_Pos (5) /*!< EADC_T::SCTL1: INTPOS Position */ 1393 #define EADC_SCTL1_INTPOS_Msk (0x1ul << EADC_SCTL1_INTPOS_Pos) /*!< EADC_T::SCTL1: INTPOS Mask */ 1394 1395 #define EADC_SCTL1_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL1: TRGDLYDIV Position */ 1396 #define EADC_SCTL1_TRGDLYDIV_Msk (0x3ul << EADC_SCTL1_TRGDLYDIV_Pos) /*!< EADC_T::SCTL1: TRGDLYDIV Mask */ 1397 1398 #define EADC_SCTL1_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL1: TRGDLYCNT Position */ 1399 #define EADC_SCTL1_TRGDLYCNT_Msk (0xfful << EADC_SCTL1_TRGDLYCNT_Pos) /*!< EADC_T::SCTL1: TRGDLYCNT Mask */ 1400 1401 #define EADC_SCTL1_TRGSEL_Pos (16) /*!< EADC_T::SCTL1: TRGSEL Position */ 1402 #define EADC_SCTL1_TRGSEL_Msk (0x1ful << EADC_SCTL1_TRGSEL_Pos) /*!< EADC_T::SCTL1: TRGSEL Mask */ 1403 1404 #define EADC_SCTL1_EXTREN_Pos (21) /*!< EADC_T::SCTL1: EXTREN Position */ 1405 #define EADC_SCTL1_EXTREN_Msk (0x1ul << EADC_SCTL1_EXTREN_Pos) /*!< EADC_T::SCTL1: EXTREN Mask */ 1406 1407 #define EADC_SCTL1_EXTFEN_Pos (22) /*!< EADC_T::SCTL1: EXTFEN Position */ 1408 #define EADC_SCTL1_EXTFEN_Msk (0x1ul << EADC_SCTL1_EXTFEN_Pos) /*!< EADC_T::SCTL1: EXTFEN Mask */ 1409 1410 #define EADC_SCTL1_DBMEN_Pos (23) /*!< EADC_T::SCTL1: DBMEN Position */ 1411 #define EADC_SCTL1_DBMEN_Msk (0x1ul << EADC_SCTL1_DBMEN_Pos) /*!< EADC_T::SCTL1: DBMEN Mask */ 1412 1413 #define EADC_SCTL1_EXTSMPT_Pos (24) /*!< EADC_T::SCTL1: EXTSMPT Position */ 1414 #define EADC_SCTL1_EXTSMPT_Msk (0xfful << EADC_SCTL1_EXTSMPT_Pos) /*!< EADC_T::SCTL1: EXTSMPT Mask */ 1415 1416 #define EADC_SCTL2_CHSEL_Pos (0) /*!< EADC_T::SCTL2: CHSEL Position */ 1417 #define EADC_SCTL2_CHSEL_Msk (0x1ful << EADC_SCTL2_CHSEL_Pos) /*!< EADC_T::SCTL2: CHSEL Mask */ 1418 1419 #define EADC_SCTL2_INTPOS_Pos (5) /*!< EADC_T::SCTL2: INTPOS Position */ 1420 #define EADC_SCTL2_INTPOS_Msk (0x1ul << EADC_SCTL2_INTPOS_Pos) /*!< EADC_T::SCTL2: INTPOS Mask */ 1421 1422 #define EADC_SCTL2_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL2: TRGDLYDIV Position */ 1423 #define EADC_SCTL2_TRGDLYDIV_Msk (0x3ul << EADC_SCTL2_TRGDLYDIV_Pos) /*!< EADC_T::SCTL2: TRGDLYDIV Mask */ 1424 1425 #define EADC_SCTL2_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL2: TRGDLYCNT Position */ 1426 #define EADC_SCTL2_TRGDLYCNT_Msk (0xfful << EADC_SCTL2_TRGDLYCNT_Pos) /*!< EADC_T::SCTL2: TRGDLYCNT Mask */ 1427 1428 #define EADC_SCTL2_TRGSEL_Pos (16) /*!< EADC_T::SCTL2: TRGSEL Position */ 1429 #define EADC_SCTL2_TRGSEL_Msk (0x1ful << EADC_SCTL2_TRGSEL_Pos) /*!< EADC_T::SCTL2: TRGSEL Mask */ 1430 1431 #define EADC_SCTL2_EXTREN_Pos (21) /*!< EADC_T::SCTL2: EXTREN Position */ 1432 #define EADC_SCTL2_EXTREN_Msk (0x1ul << EADC_SCTL2_EXTREN_Pos) /*!< EADC_T::SCTL2: EXTREN Mask */ 1433 1434 #define EADC_SCTL2_EXTFEN_Pos (22) /*!< EADC_T::SCTL2: EXTFEN Position */ 1435 #define EADC_SCTL2_EXTFEN_Msk (0x1ul << EADC_SCTL2_EXTFEN_Pos) /*!< EADC_T::SCTL2: EXTFEN Mask */ 1436 1437 #define EADC_SCTL2_DBMEN_Pos (23) /*!< EADC_T::SCTL2: DBMEN Position */ 1438 #define EADC_SCTL2_DBMEN_Msk (0x1ul << EADC_SCTL2_DBMEN_Pos) /*!< EADC_T::SCTL2: DBMEN Mask */ 1439 1440 #define EADC_SCTL2_EXTSMPT_Pos (24) /*!< EADC_T::SCTL2: EXTSMPT Position */ 1441 #define EADC_SCTL2_EXTSMPT_Msk (0xfful << EADC_SCTL2_EXTSMPT_Pos) /*!< EADC_T::SCTL2: EXTSMPT Mask */ 1442 1443 #define EADC_SCTL3_CHSEL_Pos (0) /*!< EADC_T::SCTL3: CHSEL Position */ 1444 #define EADC_SCTL3_CHSEL_Msk (0x1ful << EADC_SCTL3_CHSEL_Pos) /*!< EADC_T::SCTL3: CHSEL Mask */ 1445 1446 #define EADC_SCTL3_INTPOS_Pos (5) /*!< EADC_T::SCTL3: INTPOS Position */ 1447 #define EADC_SCTL3_INTPOS_Msk (0x1ul << EADC_SCTL3_INTPOS_Pos) /*!< EADC_T::SCTL3: INTPOS Mask */ 1448 1449 #define EADC_SCTL3_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL3: TRGDLYDIV Position */ 1450 #define EADC_SCTL3_TRGDLYDIV_Msk (0x3ul << EADC_SCTL3_TRGDLYDIV_Pos) /*!< EADC_T::SCTL3: TRGDLYDIV Mask */ 1451 1452 #define EADC_SCTL3_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL3: TRGDLYCNT Position */ 1453 #define EADC_SCTL3_TRGDLYCNT_Msk (0xfful << EADC_SCTL3_TRGDLYCNT_Pos) /*!< EADC_T::SCTL3: TRGDLYCNT Mask */ 1454 1455 #define EADC_SCTL3_TRGSEL_Pos (16) /*!< EADC_T::SCTL3: TRGSEL Position */ 1456 #define EADC_SCTL3_TRGSEL_Msk (0x1ful << EADC_SCTL3_TRGSEL_Pos) /*!< EADC_T::SCTL3: TRGSEL Mask */ 1457 1458 #define EADC_SCTL3_EXTREN_Pos (21) /*!< EADC_T::SCTL3: EXTREN Position */ 1459 #define EADC_SCTL3_EXTREN_Msk (0x1ul << EADC_SCTL3_EXTREN_Pos) /*!< EADC_T::SCTL3: EXTREN Mask */ 1460 1461 #define EADC_SCTL3_EXTFEN_Pos (22) /*!< EADC_T::SCTL3: EXTFEN Position */ 1462 #define EADC_SCTL3_EXTFEN_Msk (0x1ul << EADC_SCTL3_EXTFEN_Pos) /*!< EADC_T::SCTL3: EXTFEN Mask */ 1463 1464 #define EADC_SCTL3_DBMEN_Pos (23) /*!< EADC_T::SCTL3: DBMEN Position */ 1465 #define EADC_SCTL3_DBMEN_Msk (0x1ul << EADC_SCTL3_DBMEN_Pos) /*!< EADC_T::SCTL3: DBMEN Mask */ 1466 1467 #define EADC_SCTL3_EXTSMPT_Pos (24) /*!< EADC_T::SCTL3: EXTSMPT Position */ 1468 #define EADC_SCTL3_EXTSMPT_Msk (0xfful << EADC_SCTL3_EXTSMPT_Pos) /*!< EADC_T::SCTL3: EXTSMPT Mask */ 1469 1470 #define EADC_SCTL4_CHSEL_Pos (0) /*!< EADC_T::SCTL4: CHSEL Position */ 1471 #define EADC_SCTL4_CHSEL_Msk (0x1ful << EADC_SCTL4_CHSEL_Pos) /*!< EADC_T::SCTL4: CHSEL Mask */ 1472 1473 #define EADC_SCTL4_INTPOS_Pos (5) /*!< EADC_T::SCTL4: INTPOS Position */ 1474 #define EADC_SCTL4_INTPOS_Msk (0x1ul << EADC_SCTL4_INTPOS_Pos) /*!< EADC_T::SCTL4: INTPOS Mask */ 1475 1476 #define EADC_SCTL4_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL4: TRGDLYDIV Position */ 1477 #define EADC_SCTL4_TRGDLYDIV_Msk (0x3ul << EADC_SCTL4_TRGDLYDIV_Pos) /*!< EADC_T::SCTL4: TRGDLYDIV Mask */ 1478 1479 #define EADC_SCTL4_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL4: TRGDLYCNT Position */ 1480 #define EADC_SCTL4_TRGDLYCNT_Msk (0xfful << EADC_SCTL4_TRGDLYCNT_Pos) /*!< EADC_T::SCTL4: TRGDLYCNT Mask */ 1481 1482 #define EADC_SCTL4_TRGSEL_Pos (16) /*!< EADC_T::SCTL4: TRGSEL Position */ 1483 #define EADC_SCTL4_TRGSEL_Msk (0x1ful << EADC_SCTL4_TRGSEL_Pos) /*!< EADC_T::SCTL4: TRGSEL Mask */ 1484 1485 #define EADC_SCTL4_EXTREN_Pos (21) /*!< EADC_T::SCTL4: EXTREN Position */ 1486 #define EADC_SCTL4_EXTREN_Msk (0x1ul << EADC_SCTL4_EXTREN_Pos) /*!< EADC_T::SCTL4: EXTREN Mask */ 1487 1488 #define EADC_SCTL4_EXTFEN_Pos (22) /*!< EADC_T::SCTL4: EXTFEN Position */ 1489 #define EADC_SCTL4_EXTFEN_Msk (0x1ul << EADC_SCTL4_EXTFEN_Pos) /*!< EADC_T::SCTL4: EXTFEN Mask */ 1490 1491 #define EADC_SCTL4_EXTSMPT_Pos (24) /*!< EADC_T::SCTL4: EXTSMPT Position */ 1492 #define EADC_SCTL4_EXTSMPT_Msk (0xfful << EADC_SCTL4_EXTSMPT_Pos) /*!< EADC_T::SCTL4: EXTSMPT Mask */ 1493 1494 #define EADC_SCTL5_CHSEL_Pos (0) /*!< EADC_T::SCTL5: CHSEL Position */ 1495 #define EADC_SCTL5_CHSEL_Msk (0x1ful << EADC_SCTL5_CHSEL_Pos) /*!< EADC_T::SCTL5: CHSEL Mask */ 1496 1497 #define EADC_SCTL5_INTPOS_Pos (5) /*!< EADC_T::SCTL5: INTPOS Position */ 1498 #define EADC_SCTL5_INTPOS_Msk (0x1ul << EADC_SCTL5_INTPOS_Pos) /*!< EADC_T::SCTL5: INTPOS Mask */ 1499 1500 #define EADC_SCTL5_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL5: TRGDLYDIV Position */ 1501 #define EADC_SCTL5_TRGDLYDIV_Msk (0x3ul << EADC_SCTL5_TRGDLYDIV_Pos) /*!< EADC_T::SCTL5: TRGDLYDIV Mask */ 1502 1503 #define EADC_SCTL5_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL5: TRGDLYCNT Position */ 1504 #define EADC_SCTL5_TRGDLYCNT_Msk (0xfful << EADC_SCTL5_TRGDLYCNT_Pos) /*!< EADC_T::SCTL5: TRGDLYCNT Mask */ 1505 1506 #define EADC_SCTL5_TRGSEL_Pos (16) /*!< EADC_T::SCTL5: TRGSEL Position */ 1507 #define EADC_SCTL5_TRGSEL_Msk (0x1ful << EADC_SCTL5_TRGSEL_Pos) /*!< EADC_T::SCTL5: TRGSEL Mask */ 1508 1509 #define EADC_SCTL5_EXTREN_Pos (21) /*!< EADC_T::SCTL5: EXTREN Position */ 1510 #define EADC_SCTL5_EXTREN_Msk (0x1ul << EADC_SCTL5_EXTREN_Pos) /*!< EADC_T::SCTL5: EXTREN Mask */ 1511 1512 #define EADC_SCTL5_EXTFEN_Pos (22) /*!< EADC_T::SCTL5: EXTFEN Position */ 1513 #define EADC_SCTL5_EXTFEN_Msk (0x1ul << EADC_SCTL5_EXTFEN_Pos) /*!< EADC_T::SCTL5: EXTFEN Mask */ 1514 1515 #define EADC_SCTL5_EXTSMPT_Pos (24) /*!< EADC_T::SCTL5: EXTSMPT Position */ 1516 #define EADC_SCTL5_EXTSMPT_Msk (0xfful << EADC_SCTL5_EXTSMPT_Pos) /*!< EADC_T::SCTL5: EXTSMPT Mask */ 1517 1518 #define EADC_SCTL6_CHSEL_Pos (0) /*!< EADC_T::SCTL6: CHSEL Position */ 1519 #define EADC_SCTL6_CHSEL_Msk (0x1ful << EADC_SCTL6_CHSEL_Pos) /*!< EADC_T::SCTL6: CHSEL Mask */ 1520 1521 #define EADC_SCTL6_INTPOS_Pos (5) /*!< EADC_T::SCTL6: INTPOS Position */ 1522 #define EADC_SCTL6_INTPOS_Msk (0x1ul << EADC_SCTL6_INTPOS_Pos) /*!< EADC_T::SCTL6: INTPOS Mask */ 1523 1524 #define EADC_SCTL6_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL6: TRGDLYDIV Position */ 1525 #define EADC_SCTL6_TRGDLYDIV_Msk (0x3ul << EADC_SCTL6_TRGDLYDIV_Pos) /*!< EADC_T::SCTL6: TRGDLYDIV Mask */ 1526 1527 #define EADC_SCTL6_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL6: TRGDLYCNT Position */ 1528 #define EADC_SCTL6_TRGDLYCNT_Msk (0xfful << EADC_SCTL6_TRGDLYCNT_Pos) /*!< EADC_T::SCTL6: TRGDLYCNT Mask */ 1529 1530 #define EADC_SCTL6_TRGSEL_Pos (16) /*!< EADC_T::SCTL6: TRGSEL Position */ 1531 #define EADC_SCTL6_TRGSEL_Msk (0x1ful << EADC_SCTL6_TRGSEL_Pos) /*!< EADC_T::SCTL6: TRGSEL Mask */ 1532 1533 #define EADC_SCTL6_EXTREN_Pos (21) /*!< EADC_T::SCTL6: EXTREN Position */ 1534 #define EADC_SCTL6_EXTREN_Msk (0x1ul << EADC_SCTL6_EXTREN_Pos) /*!< EADC_T::SCTL6: EXTREN Mask */ 1535 1536 #define EADC_SCTL6_EXTFEN_Pos (22) /*!< EADC_T::SCTL6: EXTFEN Position */ 1537 #define EADC_SCTL6_EXTFEN_Msk (0x1ul << EADC_SCTL6_EXTFEN_Pos) /*!< EADC_T::SCTL6: EXTFEN Mask */ 1538 1539 #define EADC_SCTL6_EXTSMPT_Pos (24) /*!< EADC_T::SCTL6: EXTSMPT Position */ 1540 #define EADC_SCTL6_EXTSMPT_Msk (0xfful << EADC_SCTL6_EXTSMPT_Pos) /*!< EADC_T::SCTL6: EXTSMPT Mask */ 1541 1542 #define EADC_SCTL7_CHSEL_Pos (0) /*!< EADC_T::SCTL7: CHSEL Position */ 1543 #define EADC_SCTL7_CHSEL_Msk (0x1ful << EADC_SCTL7_CHSEL_Pos) /*!< EADC_T::SCTL7: CHSEL Mask */ 1544 1545 #define EADC_SCTL7_INTPOS_Pos (5) /*!< EADC_T::SCTL7: INTPOS Position */ 1546 #define EADC_SCTL7_INTPOS_Msk (0x1ul << EADC_SCTL7_INTPOS_Pos) /*!< EADC_T::SCTL7: INTPOS Mask */ 1547 1548 #define EADC_SCTL7_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL7: TRGDLYDIV Position */ 1549 #define EADC_SCTL7_TRGDLYDIV_Msk (0x3ul << EADC_SCTL7_TRGDLYDIV_Pos) /*!< EADC_T::SCTL7: TRGDLYDIV Mask */ 1550 1551 #define EADC_SCTL7_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL7: TRGDLYCNT Position */ 1552 #define EADC_SCTL7_TRGDLYCNT_Msk (0xfful << EADC_SCTL7_TRGDLYCNT_Pos) /*!< EADC_T::SCTL7: TRGDLYCNT Mask */ 1553 1554 #define EADC_SCTL7_TRGSEL_Pos (16) /*!< EADC_T::SCTL7: TRGSEL Position */ 1555 #define EADC_SCTL7_TRGSEL_Msk (0x1ful << EADC_SCTL7_TRGSEL_Pos) /*!< EADC_T::SCTL7: TRGSEL Mask */ 1556 1557 #define EADC_SCTL7_EXTREN_Pos (21) /*!< EADC_T::SCTL7: EXTREN Position */ 1558 #define EADC_SCTL7_EXTREN_Msk (0x1ul << EADC_SCTL7_EXTREN_Pos) /*!< EADC_T::SCTL7: EXTREN Mask */ 1559 1560 #define EADC_SCTL7_EXTFEN_Pos (22) /*!< EADC_T::SCTL7: EXTFEN Position */ 1561 #define EADC_SCTL7_EXTFEN_Msk (0x1ul << EADC_SCTL7_EXTFEN_Pos) /*!< EADC_T::SCTL7: EXTFEN Mask */ 1562 1563 #define EADC_SCTL7_EXTSMPT_Pos (24) /*!< EADC_T::SCTL7: EXTSMPT Position */ 1564 #define EADC_SCTL7_EXTSMPT_Msk (0xfful << EADC_SCTL7_EXTSMPT_Pos) /*!< EADC_T::SCTL7: EXTSMPT Mask */ 1565 1566 #define EADC_SCTL8_CHSEL_Pos (0) /*!< EADC_T::SCTL8: CHSEL Position */ 1567 #define EADC_SCTL8_CHSEL_Msk (0x1ful << EADC_SCTL8_CHSEL_Pos) /*!< EADC_T::SCTL8: CHSEL Mask */ 1568 1569 #define EADC_SCTL8_INTPOS_Pos (5) /*!< EADC_T::SCTL8: INTPOS Position */ 1570 #define EADC_SCTL8_INTPOS_Msk (0x1ul << EADC_SCTL8_INTPOS_Pos) /*!< EADC_T::SCTL8: INTPOS Mask */ 1571 1572 #define EADC_SCTL8_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL8: TRGDLYDIV Position */ 1573 #define EADC_SCTL8_TRGDLYDIV_Msk (0x3ul << EADC_SCTL8_TRGDLYDIV_Pos) /*!< EADC_T::SCTL8: TRGDLYDIV Mask */ 1574 1575 #define EADC_SCTL8_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL8: TRGDLYCNT Position */ 1576 #define EADC_SCTL8_TRGDLYCNT_Msk (0xfful << EADC_SCTL8_TRGDLYCNT_Pos) /*!< EADC_T::SCTL8: TRGDLYCNT Mask */ 1577 1578 #define EADC_SCTL8_TRGSEL_Pos (16) /*!< EADC_T::SCTL8: TRGSEL Position */ 1579 #define EADC_SCTL8_TRGSEL_Msk (0x1ful << EADC_SCTL8_TRGSEL_Pos) /*!< EADC_T::SCTL8: TRGSEL Mask */ 1580 1581 #define EADC_SCTL8_EXTREN_Pos (21) /*!< EADC_T::SCTL8: EXTREN Position */ 1582 #define EADC_SCTL8_EXTREN_Msk (0x1ul << EADC_SCTL8_EXTREN_Pos) /*!< EADC_T::SCTL8: EXTREN Mask */ 1583 1584 #define EADC_SCTL8_EXTFEN_Pos (22) /*!< EADC_T::SCTL8: EXTFEN Position */ 1585 #define EADC_SCTL8_EXTFEN_Msk (0x1ul << EADC_SCTL8_EXTFEN_Pos) /*!< EADC_T::SCTL8: EXTFEN Mask */ 1586 1587 #define EADC_SCTL8_EXTSMPT_Pos (24) /*!< EADC_T::SCTL8: EXTSMPT Position */ 1588 #define EADC_SCTL8_EXTSMPT_Msk (0xfful << EADC_SCTL8_EXTSMPT_Pos) /*!< EADC_T::SCTL8: EXTSMPT Mask */ 1589 1590 #define EADC_SCTL9_CHSEL_Pos (0) /*!< EADC_T::SCTL9: CHSEL Position */ 1591 #define EADC_SCTL9_CHSEL_Msk (0x1ful << EADC_SCTL9_CHSEL_Pos) /*!< EADC_T::SCTL9: CHSEL Mask */ 1592 1593 #define EADC_SCTL9_INTPOS_Pos (5) /*!< EADC_T::SCTL9: INTPOS Position */ 1594 #define EADC_SCTL9_INTPOS_Msk (0x1ul << EADC_SCTL9_INTPOS_Pos) /*!< EADC_T::SCTL9: INTPOS Mask */ 1595 1596 #define EADC_SCTL9_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL9: TRGDLYDIV Position */ 1597 #define EADC_SCTL9_TRGDLYDIV_Msk (0x3ul << EADC_SCTL9_TRGDLYDIV_Pos) /*!< EADC_T::SCTL9: TRGDLYDIV Mask */ 1598 1599 #define EADC_SCTL9_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL9: TRGDLYCNT Position */ 1600 #define EADC_SCTL9_TRGDLYCNT_Msk (0xfful << EADC_SCTL9_TRGDLYCNT_Pos) /*!< EADC_T::SCTL9: TRGDLYCNT Mask */ 1601 1602 #define EADC_SCTL9_TRGSEL_Pos (16) /*!< EADC_T::SCTL9: TRGSEL Position */ 1603 #define EADC_SCTL9_TRGSEL_Msk (0x1ful << EADC_SCTL9_TRGSEL_Pos) /*!< EADC_T::SCTL9: TRGSEL Mask */ 1604 1605 #define EADC_SCTL9_EXTREN_Pos (21) /*!< EADC_T::SCTL9: EXTREN Position */ 1606 #define EADC_SCTL9_EXTREN_Msk (0x1ul << EADC_SCTL9_EXTREN_Pos) /*!< EADC_T::SCTL9: EXTREN Mask */ 1607 1608 #define EADC_SCTL9_EXTFEN_Pos (22) /*!< EADC_T::SCTL9: EXTFEN Position */ 1609 #define EADC_SCTL9_EXTFEN_Msk (0x1ul << EADC_SCTL9_EXTFEN_Pos) /*!< EADC_T::SCTL9: EXTFEN Mask */ 1610 1611 #define EADC_SCTL9_EXTSMPT_Pos (24) /*!< EADC_T::SCTL9: EXTSMPT Position */ 1612 #define EADC_SCTL9_EXTSMPT_Msk (0xfful << EADC_SCTL9_EXTSMPT_Pos) /*!< EADC_T::SCTL9: EXTSMPT Mask */ 1613 1614 #define EADC_SCTL10_CHSEL_Pos (0) /*!< EADC_T::SCTL10: CHSEL Position */ 1615 #define EADC_SCTL10_CHSEL_Msk (0x1ful << EADC_SCTL10_CHSEL_Pos) /*!< EADC_T::SCTL10: CHSEL Mask */ 1616 1617 #define EADC_SCTL10_INTPOS_Pos (5) /*!< EADC_T::SCTL10: INTPOS Position */ 1618 #define EADC_SCTL10_INTPOS_Msk (0x1ul << EADC_SCTL10_INTPOS_Pos) /*!< EADC_T::SCTL10: INTPOS Mask */ 1619 1620 #define EADC_SCTL10_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL10: TRGDLYDIV Position */ 1621 #define EADC_SCTL10_TRGDLYDIV_Msk (0x3ul << EADC_SCTL10_TRGDLYDIV_Pos) /*!< EADC_T::SCTL10: TRGDLYDIV Mask */ 1622 1623 #define EADC_SCTL10_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL10: TRGDLYCNT Position */ 1624 #define EADC_SCTL10_TRGDLYCNT_Msk (0xfful << EADC_SCTL10_TRGDLYCNT_Pos) /*!< EADC_T::SCTL10: TRGDLYCNT Mask */ 1625 1626 #define EADC_SCTL10_TRGSEL_Pos (16) /*!< EADC_T::SCTL10: TRGSEL Position */ 1627 #define EADC_SCTL10_TRGSEL_Msk (0x1ful << EADC_SCTL10_TRGSEL_Pos) /*!< EADC_T::SCTL10: TRGSEL Mask */ 1628 1629 #define EADC_SCTL10_EXTREN_Pos (21) /*!< EADC_T::SCTL10: EXTREN Position */ 1630 #define EADC_SCTL10_EXTREN_Msk (0x1ul << EADC_SCTL10_EXTREN_Pos) /*!< EADC_T::SCTL10: EXTREN Mask */ 1631 1632 #define EADC_SCTL10_EXTFEN_Pos (22) /*!< EADC_T::SCTL10: EXTFEN Position */ 1633 #define EADC_SCTL10_EXTFEN_Msk (0x1ul << EADC_SCTL10_EXTFEN_Pos) /*!< EADC_T::SCTL10: EXTFEN Mask */ 1634 1635 #define EADC_SCTL10_EXTSMPT_Pos (24) /*!< EADC_T::SCTL10: EXTSMPT Position */ 1636 #define EADC_SCTL10_EXTSMPT_Msk (0xfful << EADC_SCTL10_EXTSMPT_Pos) /*!< EADC_T::SCTL10: EXTSMPT Mask */ 1637 1638 #define EADC_SCTL11_CHSEL_Pos (0) /*!< EADC_T::SCTL11: CHSEL Position */ 1639 #define EADC_SCTL11_CHSEL_Msk (0x1ful << EADC_SCTL11_CHSEL_Pos) /*!< EADC_T::SCTL11: CHSEL Mask */ 1640 1641 #define EADC_SCTL11_INTPOS_Pos (5) /*!< EADC_T::SCTL11: INTPOS Position */ 1642 #define EADC_SCTL11_INTPOS_Msk (0x1ul << EADC_SCTL11_INTPOS_Pos) /*!< EADC_T::SCTL11: INTPOS Mask */ 1643 1644 #define EADC_SCTL11_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL11: TRGDLYDIV Position */ 1645 #define EADC_SCTL11_TRGDLYDIV_Msk (0x3ul << EADC_SCTL11_TRGDLYDIV_Pos) /*!< EADC_T::SCTL11: TRGDLYDIV Mask */ 1646 1647 #define EADC_SCTL11_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL11: TRGDLYCNT Position */ 1648 #define EADC_SCTL11_TRGDLYCNT_Msk (0xfful << EADC_SCTL11_TRGDLYCNT_Pos) /*!< EADC_T::SCTL11: TRGDLYCNT Mask */ 1649 1650 #define EADC_SCTL11_TRGSEL_Pos (16) /*!< EADC_T::SCTL11: TRGSEL Position */ 1651 #define EADC_SCTL11_TRGSEL_Msk (0x1ful << EADC_SCTL11_TRGSEL_Pos) /*!< EADC_T::SCTL11: TRGSEL Mask */ 1652 1653 #define EADC_SCTL11_EXTREN_Pos (21) /*!< EADC_T::SCTL11: EXTREN Position */ 1654 #define EADC_SCTL11_EXTREN_Msk (0x1ul << EADC_SCTL11_EXTREN_Pos) /*!< EADC_T::SCTL11: EXTREN Mask */ 1655 1656 #define EADC_SCTL11_EXTFEN_Pos (22) /*!< EADC_T::SCTL11: EXTFEN Position */ 1657 #define EADC_SCTL11_EXTFEN_Msk (0x1ul << EADC_SCTL11_EXTFEN_Pos) /*!< EADC_T::SCTL11: EXTFEN Mask */ 1658 1659 #define EADC_SCTL11_EXTSMPT_Pos (24) /*!< EADC_T::SCTL11: EXTSMPT Position */ 1660 #define EADC_SCTL11_EXTSMPT_Msk (0xfful << EADC_SCTL11_EXTSMPT_Pos) /*!< EADC_T::SCTL11: EXTSMPT Mask */ 1661 1662 #define EADC_SCTL12_CHSEL_Pos (0) /*!< EADC_T::SCTL12: CHSEL Position */ 1663 #define EADC_SCTL12_CHSEL_Msk (0x1ful << EADC_SCTL12_CHSEL_Pos) /*!< EADC_T::SCTL12: CHSEL Mask */ 1664 1665 #define EADC_SCTL12_INTPOS_Pos (5) /*!< EADC_T::SCTL12: INTPOS Position */ 1666 #define EADC_SCTL12_INTPOS_Msk (0x1ul << EADC_SCTL12_INTPOS_Pos) /*!< EADC_T::SCTL12: INTPOS Mask */ 1667 1668 #define EADC_SCTL12_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL12: TRGDLYDIV Position */ 1669 #define EADC_SCTL12_TRGDLYDIV_Msk (0x3ul << EADC_SCTL12_TRGDLYDIV_Pos) /*!< EADC_T::SCTL12: TRGDLYDIV Mask */ 1670 1671 #define EADC_SCTL12_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL12: TRGDLYCNT Position */ 1672 #define EADC_SCTL12_TRGDLYCNT_Msk (0xfful << EADC_SCTL12_TRGDLYCNT_Pos) /*!< EADC_T::SCTL12: TRGDLYCNT Mask */ 1673 1674 #define EADC_SCTL12_TRGSEL_Pos (16) /*!< EADC_T::SCTL12: TRGSEL Position */ 1675 #define EADC_SCTL12_TRGSEL_Msk (0x1ful << EADC_SCTL12_TRGSEL_Pos) /*!< EADC_T::SCTL12: TRGSEL Mask */ 1676 1677 #define EADC_SCTL12_EXTREN_Pos (21) /*!< EADC_T::SCTL12: EXTREN Position */ 1678 #define EADC_SCTL12_EXTREN_Msk (0x1ul << EADC_SCTL12_EXTREN_Pos) /*!< EADC_T::SCTL12: EXTREN Mask */ 1679 1680 #define EADC_SCTL12_EXTFEN_Pos (22) /*!< EADC_T::SCTL12: EXTFEN Position */ 1681 #define EADC_SCTL12_EXTFEN_Msk (0x1ul << EADC_SCTL12_EXTFEN_Pos) /*!< EADC_T::SCTL12: EXTFEN Mask */ 1682 1683 #define EADC_SCTL12_EXTSMPT_Pos (24) /*!< EADC_T::SCTL12: EXTSMPT Position */ 1684 #define EADC_SCTL12_EXTSMPT_Msk (0xfful << EADC_SCTL12_EXTSMPT_Pos) /*!< EADC_T::SCTL12: EXTSMPT Mask */ 1685 1686 #define EADC_SCTL13_CHSEL_Pos (0) /*!< EADC_T::SCTL13: CHSEL Position */ 1687 #define EADC_SCTL13_CHSEL_Msk (0x1ful << EADC_SCTL13_CHSEL_Pos) /*!< EADC_T::SCTL13: CHSEL Mask */ 1688 1689 #define EADC_SCTL13_INTPOS_Pos (5) /*!< EADC_T::SCTL13: INTPOS Position */ 1690 #define EADC_SCTL13_INTPOS_Msk (0x1ul << EADC_SCTL13_INTPOS_Pos) /*!< EADC_T::SCTL13: INTPOS Mask */ 1691 1692 #define EADC_SCTL13_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL13: TRGDLYDIV Position */ 1693 #define EADC_SCTL13_TRGDLYDIV_Msk (0x3ul << EADC_SCTL13_TRGDLYDIV_Pos) /*!< EADC_T::SCTL13: TRGDLYDIV Mask */ 1694 1695 #define EADC_SCTL13_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL13: TRGDLYCNT Position */ 1696 #define EADC_SCTL13_TRGDLYCNT_Msk (0xfful << EADC_SCTL13_TRGDLYCNT_Pos) /*!< EADC_T::SCTL13: TRGDLYCNT Mask */ 1697 1698 #define EADC_SCTL13_TRGSEL_Pos (16) /*!< EADC_T::SCTL13: TRGSEL Position */ 1699 #define EADC_SCTL13_TRGSEL_Msk (0x1ful << EADC_SCTL13_TRGSEL_Pos) /*!< EADC_T::SCTL13: TRGSEL Mask */ 1700 1701 #define EADC_SCTL13_EXTREN_Pos (21) /*!< EADC_T::SCTL13: EXTREN Position */ 1702 #define EADC_SCTL13_EXTREN_Msk (0x1ul << EADC_SCTL13_EXTREN_Pos) /*!< EADC_T::SCTL13: EXTREN Mask */ 1703 1704 #define EADC_SCTL13_EXTFEN_Pos (22) /*!< EADC_T::SCTL13: EXTFEN Position */ 1705 #define EADC_SCTL13_EXTFEN_Msk (0x1ul << EADC_SCTL13_EXTFEN_Pos) /*!< EADC_T::SCTL13: EXTFEN Mask */ 1706 1707 #define EADC_SCTL13_EXTSMPT_Pos (24) /*!< EADC_T::SCTL13: EXTSMPT Position */ 1708 #define EADC_SCTL13_EXTSMPT_Msk (0xfful << EADC_SCTL13_EXTSMPT_Pos) /*!< EADC_T::SCTL13: EXTSMPT Mask */ 1709 1710 #define EADC_SCTL14_CHSEL_Pos (0) /*!< EADC_T::SCTL14: CHSEL Position */ 1711 #define EADC_SCTL14_CHSEL_Msk (0x1ful << EADC_SCTL14_CHSEL_Pos) /*!< EADC_T::SCTL14: CHSEL Mask */ 1712 1713 #define EADC_SCTL14_INTPOS_Pos (5) /*!< EADC_T::SCTL14: INTPOS Position */ 1714 #define EADC_SCTL14_INTPOS_Msk (0x1ul << EADC_SCTL14_INTPOS_Pos) /*!< EADC_T::SCTL14: INTPOS Mask */ 1715 1716 #define EADC_SCTL14_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL14: TRGDLYDIV Position */ 1717 #define EADC_SCTL14_TRGDLYDIV_Msk (0x3ul << EADC_SCTL14_TRGDLYDIV_Pos) /*!< EADC_T::SCTL14: TRGDLYDIV Mask */ 1718 1719 #define EADC_SCTL14_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL14: TRGDLYCNT Position */ 1720 #define EADC_SCTL14_TRGDLYCNT_Msk (0xfful << EADC_SCTL14_TRGDLYCNT_Pos) /*!< EADC_T::SCTL14: TRGDLYCNT Mask */ 1721 1722 #define EADC_SCTL14_TRGSEL_Pos (16) /*!< EADC_T::SCTL14: TRGSEL Position */ 1723 #define EADC_SCTL14_TRGSEL_Msk (0x1ful << EADC_SCTL14_TRGSEL_Pos) /*!< EADC_T::SCTL14: TRGSEL Mask */ 1724 1725 #define EADC_SCTL14_EXTREN_Pos (21) /*!< EADC_T::SCTL14: EXTREN Position */ 1726 #define EADC_SCTL14_EXTREN_Msk (0x1ul << EADC_SCTL14_EXTREN_Pos) /*!< EADC_T::SCTL14: EXTREN Mask */ 1727 1728 #define EADC_SCTL14_EXTFEN_Pos (22) /*!< EADC_T::SCTL14: EXTFEN Position */ 1729 #define EADC_SCTL14_EXTFEN_Msk (0x1ul << EADC_SCTL14_EXTFEN_Pos) /*!< EADC_T::SCTL14: EXTFEN Mask */ 1730 1731 #define EADC_SCTL14_EXTSMPT_Pos (24) /*!< EADC_T::SCTL14: EXTSMPT Position */ 1732 #define EADC_SCTL14_EXTSMPT_Msk (0xfful << EADC_SCTL14_EXTSMPT_Pos) /*!< EADC_T::SCTL14: EXTSMPT Mask */ 1733 1734 #define EADC_SCTL15_CHSEL_Pos (0) /*!< EADC_T::SCTL15: CHSEL Position */ 1735 #define EADC_SCTL15_CHSEL_Msk (0x1ful << EADC_SCTL15_CHSEL_Pos) /*!< EADC_T::SCTL15: CHSEL Mask */ 1736 1737 #define EADC_SCTL15_INTPOS_Pos (5) /*!< EADC_T::SCTL15: INTPOS Position */ 1738 #define EADC_SCTL15_INTPOS_Msk (0x1ul << EADC_SCTL15_INTPOS_Pos) /*!< EADC_T::SCTL15: INTPOS Mask */ 1739 1740 #define EADC_SCTL15_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL15: TRGDLYDIV Position */ 1741 #define EADC_SCTL15_TRGDLYDIV_Msk (0x3ul << EADC_SCTL15_TRGDLYDIV_Pos) /*!< EADC_T::SCTL15: TRGDLYDIV Mask */ 1742 1743 #define EADC_SCTL15_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL15: TRGDLYCNT Position */ 1744 #define EADC_SCTL15_TRGDLYCNT_Msk (0xfful << EADC_SCTL15_TRGDLYCNT_Pos) /*!< EADC_T::SCTL15: TRGDLYCNT Mask */ 1745 1746 #define EADC_SCTL15_TRGSEL_Pos (16) /*!< EADC_T::SCTL15: TRGSEL Position */ 1747 #define EADC_SCTL15_TRGSEL_Msk (0x1ful << EADC_SCTL15_TRGSEL_Pos) /*!< EADC_T::SCTL15: TRGSEL Mask */ 1748 1749 #define EADC_SCTL15_EXTREN_Pos (21) /*!< EADC_T::SCTL15: EXTREN Position */ 1750 #define EADC_SCTL15_EXTREN_Msk (0x1ul << EADC_SCTL15_EXTREN_Pos) /*!< EADC_T::SCTL15: EXTREN Mask */ 1751 1752 #define EADC_SCTL15_EXTFEN_Pos (22) /*!< EADC_T::SCTL15: EXTFEN Position */ 1753 #define EADC_SCTL15_EXTFEN_Msk (0x1ul << EADC_SCTL15_EXTFEN_Pos) /*!< EADC_T::SCTL15: EXTFEN Mask */ 1754 1755 #define EADC_SCTL15_EXTSMPT_Pos (24) /*!< EADC_T::SCTL15: EXTSMPT Position */ 1756 #define EADC_SCTL15_EXTSMPT_Msk (0xfful << EADC_SCTL15_EXTSMPT_Pos) /*!< EADC_T::SCTL15: EXTSMPT Mask */ 1757 1758 #define EADC_SCTL16_EXTSMPT_Pos (24) /*!< EADC_T::SCTL16: EXTSMPT Position */ 1759 #define EADC_SCTL16_EXTSMPT_Msk (0xfful << EADC_SCTL16_EXTSMPT_Pos) /*!< EADC_T::SCTL16: EXTSMPT Mask */ 1760 1761 #define EADC_SCTL17_EXTSMPT_Pos (24) /*!< EADC_T::SCTL17: EXTSMPT Position */ 1762 #define EADC_SCTL17_EXTSMPT_Msk (0xfful << EADC_SCTL17_EXTSMPT_Pos) /*!< EADC_T::SCTL17: EXTSMPT Mask */ 1763 1764 #define EADC_SCTL18_EXTSMPT_Pos (24) /*!< EADC_T::SCTL18: EXTSMPT Position */ 1765 #define EADC_SCTL18_EXTSMPT_Msk (0xfful << EADC_SCTL18_EXTSMPT_Pos) /*!< EADC_T::SCTL18: EXTSMPT Mask */ 1766 1767 #define EADC_INTSRC0_SPLIE0_Pos (0) /*!< EADC_T::INTSRC0: SPLIE0 Position */ 1768 #define EADC_INTSRC0_SPLIE0_Msk (0x1ul << EADC_INTSRC0_SPLIE0_Pos) /*!< EADC_T::INTSRC0: SPLIE0 Mask */ 1769 1770 #define EADC_INTSRC0_SPLIE1_Pos (1) /*!< EADC_T::INTSRC0: SPLIE1 Position */ 1771 #define EADC_INTSRC0_SPLIE1_Msk (0x1ul << EADC_INTSRC0_SPLIE1_Pos) /*!< EADC_T::INTSRC0: SPLIE1 Mask */ 1772 1773 #define EADC_INTSRC0_SPLIE2_Pos (2) /*!< EADC_T::INTSRC0: SPLIE2 Position */ 1774 #define EADC_INTSRC0_SPLIE2_Msk (0x1ul << EADC_INTSRC0_SPLIE2_Pos) /*!< EADC_T::INTSRC0: SPLIE2 Mask */ 1775 1776 #define EADC_INTSRC0_SPLIE3_Pos (3) /*!< EADC_T::INTSRC0: SPLIE3 Position */ 1777 #define EADC_INTSRC0_SPLIE3_Msk (0x1ul << EADC_INTSRC0_SPLIE3_Pos) /*!< EADC_T::INTSRC0: SPLIE3 Mask */ 1778 1779 #define EADC_INTSRC0_SPLIE4_Pos (4) /*!< EADC_T::INTSRC0: SPLIE4 Position */ 1780 #define EADC_INTSRC0_SPLIE4_Msk (0x1ul << EADC_INTSRC0_SPLIE4_Pos) /*!< EADC_T::INTSRC0: SPLIE4 Mask */ 1781 1782 #define EADC_INTSRC0_SPLIE5_Pos (5) /*!< EADC_T::INTSRC0: SPLIE5 Position */ 1783 #define EADC_INTSRC0_SPLIE5_Msk (0x1ul << EADC_INTSRC0_SPLIE5_Pos) /*!< EADC_T::INTSRC0: SPLIE5 Mask */ 1784 1785 #define EADC_INTSRC0_SPLIE6_Pos (6) /*!< EADC_T::INTSRC0: SPLIE6 Position */ 1786 #define EADC_INTSRC0_SPLIE6_Msk (0x1ul << EADC_INTSRC0_SPLIE6_Pos) /*!< EADC_T::INTSRC0: SPLIE6 Mask */ 1787 1788 #define EADC_INTSRC0_SPLIE7_Pos (7) /*!< EADC_T::INTSRC0: SPLIE7 Position */ 1789 #define EADC_INTSRC0_SPLIE7_Msk (0x1ul << EADC_INTSRC0_SPLIE7_Pos) /*!< EADC_T::INTSRC0: SPLIE7 Mask */ 1790 1791 #define EADC_INTSRC0_SPLIE8_Pos (8) /*!< EADC_T::INTSRC0: SPLIE8 Position */ 1792 #define EADC_INTSRC0_SPLIE8_Msk (0x1ul << EADC_INTSRC0_SPLIE8_Pos) /*!< EADC_T::INTSRC0: SPLIE8 Mask */ 1793 1794 #define EADC_INTSRC0_SPLIE9_Pos (9) /*!< EADC_T::INTSRC0: SPLIE9 Position */ 1795 #define EADC_INTSRC0_SPLIE9_Msk (0x1ul << EADC_INTSRC0_SPLIE9_Pos) /*!< EADC_T::INTSRC0: SPLIE9 Mask */ 1796 1797 #define EADC_INTSRC0_SPLIE10_Pos (10) /*!< EADC_T::INTSRC0: SPLIE10 Position */ 1798 #define EADC_INTSRC0_SPLIE10_Msk (0x1ul << EADC_INTSRC0_SPLIE10_Pos) /*!< EADC_T::INTSRC0: SPLIE10 Mask */ 1799 1800 #define EADC_INTSRC0_SPLIE11_Pos (11) /*!< EADC_T::INTSRC0: SPLIE11 Position */ 1801 #define EADC_INTSRC0_SPLIE11_Msk (0x1ul << EADC_INTSRC0_SPLIE11_Pos) /*!< EADC_T::INTSRC0: SPLIE11 Mask */ 1802 1803 #define EADC_INTSRC0_SPLIE12_Pos (12) /*!< EADC_T::INTSRC0: SPLIE12 Position */ 1804 #define EADC_INTSRC0_SPLIE12_Msk (0x1ul << EADC_INTSRC0_SPLIE12_Pos) /*!< EADC_T::INTSRC0: SPLIE12 Mask */ 1805 1806 #define EADC_INTSRC0_SPLIE13_Pos (13) /*!< EADC_T::INTSRC0: SPLIE13 Position */ 1807 #define EADC_INTSRC0_SPLIE13_Msk (0x1ul << EADC_INTSRC0_SPLIE13_Pos) /*!< EADC_T::INTSRC0: SPLIE13 Mask */ 1808 1809 #define EADC_INTSRC0_SPLIE14_Pos (14) /*!< EADC_T::INTSRC0: SPLIE14 Position */ 1810 #define EADC_INTSRC0_SPLIE14_Msk (0x1ul << EADC_INTSRC0_SPLIE14_Pos) /*!< EADC_T::INTSRC0: SPLIE14 Mask */ 1811 1812 #define EADC_INTSRC0_SPLIE15_Pos (15) /*!< EADC_T::INTSRC0: SPLIE15 Position */ 1813 #define EADC_INTSRC0_SPLIE15_Msk (0x1ul << EADC_INTSRC0_SPLIE15_Pos) /*!< EADC_T::INTSRC0: SPLIE15 Mask */ 1814 1815 #define EADC_INTSRC0_SPLIE16_Pos (16) /*!< EADC_T::INTSRC0: SPLIE16 Position */ 1816 #define EADC_INTSRC0_SPLIE16_Msk (0x1ul << EADC_INTSRC0_SPLIE16_Pos) /*!< EADC_T::INTSRC0: SPLIE16 Mask */ 1817 1818 #define EADC_INTSRC0_SPLIE17_Pos (17) /*!< EADC_T::INTSRC0: SPLIE17 Position */ 1819 #define EADC_INTSRC0_SPLIE17_Msk (0x1ul << EADC_INTSRC0_SPLIE17_Pos) /*!< EADC_T::INTSRC0: SPLIE17 Mask */ 1820 1821 #define EADC_INTSRC0_SPLIE18_Pos (18) /*!< EADC_T::INTSRC0: SPLIE18 Position */ 1822 #define EADC_INTSRC0_SPLIE18_Msk (0x1ul << EADC_INTSRC0_SPLIE18_Pos) /*!< EADC_T::INTSRC0: SPLIE18 Mask */ 1823 1824 #define EADC_INTSRC1_SPLIE0_Pos (0) /*!< EADC_T::INTSRC1: SPLIE0 Position */ 1825 #define EADC_INTSRC1_SPLIE0_Msk (0x1ul << EADC_INTSRC1_SPLIE0_Pos) /*!< EADC_T::INTSRC1: SPLIE0 Mask */ 1826 1827 #define EADC_INTSRC1_SPLIE1_Pos (1) /*!< EADC_T::INTSRC1: SPLIE1 Position */ 1828 #define EADC_INTSRC1_SPLIE1_Msk (0x1ul << EADC_INTSRC1_SPLIE1_Pos) /*!< EADC_T::INTSRC1: SPLIE1 Mask */ 1829 1830 #define EADC_INTSRC1_SPLIE2_Pos (2) /*!< EADC_T::INTSRC1: SPLIE2 Position */ 1831 #define EADC_INTSRC1_SPLIE2_Msk (0x1ul << EADC_INTSRC1_SPLIE2_Pos) /*!< EADC_T::INTSRC1: SPLIE2 Mask */ 1832 1833 #define EADC_INTSRC1_SPLIE3_Pos (3) /*!< EADC_T::INTSRC1: SPLIE3 Position */ 1834 #define EADC_INTSRC1_SPLIE3_Msk (0x1ul << EADC_INTSRC1_SPLIE3_Pos) /*!< EADC_T::INTSRC1: SPLIE3 Mask */ 1835 1836 #define EADC_INTSRC1_SPLIE4_Pos (4) /*!< EADC_T::INTSRC1: SPLIE4 Position */ 1837 #define EADC_INTSRC1_SPLIE4_Msk (0x1ul << EADC_INTSRC1_SPLIE4_Pos) /*!< EADC_T::INTSRC1: SPLIE4 Mask */ 1838 1839 #define EADC_INTSRC1_SPLIE5_Pos (5) /*!< EADC_T::INTSRC1: SPLIE5 Position */ 1840 #define EADC_INTSRC1_SPLIE5_Msk (0x1ul << EADC_INTSRC1_SPLIE5_Pos) /*!< EADC_T::INTSRC1: SPLIE5 Mask */ 1841 1842 #define EADC_INTSRC1_SPLIE6_Pos (6) /*!< EADC_T::INTSRC1: SPLIE6 Position */ 1843 #define EADC_INTSRC1_SPLIE6_Msk (0x1ul << EADC_INTSRC1_SPLIE6_Pos) /*!< EADC_T::INTSRC1: SPLIE6 Mask */ 1844 1845 #define EADC_INTSRC1_SPLIE7_Pos (7) /*!< EADC_T::INTSRC1: SPLIE7 Position */ 1846 #define EADC_INTSRC1_SPLIE7_Msk (0x1ul << EADC_INTSRC1_SPLIE7_Pos) /*!< EADC_T::INTSRC1: SPLIE7 Mask */ 1847 1848 #define EADC_INTSRC1_SPLIE8_Pos (8) /*!< EADC_T::INTSRC1: SPLIE8 Position */ 1849 #define EADC_INTSRC1_SPLIE8_Msk (0x1ul << EADC_INTSRC1_SPLIE8_Pos) /*!< EADC_T::INTSRC1: SPLIE8 Mask */ 1850 1851 #define EADC_INTSRC1_SPLIE9_Pos (9) /*!< EADC_T::INTSRC1: SPLIE9 Position */ 1852 #define EADC_INTSRC1_SPLIE9_Msk (0x1ul << EADC_INTSRC1_SPLIE9_Pos) /*!< EADC_T::INTSRC1: SPLIE9 Mask */ 1853 1854 #define EADC_INTSRC1_SPLIE10_Pos (10) /*!< EADC_T::INTSRC1: SPLIE10 Position */ 1855 #define EADC_INTSRC1_SPLIE10_Msk (0x1ul << EADC_INTSRC1_SPLIE10_Pos) /*!< EADC_T::INTSRC1: SPLIE10 Mask */ 1856 1857 #define EADC_INTSRC1_SPLIE11_Pos (11) /*!< EADC_T::INTSRC1: SPLIE11 Position */ 1858 #define EADC_INTSRC1_SPLIE11_Msk (0x1ul << EADC_INTSRC1_SPLIE11_Pos) /*!< EADC_T::INTSRC1: SPLIE11 Mask */ 1859 1860 #define EADC_INTSRC1_SPLIE12_Pos (12) /*!< EADC_T::INTSRC1: SPLIE12 Position */ 1861 #define EADC_INTSRC1_SPLIE12_Msk (0x1ul << EADC_INTSRC1_SPLIE12_Pos) /*!< EADC_T::INTSRC1: SPLIE12 Mask */ 1862 1863 #define EADC_INTSRC1_SPLIE13_Pos (13) /*!< EADC_T::INTSRC1: SPLIE13 Position */ 1864 #define EADC_INTSRC1_SPLIE13_Msk (0x1ul << EADC_INTSRC1_SPLIE13_Pos) /*!< EADC_T::INTSRC1: SPLIE13 Mask */ 1865 1866 #define EADC_INTSRC1_SPLIE14_Pos (14) /*!< EADC_T::INTSRC1: SPLIE14 Position */ 1867 #define EADC_INTSRC1_SPLIE14_Msk (0x1ul << EADC_INTSRC1_SPLIE14_Pos) /*!< EADC_T::INTSRC1: SPLIE14 Mask */ 1868 1869 #define EADC_INTSRC1_SPLIE15_Pos (15) /*!< EADC_T::INTSRC1: SPLIE15 Position */ 1870 #define EADC_INTSRC1_SPLIE15_Msk (0x1ul << EADC_INTSRC1_SPLIE15_Pos) /*!< EADC_T::INTSRC1: SPLIE15 Mask */ 1871 1872 #define EADC_INTSRC1_SPLIE16_Pos (16) /*!< EADC_T::INTSRC1: SPLIE16 Position */ 1873 #define EADC_INTSRC1_SPLIE16_Msk (0x1ul << EADC_INTSRC1_SPLIE16_Pos) /*!< EADC_T::INTSRC1: SPLIE16 Mask */ 1874 1875 #define EADC_INTSRC1_SPLIE17_Pos (17) /*!< EADC_T::INTSRC1: SPLIE17 Position */ 1876 #define EADC_INTSRC1_SPLIE17_Msk (0x1ul << EADC_INTSRC1_SPLIE17_Pos) /*!< EADC_T::INTSRC1: SPLIE17 Mask */ 1877 1878 #define EADC_INTSRC1_SPLIE18_Pos (18) /*!< EADC_T::INTSRC1: SPLIE18 Position */ 1879 #define EADC_INTSRC1_SPLIE18_Msk (0x1ul << EADC_INTSRC1_SPLIE18_Pos) /*!< EADC_T::INTSRC1: SPLIE18 Mask */ 1880 1881 #define EADC_INTSRC2_SPLIE0_Pos (0) /*!< EADC_T::INTSRC2: SPLIE0 Position */ 1882 #define EADC_INTSRC2_SPLIE0_Msk (0x1ul << EADC_INTSRC2_SPLIE0_Pos) /*!< EADC_T::INTSRC2: SPLIE0 Mask */ 1883 1884 #define EADC_INTSRC2_SPLIE1_Pos (1) /*!< EADC_T::INTSRC2: SPLIE1 Position */ 1885 #define EADC_INTSRC2_SPLIE1_Msk (0x1ul << EADC_INTSRC2_SPLIE1_Pos) /*!< EADC_T::INTSRC2: SPLIE1 Mask */ 1886 1887 #define EADC_INTSRC2_SPLIE2_Pos (2) /*!< EADC_T::INTSRC2: SPLIE2 Position */ 1888 #define EADC_INTSRC2_SPLIE2_Msk (0x1ul << EADC_INTSRC2_SPLIE2_Pos) /*!< EADC_T::INTSRC2: SPLIE2 Mask */ 1889 1890 #define EADC_INTSRC2_SPLIE3_Pos (3) /*!< EADC_T::INTSRC2: SPLIE3 Position */ 1891 #define EADC_INTSRC2_SPLIE3_Msk (0x1ul << EADC_INTSRC2_SPLIE3_Pos) /*!< EADC_T::INTSRC2: SPLIE3 Mask */ 1892 1893 #define EADC_INTSRC2_SPLIE4_Pos (4) /*!< EADC_T::INTSRC2: SPLIE4 Position */ 1894 #define EADC_INTSRC2_SPLIE4_Msk (0x1ul << EADC_INTSRC2_SPLIE4_Pos) /*!< EADC_T::INTSRC2: SPLIE4 Mask */ 1895 1896 #define EADC_INTSRC2_SPLIE5_Pos (5) /*!< EADC_T::INTSRC2: SPLIE5 Position */ 1897 #define EADC_INTSRC2_SPLIE5_Msk (0x1ul << EADC_INTSRC2_SPLIE5_Pos) /*!< EADC_T::INTSRC2: SPLIE5 Mask */ 1898 1899 #define EADC_INTSRC2_SPLIE6_Pos (6) /*!< EADC_T::INTSRC2: SPLIE6 Position */ 1900 #define EADC_INTSRC2_SPLIE6_Msk (0x1ul << EADC_INTSRC2_SPLIE6_Pos) /*!< EADC_T::INTSRC2: SPLIE6 Mask */ 1901 1902 #define EADC_INTSRC2_SPLIE7_Pos (7) /*!< EADC_T::INTSRC2: SPLIE7 Position */ 1903 #define EADC_INTSRC2_SPLIE7_Msk (0x1ul << EADC_INTSRC2_SPLIE7_Pos) /*!< EADC_T::INTSRC2: SPLIE7 Mask */ 1904 1905 #define EADC_INTSRC2_SPLIE8_Pos (8) /*!< EADC_T::INTSRC2: SPLIE8 Position */ 1906 #define EADC_INTSRC2_SPLIE8_Msk (0x1ul << EADC_INTSRC2_SPLIE8_Pos) /*!< EADC_T::INTSRC2: SPLIE8 Mask */ 1907 1908 #define EADC_INTSRC2_SPLIE9_Pos (9) /*!< EADC_T::INTSRC2: SPLIE9 Position */ 1909 #define EADC_INTSRC2_SPLIE9_Msk (0x1ul << EADC_INTSRC2_SPLIE9_Pos) /*!< EADC_T::INTSRC2: SPLIE9 Mask */ 1910 1911 #define EADC_INTSRC2_SPLIE10_Pos (10) /*!< EADC_T::INTSRC2: SPLIE10 Position */ 1912 #define EADC_INTSRC2_SPLIE10_Msk (0x1ul << EADC_INTSRC2_SPLIE10_Pos) /*!< EADC_T::INTSRC2: SPLIE10 Mask */ 1913 1914 #define EADC_INTSRC2_SPLIE11_Pos (11) /*!< EADC_T::INTSRC2: SPLIE11 Position */ 1915 #define EADC_INTSRC2_SPLIE11_Msk (0x1ul << EADC_INTSRC2_SPLIE11_Pos) /*!< EADC_T::INTSRC2: SPLIE11 Mask */ 1916 1917 #define EADC_INTSRC2_SPLIE12_Pos (12) /*!< EADC_T::INTSRC2: SPLIE12 Position */ 1918 #define EADC_INTSRC2_SPLIE12_Msk (0x1ul << EADC_INTSRC2_SPLIE12_Pos) /*!< EADC_T::INTSRC2: SPLIE12 Mask */ 1919 1920 #define EADC_INTSRC2_SPLIE13_Pos (13) /*!< EADC_T::INTSRC2: SPLIE13 Position */ 1921 #define EADC_INTSRC2_SPLIE13_Msk (0x1ul << EADC_INTSRC2_SPLIE13_Pos) /*!< EADC_T::INTSRC2: SPLIE13 Mask */ 1922 1923 #define EADC_INTSRC2_SPLIE14_Pos (14) /*!< EADC_T::INTSRC2: SPLIE14 Position */ 1924 #define EADC_INTSRC2_SPLIE14_Msk (0x1ul << EADC_INTSRC2_SPLIE14_Pos) /*!< EADC_T::INTSRC2: SPLIE14 Mask */ 1925 1926 #define EADC_INTSRC2_SPLIE15_Pos (15) /*!< EADC_T::INTSRC2: SPLIE15 Position */ 1927 #define EADC_INTSRC2_SPLIE15_Msk (0x1ul << EADC_INTSRC2_SPLIE15_Pos) /*!< EADC_T::INTSRC2: SPLIE15 Mask */ 1928 1929 #define EADC_INTSRC2_SPLIE16_Pos (16) /*!< EADC_T::INTSRC2: SPLIE16 Position */ 1930 #define EADC_INTSRC2_SPLIE16_Msk (0x1ul << EADC_INTSRC2_SPLIE16_Pos) /*!< EADC_T::INTSRC2: SPLIE16 Mask */ 1931 1932 #define EADC_INTSRC2_SPLIE17_Pos (17) /*!< EADC_T::INTSRC2: SPLIE17 Position */ 1933 #define EADC_INTSRC2_SPLIE17_Msk (0x1ul << EADC_INTSRC2_SPLIE17_Pos) /*!< EADC_T::INTSRC2: SPLIE17 Mask */ 1934 1935 #define EADC_INTSRC2_SPLIE18_Pos (18) /*!< EADC_T::INTSRC2: SPLIE18 Position */ 1936 #define EADC_INTSRC2_SPLIE18_Msk (0x1ul << EADC_INTSRC2_SPLIE18_Pos) /*!< EADC_T::INTSRC2: SPLIE18 Mask */ 1937 1938 #define EADC_INTSRC3_SPLIE0_Pos (0) /*!< EADC_T::INTSRC3: SPLIE0 Position */ 1939 #define EADC_INTSRC3_SPLIE0_Msk (0x1ul << EADC_INTSRC3_SPLIE0_Pos) /*!< EADC_T::INTSRC3: SPLIE0 Mask */ 1940 1941 #define EADC_INTSRC3_SPLIE1_Pos (1) /*!< EADC_T::INTSRC3: SPLIE1 Position */ 1942 #define EADC_INTSRC3_SPLIE1_Msk (0x1ul << EADC_INTSRC3_SPLIE1_Pos) /*!< EADC_T::INTSRC3: SPLIE1 Mask */ 1943 1944 #define EADC_INTSRC3_SPLIE2_Pos (2) /*!< EADC_T::INTSRC3: SPLIE2 Position */ 1945 #define EADC_INTSRC3_SPLIE2_Msk (0x1ul << EADC_INTSRC3_SPLIE2_Pos) /*!< EADC_T::INTSRC3: SPLIE2 Mask */ 1946 1947 #define EADC_INTSRC3_SPLIE3_Pos (3) /*!< EADC_T::INTSRC3: SPLIE3 Position */ 1948 #define EADC_INTSRC3_SPLIE3_Msk (0x1ul << EADC_INTSRC3_SPLIE3_Pos) /*!< EADC_T::INTSRC3: SPLIE3 Mask */ 1949 1950 #define EADC_INTSRC3_SPLIE4_Pos (4) /*!< EADC_T::INTSRC3: SPLIE4 Position */ 1951 #define EADC_INTSRC3_SPLIE4_Msk (0x1ul << EADC_INTSRC3_SPLIE4_Pos) /*!< EADC_T::INTSRC3: SPLIE4 Mask */ 1952 1953 #define EADC_INTSRC3_SPLIE5_Pos (5) /*!< EADC_T::INTSRC3: SPLIE5 Position */ 1954 #define EADC_INTSRC3_SPLIE5_Msk (0x1ul << EADC_INTSRC3_SPLIE5_Pos) /*!< EADC_T::INTSRC3: SPLIE5 Mask */ 1955 1956 #define EADC_INTSRC3_SPLIE6_Pos (6) /*!< EADC_T::INTSRC3: SPLIE6 Position */ 1957 #define EADC_INTSRC3_SPLIE6_Msk (0x1ul << EADC_INTSRC3_SPLIE6_Pos) /*!< EADC_T::INTSRC3: SPLIE6 Mask */ 1958 1959 #define EADC_INTSRC3_SPLIE7_Pos (7) /*!< EADC_T::INTSRC3: SPLIE7 Position */ 1960 #define EADC_INTSRC3_SPLIE7_Msk (0x1ul << EADC_INTSRC3_SPLIE7_Pos) /*!< EADC_T::INTSRC3: SPLIE7 Mask */ 1961 1962 #define EADC_INTSRC3_SPLIE8_Pos (8) /*!< EADC_T::INTSRC3: SPLIE8 Position */ 1963 #define EADC_INTSRC3_SPLIE8_Msk (0x1ul << EADC_INTSRC3_SPLIE8_Pos) /*!< EADC_T::INTSRC3: SPLIE8 Mask */ 1964 1965 #define EADC_INTSRC3_SPLIE9_Pos (9) /*!< EADC_T::INTSRC3: SPLIE9 Position */ 1966 #define EADC_INTSRC3_SPLIE9_Msk (0x1ul << EADC_INTSRC3_SPLIE9_Pos) /*!< EADC_T::INTSRC3: SPLIE9 Mask */ 1967 1968 #define EADC_INTSRC3_SPLIE10_Pos (10) /*!< EADC_T::INTSRC3: SPLIE10 Position */ 1969 #define EADC_INTSRC3_SPLIE10_Msk (0x1ul << EADC_INTSRC3_SPLIE10_Pos) /*!< EADC_T::INTSRC3: SPLIE10 Mask */ 1970 1971 #define EADC_INTSRC3_SPLIE11_Pos (11) /*!< EADC_T::INTSRC3: SPLIE11 Position */ 1972 #define EADC_INTSRC3_SPLIE11_Msk (0x1ul << EADC_INTSRC3_SPLIE11_Pos) /*!< EADC_T::INTSRC3: SPLIE11 Mask */ 1973 1974 #define EADC_INTSRC3_SPLIE12_Pos (12) /*!< EADC_T::INTSRC3: SPLIE12 Position */ 1975 #define EADC_INTSRC3_SPLIE12_Msk (0x1ul << EADC_INTSRC3_SPLIE12_Pos) /*!< EADC_T::INTSRC3: SPLIE12 Mask */ 1976 1977 #define EADC_INTSRC3_SPLIE13_Pos (13) /*!< EADC_T::INTSRC3: SPLIE13 Position */ 1978 #define EADC_INTSRC3_SPLIE13_Msk (0x1ul << EADC_INTSRC3_SPLIE13_Pos) /*!< EADC_T::INTSRC3: SPLIE13 Mask */ 1979 1980 #define EADC_INTSRC3_SPLIE14_Pos (14) /*!< EADC_T::INTSRC3: SPLIE14 Position */ 1981 #define EADC_INTSRC3_SPLIE14_Msk (0x1ul << EADC_INTSRC3_SPLIE14_Pos) /*!< EADC_T::INTSRC3: SPLIE14 Mask */ 1982 1983 #define EADC_INTSRC3_SPLIE15_Pos (15) /*!< EADC_T::INTSRC3: SPLIE15 Position */ 1984 #define EADC_INTSRC3_SPLIE15_Msk (0x1ul << EADC_INTSRC3_SPLIE15_Pos) /*!< EADC_T::INTSRC3: SPLIE15 Mask */ 1985 1986 #define EADC_INTSRC3_SPLIE16_Pos (16) /*!< EADC_T::INTSRC3: SPLIE16 Position */ 1987 #define EADC_INTSRC3_SPLIE16_Msk (0x1ul << EADC_INTSRC3_SPLIE16_Pos) /*!< EADC_T::INTSRC3: SPLIE16 Mask */ 1988 1989 #define EADC_INTSRC3_SPLIE17_Pos (17) /*!< EADC_T::INTSRC3: SPLIE17 Position */ 1990 #define EADC_INTSRC3_SPLIE17_Msk (0x1ul << EADC_INTSRC3_SPLIE17_Pos) /*!< EADC_T::INTSRC3: SPLIE17 Mask */ 1991 1992 #define EADC_INTSRC3_SPLIE18_Pos (18) /*!< EADC_T::INTSRC3: SPLIE18 Position */ 1993 #define EADC_INTSRC3_SPLIE18_Msk (0x1ul << EADC_INTSRC3_SPLIE18_Pos) /*!< EADC_T::INTSRC3: SPLIE18 Mask */ 1994 1995 #define EADC_CMP_ADCMPEN_Pos (0) /*!< EADC_T::CMP: ADCMPEN Position */ 1996 #define EADC_CMP_ADCMPEN_Msk (0x1ul << EADC_CMP_ADCMPEN_Pos) /*!< EADC_T::CMP: ADCMPEN Mask */ 1997 1998 #define EADC_CMP_ADCMPIE_Pos (1) /*!< EADC_T::CMP: ADCMPIE Position */ 1999 #define EADC_CMP_ADCMPIE_Msk (0x1ul << EADC_CMP_ADCMPIE_Pos) /*!< EADC_T::CMP: ADCMPIE Mask */ 2000 2001 #define EADC_CMP_CMPCOND_Pos (2) /*!< EADC_T::CMP: CMPCOND Position */ 2002 #define EADC_CMP_CMPCOND_Msk (0x1ul << EADC_CMP_CMPCOND_Pos) /*!< EADC_T::CMP: CMPCOND Mask */ 2003 2004 #define EADC_CMP_CMPSPL_Pos (3) /*!< EADC_T::CMP: CMPSPL Position */ 2005 #define EADC_CMP_CMPSPL_Msk (0x1ful << EADC_CMP_CMPSPL_Pos) /*!< EADC_T::CMP: CMPSPL Mask */ 2006 2007 #define EADC_CMP_CMPMCNT_Pos (8) /*!< EADC_T::CMP: CMPMCNT Position */ 2008 #define EADC_CMP_CMPMCNT_Msk (0xful << EADC_CMP_CMPMCNT_Pos) /*!< EADC_T::CMP: CMPMCNT Mask */ 2009 2010 #define EADC_CMP_CMPWEN_Pos (15) /*!< EADC_T::CMP: CMPWEN Position */ 2011 #define EADC_CMP_CMPWEN_Msk (0x1ul << EADC_CMP_CMPWEN_Pos) /*!< EADC_T::CMP: CMPWEN Mask */ 2012 2013 #define EADC_CMP_CMPDAT_Pos (16) /*!< EADC_T::CMP: CMPDAT Position */ 2014 #define EADC_CMP_CMPDAT_Msk (0xffful << EADC_CMP_CMPDAT_Pos) /*!< EADC_T::CMP: CMPDAT Mask */ 2015 2016 #define EADC_CMP0_ADCMPEN_Pos (0) /*!< EADC_T::CMP0: ADCMPEN Position */ 2017 #define EADC_CMP0_ADCMPEN_Msk (0x1ul << EADC_CMP0_ADCMPEN_Pos) /*!< EADC_T::CMP0: ADCMPEN Mask */ 2018 2019 #define EADC_CMP0_ADCMPIE_Pos (1) /*!< EADC_T::CMP0: ADCMPIE Position */ 2020 #define EADC_CMP0_ADCMPIE_Msk (0x1ul << EADC_CMP0_ADCMPIE_Pos) /*!< EADC_T::CMP0: ADCMPIE Mask */ 2021 2022 #define EADC_CMP0_CMPCOND_Pos (2) /*!< EADC_T::CMP0: CMPCOND Position */ 2023 #define EADC_CMP0_CMPCOND_Msk (0x1ul << EADC_CMP0_CMPCOND_Pos) /*!< EADC_T::CMP0: CMPCOND Mask */ 2024 2025 #define EADC_CMP0_CMPSPL_Pos (3) /*!< EADC_T::CMP0: CMPSPL Position */ 2026 #define EADC_CMP0_CMPSPL_Msk (0x1ful << EADC_CMP0_CMPSPL_Pos) /*!< EADC_T::CMP0: CMPSPL Mask */ 2027 2028 #define EADC_CMP0_CMPMCNT_Pos (8) /*!< EADC_T::CMP0: CMPMCNT Position */ 2029 #define EADC_CMP0_CMPMCNT_Msk (0xful << EADC_CMP0_CMPMCNT_Pos) /*!< EADC_T::CMP0: CMPMCNT Mask */ 2030 2031 #define EADC_CMP0_CMPWEN_Pos (15) /*!< EADC_T::CMP0: CMPWEN Position */ 2032 #define EADC_CMP0_CMPWEN_Msk (0x1ul << EADC_CMP0_CMPWEN_Pos) /*!< EADC_T::CMP0: CMPWEN Mask */ 2033 2034 #define EADC_CMP0_CMPDAT_Pos (16) /*!< EADC_T::CMP0: CMPDAT Position */ 2035 #define EADC_CMP0_CMPDAT_Msk (0xffful << EADC_CMP0_CMPDAT_Pos) /*!< EADC_T::CMP0: CMPDAT Mask */ 2036 2037 #define EADC_CMP1_ADCMPEN_Pos (0) /*!< EADC_T::CMP1: ADCMPEN Position */ 2038 #define EADC_CMP1_ADCMPEN_Msk (0x1ul << EADC_CMP1_ADCMPEN_Pos) /*!< EADC_T::CMP1: ADCMPEN Mask */ 2039 2040 #define EADC_CMP1_ADCMPIE_Pos (1) /*!< EADC_T::CMP1: ADCMPIE Position */ 2041 #define EADC_CMP1_ADCMPIE_Msk (0x1ul << EADC_CMP1_ADCMPIE_Pos) /*!< EADC_T::CMP1: ADCMPIE Mask */ 2042 2043 #define EADC_CMP1_CMPCOND_Pos (2) /*!< EADC_T::CMP1: CMPCOND Position */ 2044 #define EADC_CMP1_CMPCOND_Msk (0x1ul << EADC_CMP1_CMPCOND_Pos) /*!< EADC_T::CMP1: CMPCOND Mask */ 2045 2046 #define EADC_CMP1_CMPSPL_Pos (3) /*!< EADC_T::CMP1: CMPSPL Position */ 2047 #define EADC_CMP1_CMPSPL_Msk (0x1ful << EADC_CMP1_CMPSPL_Pos) /*!< EADC_T::CMP1: CMPSPL Mask */ 2048 2049 #define EADC_CMP1_CMPMCNT_Pos (8) /*!< EADC_T::CMP1: CMPMCNT Position */ 2050 #define EADC_CMP1_CMPMCNT_Msk (0xful << EADC_CMP1_CMPMCNT_Pos) /*!< EADC_T::CMP1: CMPMCNT Mask */ 2051 2052 #define EADC_CMP1_CMPWEN_Pos (15) /*!< EADC_T::CMP1: CMPWEN Position */ 2053 #define EADC_CMP1_CMPWEN_Msk (0x1ul << EADC_CMP1_CMPWEN_Pos) /*!< EADC_T::CMP1: CMPWEN Mask */ 2054 2055 #define EADC_CMP1_CMPDAT_Pos (16) /*!< EADC_T::CMP1: CMPDAT Position */ 2056 #define EADC_CMP1_CMPDAT_Msk (0xffful << EADC_CMP1_CMPDAT_Pos) /*!< EADC_T::CMP1: CMPDAT Mask */ 2057 2058 #define EADC_CMP2_ADCMPEN_Pos (0) /*!< EADC_T::CMP2: ADCMPEN Position */ 2059 #define EADC_CMP2_ADCMPEN_Msk (0x1ul << EADC_CMP2_ADCMPEN_Pos) /*!< EADC_T::CMP2: ADCMPEN Mask */ 2060 2061 #define EADC_CMP2_ADCMPIE_Pos (1) /*!< EADC_T::CMP2: ADCMPIE Position */ 2062 #define EADC_CMP2_ADCMPIE_Msk (0x1ul << EADC_CMP2_ADCMPIE_Pos) /*!< EADC_T::CMP2: ADCMPIE Mask */ 2063 2064 #define EADC_CMP2_CMPCOND_Pos (2) /*!< EADC_T::CMP2: CMPCOND Position */ 2065 #define EADC_CMP2_CMPCOND_Msk (0x1ul << EADC_CMP2_CMPCOND_Pos) /*!< EADC_T::CMP2: CMPCOND Mask */ 2066 2067 #define EADC_CMP2_CMPSPL_Pos (3) /*!< EADC_T::CMP2: CMPSPL Position */ 2068 #define EADC_CMP2_CMPSPL_Msk (0x1ful << EADC_CMP2_CMPSPL_Pos) /*!< EADC_T::CMP2: CMPSPL Mask */ 2069 2070 #define EADC_CMP2_CMPMCNT_Pos (8) /*!< EADC_T::CMP2: CMPMCNT Position */ 2071 #define EADC_CMP2_CMPMCNT_Msk (0xful << EADC_CMP2_CMPMCNT_Pos) /*!< EADC_T::CMP2: CMPMCNT Mask */ 2072 2073 #define EADC_CMP2_CMPWEN_Pos (15) /*!< EADC_T::CMP2: CMPWEN Position */ 2074 #define EADC_CMP2_CMPWEN_Msk (0x1ul << EADC_CMP2_CMPWEN_Pos) /*!< EADC_T::CMP2: CMPWEN Mask */ 2075 2076 #define EADC_CMP2_CMPDAT_Pos (16) /*!< EADC_T::CMP2: CMPDAT Position */ 2077 #define EADC_CMP2_CMPDAT_Msk (0xffful << EADC_CMP2_CMPDAT_Pos) /*!< EADC_T::CMP2: CMPDAT Mask */ 2078 2079 #define EADC_CMP3_ADCMPEN_Pos (0) /*!< EADC_T::CMP3: ADCMPEN Position */ 2080 #define EADC_CMP3_ADCMPEN_Msk (0x1ul << EADC_CMP3_ADCMPEN_Pos) /*!< EADC_T::CMP3: ADCMPEN Mask */ 2081 2082 #define EADC_CMP3_ADCMPIE_Pos (1) /*!< EADC_T::CMP3: ADCMPIE Position */ 2083 #define EADC_CMP3_ADCMPIE_Msk (0x1ul << EADC_CMP3_ADCMPIE_Pos) /*!< EADC_T::CMP3: ADCMPIE Mask */ 2084 2085 #define EADC_CMP3_CMPCOND_Pos (2) /*!< EADC_T::CMP3: CMPCOND Position */ 2086 #define EADC_CMP3_CMPCOND_Msk (0x1ul << EADC_CMP3_CMPCOND_Pos) /*!< EADC_T::CMP3: CMPCOND Mask */ 2087 2088 #define EADC_CMP3_CMPSPL_Pos (3) /*!< EADC_T::CMP3: CMPSPL Position */ 2089 #define EADC_CMP3_CMPSPL_Msk (0x1ful << EADC_CMP3_CMPSPL_Pos) /*!< EADC_T::CMP3: CMPSPL Mask */ 2090 2091 #define EADC_CMP3_CMPMCNT_Pos (8) /*!< EADC_T::CMP3: CMPMCNT Position */ 2092 #define EADC_CMP3_CMPMCNT_Msk (0xful << EADC_CMP3_CMPMCNT_Pos) /*!< EADC_T::CMP3: CMPMCNT Mask */ 2093 2094 #define EADC_CMP3_CMPWEN_Pos (15) /*!< EADC_T::CMP3: CMPWEN Position */ 2095 #define EADC_CMP3_CMPWEN_Msk (0x1ul << EADC_CMP3_CMPWEN_Pos) /*!< EADC_T::CMP3: CMPWEN Mask */ 2096 2097 #define EADC_CMP3_CMPDAT_Pos (16) /*!< EADC_T::CMP3: CMPDAT Position */ 2098 #define EADC_CMP3_CMPDAT_Msk (0xffful << EADC_CMP3_CMPDAT_Pos) /*!< EADC_T::CMP3: CMPDAT Mask */ 2099 2100 #define EADC_STATUS0_VALID_Pos (0) /*!< EADC_T::STATUS0: VALID Position */ 2101 #define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) /*!< EADC_T::STATUS0: VALID Mask */ 2102 2103 #define EADC_STATUS0_OV_Pos (16) /*!< EADC_T::STATUS0: OV Position */ 2104 #define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) /*!< EADC_T::STATUS0: OV Mask */ 2105 2106 #define EADC_STATUS1_VALID_Pos (0) /*!< EADC_T::STATUS1: VALID Position */ 2107 #define EADC_STATUS1_VALID_Msk (0x7ul << EADC_STATUS1_VALID_Pos) /*!< EADC_T::STATUS1: VALID Mask */ 2108 2109 #define EADC_STATUS1_OV_Pos (16) /*!< EADC_T::STATUS1: OV Position */ 2110 #define EADC_STATUS1_OV_Msk (0x7ul << EADC_STATUS1_OV_Pos) /*!< EADC_T::STATUS1: OV Mask */ 2111 2112 #define EADC_STATUS2_ADIF0_Pos (0) /*!< EADC_T::STATUS2: ADIF0 Position */ 2113 #define EADC_STATUS2_ADIF0_Msk (0x1ul << EADC_STATUS2_ADIF0_Pos) /*!< EADC_T::STATUS2: ADIF0 Mask */ 2114 2115 #define EADC_STATUS2_ADIF1_Pos (1) /*!< EADC_T::STATUS2: ADIF1 Position */ 2116 #define EADC_STATUS2_ADIF1_Msk (0x1ul << EADC_STATUS2_ADIF1_Pos) /*!< EADC_T::STATUS2: ADIF1 Mask */ 2117 2118 #define EADC_STATUS2_ADIF2_Pos (2) /*!< EADC_T::STATUS2: ADIF2 Position */ 2119 #define EADC_STATUS2_ADIF2_Msk (0x1ul << EADC_STATUS2_ADIF2_Pos) /*!< EADC_T::STATUS2: ADIF2 Mask */ 2120 2121 #define EADC_STATUS2_ADIF3_Pos (3) /*!< EADC_T::STATUS2: ADIF3 Position */ 2122 #define EADC_STATUS2_ADIF3_Msk (0x1ul << EADC_STATUS2_ADIF3_Pos) /*!< EADC_T::STATUS2: ADIF3 Mask */ 2123 2124 #define EADC_STATUS2_ADCMPF0_Pos (4) /*!< EADC_T::STATUS2: ADCMPF0 Position */ 2125 #define EADC_STATUS2_ADCMPF0_Msk (0x1ul << EADC_STATUS2_ADCMPF0_Pos) /*!< EADC_T::STATUS2: ADCMPF0 Mask */ 2126 2127 #define EADC_STATUS2_ADCMPF1_Pos (5) /*!< EADC_T::STATUS2: ADCMPF1 Position */ 2128 #define EADC_STATUS2_ADCMPF1_Msk (0x1ul << EADC_STATUS2_ADCMPF1_Pos) /*!< EADC_T::STATUS2: ADCMPF1 Mask */ 2129 2130 #define EADC_STATUS2_ADCMPF2_Pos (6) /*!< EADC_T::STATUS2: ADCMPF2 Position */ 2131 #define EADC_STATUS2_ADCMPF2_Msk (0x1ul << EADC_STATUS2_ADCMPF2_Pos) /*!< EADC_T::STATUS2: ADCMPF2 Mask */ 2132 2133 #define EADC_STATUS2_ADCMPF3_Pos (7) /*!< EADC_T::STATUS2: ADCMPF3 Position */ 2134 #define EADC_STATUS2_ADCMPF3_Msk (0x1ul << EADC_STATUS2_ADCMPF3_Pos) /*!< EADC_T::STATUS2: ADCMPF3 Mask */ 2135 2136 #define EADC_STATUS2_ADOVIF0_Pos (8) /*!< EADC_T::STATUS2: ADOVIF0 Position */ 2137 #define EADC_STATUS2_ADOVIF0_Msk (0x1ul << EADC_STATUS2_ADOVIF0_Pos) /*!< EADC_T::STATUS2: ADOVIF0 Mask */ 2138 2139 #define EADC_STATUS2_ADOVIF1_Pos (9) /*!< EADC_T::STATUS2: ADOVIF1 Position */ 2140 #define EADC_STATUS2_ADOVIF1_Msk (0x1ul << EADC_STATUS2_ADOVIF1_Pos) /*!< EADC_T::STATUS2: ADOVIF1 Mask */ 2141 2142 #define EADC_STATUS2_ADOVIF2_Pos (10) /*!< EADC_T::STATUS2: ADOVIF2 Position */ 2143 #define EADC_STATUS2_ADOVIF2_Msk (0x1ul << EADC_STATUS2_ADOVIF2_Pos) /*!< EADC_T::STATUS2: ADOVIF2 Mask */ 2144 2145 #define EADC_STATUS2_ADOVIF3_Pos (11) /*!< EADC_T::STATUS2: ADOVIF3 Position */ 2146 #define EADC_STATUS2_ADOVIF3_Msk (0x1ul << EADC_STATUS2_ADOVIF3_Pos) /*!< EADC_T::STATUS2: ADOVIF3 Mask */ 2147 2148 #define EADC_STATUS2_ADCMPO0_Pos (12) /*!< EADC_T::STATUS2: ADCMPO0 Position */ 2149 #define EADC_STATUS2_ADCMPO0_Msk (0x1ul << EADC_STATUS2_ADCMPO0_Pos) /*!< EADC_T::STATUS2: ADCMPO0 Mask */ 2150 2151 #define EADC_STATUS2_ADCMPO1_Pos (13) /*!< EADC_T::STATUS2: ADCMPO1 Position */ 2152 #define EADC_STATUS2_ADCMPO1_Msk (0x1ul << EADC_STATUS2_ADCMPO1_Pos) /*!< EADC_T::STATUS2: ADCMPO1 Mask */ 2153 2154 #define EADC_STATUS2_ADCMPO2_Pos (14) /*!< EADC_T::STATUS2: ADCMPO2 Position */ 2155 #define EADC_STATUS2_ADCMPO2_Msk (0x1ul << EADC_STATUS2_ADCMPO2_Pos) /*!< EADC_T::STATUS2: ADCMPO2 Mask */ 2156 2157 #define EADC_STATUS2_ADCMPO3_Pos (15) /*!< EADC_T::STATUS2: ADCMPO3 Position */ 2158 #define EADC_STATUS2_ADCMPO3_Msk (0x1ul << EADC_STATUS2_ADCMPO3_Pos) /*!< EADC_T::STATUS2: ADCMPO3 Mask */ 2159 2160 #define EADC_STATUS2_CHANNEL_Pos (16) /*!< EADC_T::STATUS2: CHANNEL Position */ 2161 #define EADC_STATUS2_CHANNEL_Msk (0x1ful << EADC_STATUS2_CHANNEL_Pos) /*!< EADC_T::STATUS2: CHANNEL Mask */ 2162 2163 #define EADC_STATUS2_BUSY_Pos (23) /*!< EADC_T::STATUS2: BUSY Position */ 2164 #define EADC_STATUS2_BUSY_Msk (0x1ul << EADC_STATUS2_BUSY_Pos) /*!< EADC_T::STATUS2: BUSY Mask */ 2165 2166 #define EADC_STATUS2_ADOVIF_Pos (24) /*!< EADC_T::STATUS2: ADOVIF Position */ 2167 #define EADC_STATUS2_ADOVIF_Msk (0x1ul << EADC_STATUS2_ADOVIF_Pos) /*!< EADC_T::STATUS2: ADOVIF Mask */ 2168 2169 #define EADC_STATUS2_STOVF_Pos (25) /*!< EADC_T::STATUS2: STOVF Position */ 2170 #define EADC_STATUS2_STOVF_Msk (0x1ul << EADC_STATUS2_STOVF_Pos) /*!< EADC_T::STATUS2: STOVF Mask */ 2171 2172 #define EADC_STATUS2_AVALID_Pos (26) /*!< EADC_T::STATUS2: AVALID Position */ 2173 #define EADC_STATUS2_AVALID_Msk (0x1ul << EADC_STATUS2_AVALID_Pos) /*!< EADC_T::STATUS2: AVALID Mask */ 2174 2175 #define EADC_STATUS2_AOV_Pos (27) /*!< EADC_T::STATUS2: AOV Position */ 2176 #define EADC_STATUS2_AOV_Msk (0x1ul << EADC_STATUS2_AOV_Pos) /*!< EADC_T::STATUS2: AOV Mask */ 2177 2178 #define EADC_STATUS3_CURSPL_Pos (0) /*!< EADC_T::STATUS3: CURSPL Position */ 2179 #define EADC_STATUS3_CURSPL_Msk (0x1ful << EADC_STATUS3_CURSPL_Pos) /*!< EADC_T::STATUS3: CURSPL Mask */ 2180 2181 #define EADC_DDAT0_RESULT_Pos (0) /*!< EADC_T::DDAT0: RESULT Position */ 2182 #define EADC_DDAT0_RESULT_Msk (0xfffful << EADC_DDAT0_RESULT_Pos) /*!< EADC_T::DDAT0: RESULT Mask */ 2183 2184 #define EADC_DDAT0_OV_Pos (16) /*!< EADC_T::DDAT0: OV Position */ 2185 #define EADC_DDAT0_OV_Msk (0x1ul << EADC_DDAT0_OV_Pos) /*!< EADC_T::DDAT0: OV Mask */ 2186 2187 #define EADC_DDAT0_VALID_Pos (17) /*!< EADC_T::DDAT0: VALID Position */ 2188 #define EADC_DDAT0_VALID_Msk (0x1ul << EADC_DDAT0_VALID_Pos) /*!< EADC_T::DDAT0: VALID Mask */ 2189 2190 #define EADC_DDAT1_RESULT_Pos (0) /*!< EADC_T::DDAT1: RESULT Position */ 2191 #define EADC_DDAT1_RESULT_Msk (0xfffful << EADC_DDAT1_RESULT_Pos) /*!< EADC_T::DDAT1: RESULT Mask */ 2192 2193 #define EADC_DDAT1_OV_Pos (16) /*!< EADC_T::DDAT1: OV Position */ 2194 #define EADC_DDAT1_OV_Msk (0x1ul << EADC_DDAT1_OV_Pos) /*!< EADC_T::DDAT1: OV Mask */ 2195 2196 #define EADC_DDAT1_VALID_Pos (17) /*!< EADC_T::DDAT1: VALID Position */ 2197 #define EADC_DDAT1_VALID_Msk (0x1ul << EADC_DDAT1_VALID_Pos) /*!< EADC_T::DDAT1: VALID Mask */ 2198 2199 #define EADC_DDAT2_RESULT_Pos (0) /*!< EADC_T::DDAT2: RESULT Position */ 2200 #define EADC_DDAT2_RESULT_Msk (0xfffful << EADC_DDAT2_RESULT_Pos) /*!< EADC_T::DDAT2: RESULT Mask */ 2201 2202 #define EADC_DDAT2_OV_Pos (16) /*!< EADC_T::DDAT2: OV Position */ 2203 #define EADC_DDAT2_OV_Msk (0x1ul << EADC_DDAT2_OV_Pos) /*!< EADC_T::DDAT2: OV Mask */ 2204 2205 #define EADC_DDAT2_VALID_Pos (17) /*!< EADC_T::DDAT2: VALID Position */ 2206 #define EADC_DDAT2_VALID_Msk (0x1ul << EADC_DDAT2_VALID_Pos) /*!< EADC_T::DDAT2: VALID Mask */ 2207 2208 #define EADC_DDAT3_RESULT_Pos (0) /*!< EADC_T::DDAT3: RESULT Position */ 2209 #define EADC_DDAT3_RESULT_Msk (0xfffful << EADC_DDAT3_RESULT_Pos) /*!< EADC_T::DDAT3: RESULT Mask */ 2210 2211 #define EADC_DDAT3_OV_Pos (16) /*!< EADC_T::DDAT3: OV Position */ 2212 #define EADC_DDAT3_OV_Msk (0x1ul << EADC_DDAT3_OV_Pos) /*!< EADC_T::DDAT3: OV Mask */ 2213 2214 #define EADC_DDAT3_VALID_Pos (17) /*!< EADC_T::DDAT3: VALID Position */ 2215 #define EADC_DDAT3_VALID_Msk (0x1ul << EADC_DDAT3_VALID_Pos) /*!< EADC_T::DDAT3: VALID Mask */ 2216 2217 #define EADC_CALCTL_CAL_Pos (0) /*!< EADC_T::CALCTL: CAL Position */ 2218 #define EADC_CALCTL_CAL_Msk (0x1ul << EADC_CALCTL_CAL_Pos) /*!< EADC_T::CALCTL: CAL Mask */ 2219 2220 #define EADC_CALCTL_CALIE_Pos (1) /*!< EADC_T::CALCTL: CALIE Position */ 2221 #define EADC_CALCTL_CALIE_Msk (0x1ul << EADC_CALCTL_CALIE_Pos) /*!< EADC_T::CALCTL: CALIE Mask */ 2222 2223 #define EADC_CALSR_CALIF_Pos (16) /*!< EADC_T::CALSR: CALIF Position */ 2224 #define EADC_CALSR_CALIF_Msk (0x1ul << EADC_CALSR_CALIF_Pos) /*!< EADC_T::CALSR: CALIF Mask */ 2225 2226 #define EADC_PDMACTL_PDMATEN_Pos (0) /*!< EADC_T::PDMACTL: PDMATEN Position */ 2227 #define EADC_PDMACTL_PDMATEN_Msk (0x7fffful << EADC_PDMACTL_PDMATEN_Pos) /*!< EADC_T::PDMACTL: PDMATEN Mask */ 2228 2229 #define EADC_MCTL1_ALIGN_Pos (0) /*!< EADC_T::MCTL1: ALIGN Position */ 2230 #define EADC_MCTL1_ALIGN_Msk (0x1ul << EADC_MCTL1_ALIGN_Pos) /*!< EADC_T::MCTL1: ALIGN Mask */ 2231 2232 #define EADC_MCTL1_AVG_Pos (1) /*!< EADC_T::MCTL1: AVG Position */ 2233 #define EADC_MCTL1_AVG_Msk (0x1ul << EADC_MCTL1_AVG_Pos) /*!< EADC_T::MCTL1: AVG Mask */ 2234 2235 #define EADC_MCTL1_ACU_Pos (4) /*!< EADC_T::MCTL1: ACU Position */ 2236 #define EADC_MCTL1_ACU_Msk (0xful << EADC_MCTL1_ACU_Pos) /*!< EADC_T::MCTL1: ACU Mask */ 2237 2238 #define EADC_M0CTL1_ALIGN_Pos (0) /*!< EADC_T::M0CTL1: ALIGN Position */ 2239 #define EADC_M0CTL1_ALIGN_Msk (0x1ul << EADC_M0CTL1_ALIGN_Pos) /*!< EADC_T::M0CTL1: ALIGN Mask */ 2240 2241 #define EADC_M0CTL1_AVG_Pos (1) /*!< EADC_T::M0CTL1: AVG Position */ 2242 #define EADC_M0CTL1_AVG_Msk (0x1ul << EADC_M0CTL1_AVG_Pos) /*!< EADC_T::M0CTL1: AVG Mask */ 2243 2244 #define EADC_M0CTL1_ACU_Pos (4) /*!< EADC_T::M0CTL1: ACU Position */ 2245 #define EADC_M0CTL1_ACU_Msk (0xful << EADC_M0CTL1_ACU_Pos) /*!< EADC_T::M0CTL1: ACU Mask */ 2246 2247 #define EADC_M1CTL1_ALIGN_Pos (0) /*!< EADC_T::M1CTL1: ALIGN Position */ 2248 #define EADC_M1CTL1_ALIGN_Msk (0x1ul << EADC_M1CTL1_ALIGN_Pos) /*!< EADC_T::M1CTL1: ALIGN Mask */ 2249 2250 #define EADC_M1CTL1_AVG_Pos (1) /*!< EADC_T::M1CTL1: AVG Position */ 2251 #define EADC_M1CTL1_AVG_Msk (0x1ul << EADC_M1CTL1_AVG_Pos) /*!< EADC_T::M1CTL1: AVG Mask */ 2252 2253 #define EADC_M1CTL1_ACU_Pos (4) /*!< EADC_T::M1CTL1: ACU Position */ 2254 #define EADC_M1CTL1_ACU_Msk (0xful << EADC_M1CTL1_ACU_Pos) /*!< EADC_T::M1CTL1: ACU Mask */ 2255 2256 #define EADC_M2CTL1_ALIGN_Pos (0) /*!< EADC_T::M2CTL1: ALIGN Position */ 2257 #define EADC_M2CTL1_ALIGN_Msk (0x1ul << EADC_M2CTL1_ALIGN_Pos) /*!< EADC_T::M2CTL1: ALIGN Mask */ 2258 2259 #define EADC_M2CTL1_AVG_Pos (1) /*!< EADC_T::M2CTL1: AVG Position */ 2260 #define EADC_M2CTL1_AVG_Msk (0x1ul << EADC_M2CTL1_AVG_Pos) /*!< EADC_T::M2CTL1: AVG Mask */ 2261 2262 #define EADC_M2CTL1_ACU_Pos (4) /*!< EADC_T::M2CTL1: ACU Position */ 2263 #define EADC_M2CTL1_ACU_Msk (0xful << EADC_M2CTL1_ACU_Pos) /*!< EADC_T::M2CTL1: ACU Mask */ 2264 2265 #define EADC_M3CTL1_ALIGN_Pos (0) /*!< EADC_T::M3CTL1: ALIGN Position */ 2266 #define EADC_M3CTL1_ALIGN_Msk (0x1ul << EADC_M3CTL1_ALIGN_Pos) /*!< EADC_T::M3CTL1: ALIGN Mask */ 2267 2268 #define EADC_M3CTL1_AVG_Pos (1) /*!< EADC_T::M3CTL1: AVG Position */ 2269 #define EADC_M3CTL1_AVG_Msk (0x1ul << EADC_M3CTL1_AVG_Pos) /*!< EADC_T::M3CTL1: AVG Mask */ 2270 2271 #define EADC_M3CTL1_ACU_Pos (4) /*!< EADC_T::M3CTL1: ACU Position */ 2272 #define EADC_M3CTL1_ACU_Msk (0xful << EADC_M3CTL1_ACU_Pos) /*!< EADC_T::M3CTL1: ACU Mask */ 2273 2274 #define EADC_M4CTL1_ALIGN_Pos (0) /*!< EADC_T::M4CTL1: ALIGN Position */ 2275 #define EADC_M4CTL1_ALIGN_Msk (0x1ul << EADC_M4CTL1_ALIGN_Pos) /*!< EADC_T::M4CTL1: ALIGN Mask */ 2276 2277 #define EADC_M4CTL1_AVG_Pos (1) /*!< EADC_T::M4CTL1: AVG Position */ 2278 #define EADC_M4CTL1_AVG_Msk (0x1ul << EADC_M4CTL1_AVG_Pos) /*!< EADC_T::M4CTL1: AVG Mask */ 2279 2280 #define EADC_M4CTL1_ACU_Pos (4) /*!< EADC_T::M4CTL1: ACU Position */ 2281 #define EADC_M4CTL1_ACU_Msk (0xful << EADC_M4CTL1_ACU_Pos) /*!< EADC_T::M4CTL1: ACU Mask */ 2282 2283 #define EADC_M5CTL1_ALIGN_Pos (0) /*!< EADC_T::M5CTL1: ALIGN Position */ 2284 #define EADC_M5CTL1_ALIGN_Msk (0x1ul << EADC_M5CTL1_ALIGN_Pos) /*!< EADC_T::M5CTL1: ALIGN Mask */ 2285 2286 #define EADC_M5CTL1_AVG_Pos (1) /*!< EADC_T::M5CTL1: AVG Position */ 2287 #define EADC_M5CTL1_AVG_Msk (0x1ul << EADC_M5CTL1_AVG_Pos) /*!< EADC_T::M5CTL1: AVG Mask */ 2288 2289 #define EADC_M5CTL1_ACU_Pos (4) /*!< EADC_T::M5CTL1: ACU Position */ 2290 #define EADC_M5CTL1_ACU_Msk (0xful << EADC_M5CTL1_ACU_Pos) /*!< EADC_T::M5CTL1: ACU Mask */ 2291 2292 #define EADC_M6CTL1_ALIGN_Pos (0) /*!< EADC_T::M6CTL1: ALIGN Position */ 2293 #define EADC_M6CTL1_ALIGN_Msk (0x1ul << EADC_M6CTL1_ALIGN_Pos) /*!< EADC_T::M6CTL1: ALIGN Mask */ 2294 2295 #define EADC_M6CTL1_AVG_Pos (1) /*!< EADC_T::M6CTL1: AVG Position */ 2296 #define EADC_M6CTL1_AVG_Msk (0x1ul << EADC_M6CTL1_AVG_Pos) /*!< EADC_T::M6CTL1: AVG Mask */ 2297 2298 #define EADC_M6CTL1_ACU_Pos (4) /*!< EADC_T::M6CTL1: ACU Position */ 2299 #define EADC_M6CTL1_ACU_Msk (0xful << EADC_M6CTL1_ACU_Pos) /*!< EADC_T::M6CTL1: ACU Mask */ 2300 2301 #define EADC_M7CTL1_ALIGN_Pos (0) /*!< EADC_T::M7CTL1: ALIGN Position */ 2302 #define EADC_M7CTL1_ALIGN_Msk (0x1ul << EADC_M7CTL1_ALIGN_Pos) /*!< EADC_T::M7CTL1: ALIGN Mask */ 2303 2304 #define EADC_M7CTL1_AVG_Pos (1) /*!< EADC_T::M7CTL1: AVG Position */ 2305 #define EADC_M7CTL1_AVG_Msk (0x1ul << EADC_M7CTL1_AVG_Pos) /*!< EADC_T::M7CTL1: AVG Mask */ 2306 2307 #define EADC_M7CTL1_ACU_Pos (4) /*!< EADC_T::M7CTL1: ACU Position */ 2308 #define EADC_M7CTL1_ACU_Msk (0xful << EADC_M7CTL1_ACU_Pos) /*!< EADC_T::M7CTL1: ACU Mask */ 2309 2310 #define EADC_M8CTL1_ALIGN_Pos (0) /*!< EADC_T::M8CTL1: ALIGN Position */ 2311 #define EADC_M8CTL1_ALIGN_Msk (0x1ul << EADC_M8CTL1_ALIGN_Pos) /*!< EADC_T::M8CTL1: ALIGN Mask */ 2312 2313 #define EADC_M8CTL1_AVG_Pos (1) /*!< EADC_T::M8CTL1: AVG Position */ 2314 #define EADC_M8CTL1_AVG_Msk (0x1ul << EADC_M8CTL1_AVG_Pos) /*!< EADC_T::M8CTL1: AVG Mask */ 2315 2316 #define EADC_M8CTL1_ACU_Pos (4) /*!< EADC_T::M8CTL1: ACU Position */ 2317 #define EADC_M8CTL1_ACU_Msk (0xful << EADC_M8CTL1_ACU_Pos) /*!< EADC_T::M8CTL1: ACU Mask */ 2318 2319 #define EADC_M9CTL1_ALIGN_Pos (0) /*!< EADC_T::M9CTL1: ALIGN Position */ 2320 #define EADC_M9CTL1_ALIGN_Msk (0x1ul << EADC_M9CTL1_ALIGN_Pos) /*!< EADC_T::M9CTL1: ALIGN Mask */ 2321 2322 #define EADC_M9CTL1_AVG_Pos (1) /*!< EADC_T::M9CTL1: AVG Position */ 2323 #define EADC_M9CTL1_AVG_Msk (0x1ul << EADC_M9CTL1_AVG_Pos) /*!< EADC_T::M9CTL1: AVG Mask */ 2324 2325 #define EADC_M9CTL1_ACU_Pos (4) /*!< EADC_T::M9CTL1: ACU Position */ 2326 #define EADC_M9CTL1_ACU_Msk (0xful << EADC_M9CTL1_ACU_Pos) /*!< EADC_T::M9CTL1: ACU Mask */ 2327 2328 #define EADC_M10CTL1_ALIGN_Pos (0) /*!< EADC_T::M10CTL1: ALIGN Position */ 2329 #define EADC_M10CTL1_ALIGN_Msk (0x1ul << EADC_M10CTL1_ALIGN_Pos) /*!< EADC_T::M10CTL1: ALIGN Mask */ 2330 2331 #define EADC_M10CTL1_AVG_Pos (1) /*!< EADC_T::M10CTL1: AVG Position */ 2332 #define EADC_M10CTL1_AVG_Msk (0x1ul << EADC_M10CTL1_AVG_Pos) /*!< EADC_T::M10CTL1: AVG Mask */ 2333 2334 #define EADC_M10CTL1_ACU_Pos (4) /*!< EADC_T::M10CTL1: ACU Position */ 2335 #define EADC_M10CTL1_ACU_Msk (0xful << EADC_M10CTL1_ACU_Pos) /*!< EADC_T::M10CTL1: ACU Mask */ 2336 2337 #define EADC_M11CTL1_ALIGN_Pos (0) /*!< EADC_T::M11CTL1: ALIGN Position */ 2338 #define EADC_M11CTL1_ALIGN_Msk (0x1ul << EADC_M11CTL1_ALIGN_Pos) /*!< EADC_T::M11CTL1: ALIGN Mask */ 2339 2340 #define EADC_M11CTL1_AVG_Pos (1) /*!< EADC_T::M11CTL1: AVG Position */ 2341 #define EADC_M11CTL1_AVG_Msk (0x1ul << EADC_M11CTL1_AVG_Pos) /*!< EADC_T::M11CTL1: AVG Mask */ 2342 2343 #define EADC_M11CTL1_ACU_Pos (4) /*!< EADC_T::M11CTL1: ACU Position */ 2344 #define EADC_M11CTL1_ACU_Msk (0xful << EADC_M11CTL1_ACU_Pos) /*!< EADC_T::M11CTL1: ACU Mask */ 2345 2346 #define EADC_M12CTL1_ALIGN_Pos (0) /*!< EADC_T::M12CTL1: ALIGN Position */ 2347 #define EADC_M12CTL1_ALIGN_Msk (0x1ul << EADC_M12CTL1_ALIGN_Pos) /*!< EADC_T::M12CTL1: ALIGN Mask */ 2348 2349 #define EADC_M12CTL1_AVG_Pos (1) /*!< EADC_T::M12CTL1: AVG Position */ 2350 #define EADC_M12CTL1_AVG_Msk (0x1ul << EADC_M12CTL1_AVG_Pos) /*!< EADC_T::M12CTL1: AVG Mask */ 2351 2352 #define EADC_M12CTL1_ACU_Pos (4) /*!< EADC_T::M12CTL1: ACU Position */ 2353 #define EADC_M12CTL1_ACU_Msk (0xful << EADC_M12CTL1_ACU_Pos) /*!< EADC_T::M12CTL1: ACU Mask */ 2354 2355 #define EADC_M13CTL1_ALIGN_Pos (0) /*!< EADC_T::M13CTL1: ALIGN Position */ 2356 #define EADC_M13CTL1_ALIGN_Msk (0x1ul << EADC_M13CTL1_ALIGN_Pos) /*!< EADC_T::M13CTL1: ALIGN Mask */ 2357 2358 #define EADC_M13CTL1_AVG_Pos (1) /*!< EADC_T::M13CTL1: AVG Position */ 2359 #define EADC_M13CTL1_AVG_Msk (0x1ul << EADC_M13CTL1_AVG_Pos) /*!< EADC_T::M13CTL1: AVG Mask */ 2360 2361 #define EADC_M13CTL1_ACU_Pos (4) /*!< EADC_T::M13CTL1: ACU Position */ 2362 #define EADC_M13CTL1_ACU_Msk (0xful << EADC_M13CTL1_ACU_Pos) /*!< EADC_T::M13CTL1: ACU Mask */ 2363 2364 #define EADC_M14CTL1_ALIGN_Pos (0) /*!< EADC_T::M14CTL1: ALIGN Position */ 2365 #define EADC_M14CTL1_ALIGN_Msk (0x1ul << EADC_M14CTL1_ALIGN_Pos) /*!< EADC_T::M14CTL1: ALIGN Mask */ 2366 2367 #define EADC_M14CTL1_AVG_Pos (1) /*!< EADC_T::M14CTL1: AVG Position */ 2368 #define EADC_M14CTL1_AVG_Msk (0x1ul << EADC_M14CTL1_AVG_Pos) /*!< EADC_T::M14CTL1: AVG Mask */ 2369 2370 #define EADC_M14CTL1_ACU_Pos (4) /*!< EADC_T::M14CTL1: ACU Position */ 2371 #define EADC_M14CTL1_ACU_Msk (0xful << EADC_M14CTL1_ACU_Pos) /*!< EADC_T::M14CTL1: ACU Mask */ 2372 2373 #define EADC_M15CTL1_ALIGN_Pos (0) /*!< EADC_T::M15CTL1: ALIGN Position */ 2374 #define EADC_M15CTL1_ALIGN_Msk (0x1ul << EADC_M15CTL1_ALIGN_Pos) /*!< EADC_T::M15CTL1: ALIGN Mask */ 2375 2376 #define EADC_M15CTL1_AVG_Pos (1) /*!< EADC_T::M15CTL1: AVG Position */ 2377 #define EADC_M15CTL1_AVG_Msk (0x1ul << EADC_M15CTL1_AVG_Pos) /*!< EADC_T::M15CTL1: AVG Mask */ 2378 2379 #define EADC_M15CTL1_ACU_Pos (4) /*!< EADC_T::M15CTL1: ACU Position */ 2380 #define EADC_M15CTL1_ACU_Msk (0xful << EADC_M15CTL1_ACU_Pos) /*!< EADC_T::M15CTL1: ACU Mask */ 2381 2382 /**@}*/ /* EADC_CONST */ 2383 /**@}*/ /* end of EADC register group */ 2384 /**@}*/ /* end of REGISTER group */ 2385 2386 #if defined ( __CC_ARM ) 2387 #pragma no_anon_unions 2388 #endif 2389 2390 #endif /* __EADC_REG_H__ */ 2391
