1 /**************************************************************************//** 2 * @file dac_reg.h 3 * @version V1.00 4 * @brief DAC register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __DAC_REG_H__ 10 #define __DAC_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup DAC Digital to Analog Converter (DAC) 23 Memory Mapped Structure for DAC Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var DAC_T::CTL 32 * Offset: 0x00 DAC Control Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[0] |DACEN |DAC Enable Bit 37 * | | |0 = DAC is Disabled. 38 * | | |1 = DAC is Enabled. 39 * |[1] |DACIEN |DAC Interrupt Enable Bit 40 * | | |0 = Interrupt is Disabled. 41 * | | |1 = Interrupt is Enabled. 42 * |[2] |DMAEN |DMA Mode Enable Bit 43 * | | |0 = DMA mode Disabled. 44 * | | |1 = DMA mode Enabled. 45 * |[3] |DMAURIEN |DMA Under-run Interrupt Enable Bit 46 * | | |0 = DMA under-run interrupt Disabled. 47 * | | |1 = DMA under-run interrupt Enabled. 48 * |[4] |TRGEN |Trigger Mode Enable Bit 49 * | | |0 = DAC event trigger mode Disabled. 50 * | | |1 = DAC event trigger mode Enabled. 51 * |[7:5] |TRGSEL |Trigger Source Selection 52 * | | |000 = Software trigger. 53 * | | |001 = External pin DAC0_ST trigger. 54 * | | |010 = Timer 0 trigger. 55 * | | |011 = Timer 1 trigger. 56 * | | |100 = Timer 2 trigger. 57 * | | |101 = Timer 3 trigger. 58 * | | |110 = EPWM0 trigger. 59 * | | |111 = EPWM1 trigger. 60 * |[8] |BYPASS |Bypass Buffer Mode 61 * | | |0 = Output voltage buffer Enabled. 62 * | | |1 = Output voltage buffer Disabled. 63 * |[10] |LALIGN |DAC Data Left-aligned Enabled Control 64 * | | |0 = Right alignment. 65 * | | |1 = Left alignment. 66 * |[13:12] |ETRGSEL |External Pin Trigger Selection 67 * | | |00 = Low level trigger. 68 * | | |01 = High level trigger. 69 * | | |10 = Falling edge trigger. 70 * | | |11 = Rising edge trigger. 71 * |[15:14] |BWSEL |DAC Data Bit-width Selection 72 * | | |00 = data is 12 bits. 73 * | | |01 = data is 8 bits. 74 * | | |Others = reserved. 75 * |[16] |GRPEN |DAC Group Mode Enable Bit 76 * | | |0 = DAC0 and DAC1 are not grouped. 77 * | | |1 = DAC0 and DAC1 are grouped. 78 * @var DAC_T::SWTRG 79 * Offset: 0x04 DAC Software Trigger Control Register 80 * --------------------------------------------------------------------------------------------------- 81 * |Bits |Field |Descriptions 82 * | :----: | :----: | :---- | 83 * |[0] |SWTRG |Software Trigger 84 * | | |0 = Software trigger Disabled. 85 * | | |1 = Software trigger Enabled. 86 * | | |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0. 87 * @var DAC_T::DAT 88 * Offset: 0x08 DAC Data Holding Register 89 * --------------------------------------------------------------------------------------------------- 90 * |Bits |Field |Descriptions 91 * | :----: | :----: | :---- | 92 * |[15:0] |DACDAT |DAC 12-bit Holding Data 93 * | | |These bits are written by user software which specifies 12-bit conversion data for DAC output 94 * | | |The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware. 95 * | | |12 bit left alignment: user has to load data into DAC_DAT[15:4] bits. 96 * | | |12 bit right alignment: user has to load data into DAC_DAT[11:0] bits. 97 * @var DAC_T::DATOUT 98 * Offset: 0x0C DAC Data Output Register 99 * --------------------------------------------------------------------------------------------------- 100 * |Bits |Field |Descriptions 101 * | :----: | :----: | :---- | 102 * |[11:0] |DATOUT |DAC 12-bit Output Data 103 * | | |These bits are current digital data for DAC output conversion. 104 * | | |It is loaded from DAC_DAT register and user cannot write it directly. 105 * @var DAC_T::STATUS 106 * Offset: 0x10 DAC Status Register 107 * --------------------------------------------------------------------------------------------------- 108 * |Bits |Field |Descriptions 109 * | :----: | :----: | :---- | 110 * |[0] |FINISH |DAC Conversion Complete Finish Flag 111 * | | |0 = DAC is in conversion state. 112 * | | |1 = DAC conversion finish. 113 * | | |This bit set to 1 when conversion time counter counts to SETTLET 114 * | | |It is cleared to 0 when DAC starts a new conversion 115 * | | |User writes 1 to clear this bit to 0. 116 * |[1] |DMAUDR |DMA Under-run Interrupt Flag 117 * | | |0 = No DMA under-run error condition occurred. 118 * | | |1 = DMA under-run error condition occurred. 119 * | | |User writes 1 to clear this bit. 120 * |[8] |BUSY |DAC Busy Flag (Read Only) 121 * | | |0 = DAC is ready for next conversion. 122 * | | |1 = DAC is busy in conversion. 123 * | | |This is read only bit. 124 * @var DAC_T::TCTL 125 * Offset: 0x14 DAC Timing Control Register 126 * --------------------------------------------------------------------------------------------------- 127 * |Bits |Field |Descriptions 128 * | :----: | :----: | :---- | 129 * |[9:0] |SETTLET |DAC Output Settling Time 130 * | | |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed. 131 * | | |For example, DAC controller clock speed is 80MHz and DAC conversion settling time is 1 us, SETTLETvalue must be greater than 0x50. 132 * | | |SELTTLET = DAC controller clock speed x settling time. 133 * @var DAC_T::GRPDAT 134 * Offset: 0x30 DAC Group Mode Data Holding Register 135 * --------------------------------------------------------------------------------------------------- 136 * |Bits |Field |Descriptions 137 * | :----: | :----: | :---- | 138 * |[15:0] |DAC0DAT |DAC0 12-bit Holding Data 139 * | | |These bits are written by user software which specifies 12-bit conversion data for DAC output 140 * | | |The unused bits (DAC_GRPDAT[3:0] in left-alignment mode and DAC_GRPDAT[15:12] in right alignment mode) are ignored by DAC controller hardware. 141 * | | |12 bit left alignment: user has to load data into DAC_GRPDAT[15:4] bits. 142 * | | |12 bit right alignment: user has to load data into DAC_GRPDAT[11:0] bits. 143 * | | |Note: In group mode, user can write 12-bit conversion data for DAC0 in DAC_GRPDAT[15:0] or DAC0_DAT[15:0] 144 * | | |The advantage of writing 12-bit conversion data in DAC_GRPDAT[15:0] is that can share one PDMA transfer mechanism. 145 * | | |Note: Write 12-bit conversion data in DAC0_DAT[15:0] or DAC1_DAT[15:0] have individual PDMA transfer mechanism between two DACs 146 * |[31:16] |DAC1DAT |DAC1 12-bit Holding Data 147 * | | |In group mode, user can write these bits for DAC1 12-bit conversion data 148 * | | |The unused bits (DAC_GRPDAT[3:0] in left-alignment mode and DAC_GRPDAT[15:12] in right alignment mode) are ignored by DAC controller hardware. 149 * | | |12 bit left alignment: user has to load data into DAC_GRPDAT[15:4] bits. 150 * | | |12 bit right alignment: user has to load data into DAC_GRPDAT[11:0] bits. 151 * | | |Note: In group mode, user can write 12-bit conversion data for DAC1 in DAC_GRPDAT[31:16] or DAC1_DAT[15:0] 152 * | | |The advantage of writing 12-bit conversion data in DAC_GRPDAT[31:16] is that can share one PDMA transfer mechanism. 153 * | | |Note: Write 12-bit conversion data in DAC0_DAT[15:0] or DAC1_DAT[15:0] have individual PDMA transfer mechanism between two DACs 154 */ 155 __IO uint32_t CTL; /*!< [0x0000] DAC Control Register */ 156 __IO uint32_t SWTRG; /*!< [0x0004] DAC Software Trigger Control Register */ 157 __IO uint32_t DAT; /*!< [0x0008] DAC Data Holding Register */ 158 __I uint32_t DATOUT; /*!< [0x000c] DAC Data Output Register */ 159 __IO uint32_t STATUS; /*!< [0x0010] DAC Status Register */ 160 __IO uint32_t TCTL; /*!< [0x0014] DAC Timing Control Register */ 161 __I uint32_t RESERVE0[6]; 162 __IO uint32_t GRPDAT; /*!< [0x0030] DAC Group Mode Data Holding Register */ 163 164 } DAC_T; 165 166 /** 167 @addtogroup DAC_CONST DAC Bit Field Definition 168 Constant Definitions for DAC Controller 169 @{ */ 170 171 #define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */ 172 #define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */ 173 174 #define DAC_CTL_DACIEN_Pos (1) /*!< DAC_T::CTL: DACIEN Position */ 175 #define DAC_CTL_DACIEN_Msk (0x1ul << DAC_CTL_DACIEN_Pos) /*!< DAC_T::CTL: DACIEN Mask */ 176 177 #define DAC_CTL_DMAEN_Pos (2) /*!< DAC_T::CTL: DMAEN Position */ 178 #define DAC_CTL_DMAEN_Msk (0x1ul << DAC_CTL_DMAEN_Pos) /*!< DAC_T::CTL: DMAEN Mask */ 179 180 #define DAC_CTL_DMAURIEN_Pos (3) /*!< DAC_T::CTL: DMAURIEN Position */ 181 #define DAC_CTL_DMAURIEN_Msk (0x1ul << DAC_CTL_DMAURIEN_Pos) /*!< DAC_T::CTL: DMAURIEN Mask */ 182 183 #define DAC_CTL_TRGEN_Pos (4) /*!< DAC_T::CTL: TRGEN Position */ 184 #define DAC_CTL_TRGEN_Msk (0x1ul << DAC_CTL_TRGEN_Pos) /*!< DAC_T::CTL: TRGEN Mask */ 185 186 #define DAC_CTL_TRGSEL_Pos (5) /*!< DAC_T::CTL: TRGSEL Position */ 187 #define DAC_CTL_TRGSEL_Msk (0x7ul << DAC_CTL_TRGSEL_Pos) /*!< DAC_T::CTL: TRGSEL Mask */ 188 189 #define DAC_CTL_BYPASS_Pos (8) /*!< DAC_T::CTL: BYPASS Position */ 190 #define DAC_CTL_BYPASS_Msk (0x1ul << DAC_CTL_BYPASS_Pos) /*!< DAC_T::CTL: BYPASS Mask */ 191 192 #define DAC_CTL_LALIGN_Pos (10) /*!< DAC_T::CTL: LALIGN Position */ 193 #define DAC_CTL_LALIGN_Msk (0x1ul << DAC_CTL_LALIGN_Pos) /*!< DAC_T::CTL: LALIGN Mask */ 194 195 #define DAC_CTL_ETRGSEL_Pos (12) /*!< DAC_T::CTL: ETRGSEL Position */ 196 #define DAC_CTL_ETRGSEL_Msk (0x3ul << DAC_CTL_ETRGSEL_Pos) /*!< DAC_T::CTL: ETRGSEL Mask */ 197 198 #define DAC_CTL_BWSEL_Pos (14) /*!< DAC_T::CTL: BWSEL Position */ 199 #define DAC_CTL_BWSEL_Msk (0x3ul << DAC_CTL_BWSEL_Pos) /*!< DAC_T::CTL: BWSEL Mask */ 200 201 #define DAC_CTL_GRPEN_Pos (16) /*!< DAC_T::CTL: GRPEN Position */ 202 #define DAC_CTL_GRPEN_Msk (0x1ul << DAC_CTL_GRPEN_Pos) /*!< DAC_T::CTL: GRPEN Mask */ 203 204 #define DAC_SWTRG_SWTRG_Pos (0) /*!< DAC_T::SWTRG: SWTRG Position */ 205 #define DAC_SWTRG_SWTRG_Msk (0x1ul << DAC_SWTRG_SWTRG_Pos) /*!< DAC_T::SWTRG: SWTRG Mask */ 206 207 #define DAC_DAT_DACDAT_Pos (0) /*!< DAC_T::DAT: DACDAT Position */ 208 #define DAC_DAT_DACDAT_Msk (0xfffful << DAC_DAT_DACDAT_Pos) /*!< DAC_T::DAT: DACDAT Mask */ 209 210 #define DAC_DATOUT_DATOUT_Pos (0) /*!< DAC_T::DATOUT: DATOUT Position */ 211 #define DAC_DATOUT_DATOUT_Msk (0xffful << DAC_DATOUT_DATOUT_Pos) /*!< DAC_T::DATOUT: DATOUT Mask */ 212 213 #define DAC_STATUS_FINISH_Pos (0) /*!< DAC_T::STATUS: FINISH Position */ 214 #define DAC_STATUS_FINISH_Msk (0x1ul << DAC_STATUS_FINISH_Pos) /*!< DAC_T::STATUS: FINISH Mask */ 215 216 #define DAC_STATUS_DMAUDR_Pos (1) /*!< DAC_T::STATUS: DMAUDR Position */ 217 #define DAC_STATUS_DMAUDR_Msk (0x1ul << DAC_STATUS_DMAUDR_Pos) /*!< DAC_T::STATUS: DMAUDR Mask */ 218 219 #define DAC_STATUS_BUSY_Pos (8) /*!< DAC_T::STATUS: BUSY Position */ 220 #define DAC_STATUS_BUSY_Msk (0x1ul << DAC_STATUS_BUSY_Pos) /*!< DAC_T::STATUS: BUSY Mask */ 221 222 #define DAC_TCTL_SETTLET_Pos (0) /*!< DAC_T::TCTL: SETTLET Position */ 223 #define DAC_TCTL_SETTLET_Msk (0x3fful << DAC_TCTL_SETTLET_Pos) /*!< DAC_T::TCTL: SETTLET Mask */ 224 225 #define DAC_GRPDAT_DAC0DAT_Pos (0) /*!< DAC_T::GRPDAT: DAC0DAT Position */ 226 #define DAC_GRPDAT_DAC0DAT_Msk (0xfffful << DAC_GRPDAT_DAC0DAT_Pos) /*!< DAC_T::GRPDAT: DAC0DAT Mask */ 227 228 #define DAC_GRPDAT_DAC1DAT_Pos (16) /*!< DAC_T::GRPDAT: DAC1DAT Position */ 229 #define DAC_GRPDAT_DAC1DAT_Msk (0xfffful << DAC_GRPDAT_DAC1DAT_Pos) /*!< DAC_T::GRPDAT: DAC1DAT Mask */ 230 231 /**@}*/ /* DAC_CONST */ 232 /**@}*/ /* end of DAC register group */ 233 /**@}*/ /* end of REGISTER group */ 234 235 #if defined ( __CC_ARM ) 236 #pragma no_anon_unions 237 #endif 238 239 #endif /* __DAC_REG_H__ */ 240
