1 /**************************************************************************//** 2 * @file crc_reg.h 3 * @version V3.00 4 * @brief CRC register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __CRC_REG_H__ 10 #define __CRC_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** @addtogroup REGISTER Control Register 17 @{ 18 */ 19 20 /*---------------------- Cyclic Redundancy Check Controller -------------------------*/ 21 /** 22 @addtogroup CRC Cyclic Redundancy Check Controller (CRC) 23 Memory Mapped Structure for CRC Controller 24 @{ 25 */ 26 27 typedef struct 28 { 29 30 31 /** 32 * @var CRC_T::CTL 33 * Offset: 0x00 CRC Control Register 34 * --------------------------------------------------------------------------------------------------- 35 * |Bits |Field |Descriptions 36 * | :----: | :----: | :---- | 37 * |[0] |CRCEN |CRC Channel Enable Bit 38 * | | |0 = No effect. 39 * | | |1 = CRC operation Enabled. 40 * |[1] |CHKSINIT |Checksum Initialization 41 * | | |0 = No effect. 42 * | | |1 = Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value. 43 * | | |Note: This bit will be cleared automatically and written only. 44 * |[24] |DATREV |Write Data Bit Order Reverse 45 * | | |This bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register. 46 * | | |0 = Bit order reversed for CRC write data in Disabled. 47 * | | |1 = Bit order reversed for CRC write data in Enabled (per byte). 48 * | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB. 49 * |[25] |CHKSREV |Checksum Bit Order Reverse 50 * | | |This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register. 51 * | | |0 = Bit order reverse for CRC checksum Disabled. 52 * | | |1 = Bit order reverse for CRC checksum Enabled. 53 * | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB. 54 * |[26] |DATFMT |Write Data 1's Complement 55 * | | |This bit is used to enable the 1's complement function for write data value in CRC_DAT register. 56 * | | |0 = 1's complement for CRC writes data in Disabled. 57 * | | |1 = 1's complement for CRC writes data in Enabled. 58 * |[27] |CHKSFMT |Checksum 1's Complement 59 * | | |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register. 60 * | | |0 = 1's complement for CRC checksum Disabled. 61 * | | |0 = 1's complement for CRC checksum Enabled. 62 * |[29:28] |DATLEN |CPU Write Data Length 63 * | | |This field indicates the write data length. 64 * | | |00 = Data length is 8-bit mode. 65 * | | |01 = Data length is 16-bit mode. 66 * | | |1x = Data length is 32-bit mode. 67 * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]. 68 * |[31:30] |CRCMODE |CRC Polynomial Mode 69 * | | |This field indicates the CRC operation polynomial mode. 70 * | | |10 = CRC-16 Polynomial mode. 71 * | | |01 = CRC-8 Polynomial mode. 72 * | | |10 = CRC-16 Polynomial mode. 73 * | | |11 = CRC-32 Polynomial mode. 74 * | | |Note: User must program the polynomial value in CRC_POLYNOMIAL register to specify the polynomial used for CRC calculation. 75 * @var CRC_T::DAT 76 * Offset: 0x04 CRC Write Data Register 77 * --------------------------------------------------------------------------------------------------- 78 * |Bits |Field |Descriptions 79 * | :----: | :----: | :---- | 80 * |[31:0] |DATA |CRC Write Data Bits 81 * | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation. 82 * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]. 83 * @var CRC_T::SEED 84 * Offset: 0x08 CRC Seed Register 85 * --------------------------------------------------------------------------------------------------- 86 * |Bits |Field |Descriptions 87 * | :----: | :----: | :---- | 88 * |[31:0] |SEED |CRC Seed Value 89 * | | |This field indicates the CRC seed value. 90 * | | |Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]). 91 * @var CRC_T::CHECKSUM 92 * Offset: 0x0C CRC Checksum Register 93 * --------------------------------------------------------------------------------------------------- 94 * |Bits |Field |Descriptions 95 * | :----: | :----: | :---- | 96 * |[31:0] |CHECKSUM |CRC Checksum Results 97 * | | |This field indicates the CRC checksum result. 98 * | | |Note: The valid bits of CRC_CHECKSUM[31:0] is correlated to CRCMODE (CRC_CTL[31:30]). 99 * @var CRC_T::POLYNOMIAL 100 * Offset: 0x10 CRC Polynomial Register 101 * --------------------------------------------------------------------------------------------------- 102 * |Bits |Field |Descriptions 103 * | :----: | :----: | :---- | 104 * |[31:0] |POLYNOMIAL |CRC Polynomial Register 105 * | | |This field indicates the value of CRC polynomial. 106 */ 107 __IO uint32_t CTL; /*!< [0x0000] CRC Control Register */ 108 __IO uint32_t DAT; /*!< [0x0004] CRC Write Data Register */ 109 __IO uint32_t SEED; /*!< [0x0008] CRC Seed Register */ 110 __I uint32_t CHECKSUM; /*!< [0x000c] CRC Checksum Register */ 111 __IO uint32_t POLYNOMIAL; /*!< [0x0010] CRC Polynomial Register */ 112 113 } CRC_T; 114 115 /** 116 @addtogroup CRC_CONST CRC Bit Field Definition 117 Constant Definitions for CRC Controller 118 @{ 119 */ 120 121 #define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */ 122 #define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */ 123 124 #define CRC_CTL_CHKSINIT_Pos (1) /*!< CRC_T::CTL: CHKSINIT Position */ 125 #define CRC_CTL_CHKSINIT_Msk (0x1ul << CRC_CTL_CHKSINIT_Pos) /*!< CRC_T::CTL: CHKSINIT Mask */ 126 127 #define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */ 128 #define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */ 129 130 #define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */ 131 #define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */ 132 133 #define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */ 134 #define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */ 135 136 #define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */ 137 #define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */ 138 139 #define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */ 140 #define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */ 141 142 #define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */ 143 #define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */ 144 145 #define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */ 146 #define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */ 147 148 #define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */ 149 #define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */ 150 151 #define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */ 152 #define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */ 153 154 #define CRC_POLYNOMIAL_POLYNOMIAL_Pos (0) /*!< CRC_T::POLYNOMIAL: POLYNOMIAL Position */ 155 #define CRC_POLYNOMIAL_POLYNOMIAL_Msk (0xfffffffful << CRC_POLYNOMIAL_POLYNOMIAL_Pos) /*!< CRC_T::POLYNOMIAL: POLYNOMIAL Mask */ 156 157 158 /**@}*/ /* CRC_CONST */ 159 /**@}*/ /* end of CRC register group */ 160 /**@}*/ /* end of REGISTER group */ 161 162 #if defined ( __CC_ARM ) 163 #pragma no_anon_unions 164 #endif 165 166 #endif /* __CRC_REG_H__ */ 167
