1 /**************************************************************************//** 2 * @file acmp_reg.h 3 * @version V1.00 4 * @brief ACMP register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __ACMP_REG_H__ 10 #define __ACMP_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 17 /******************************************************************************/ 18 /* Device Specific Peripheral registers structures */ 19 /******************************************************************************/ 20 21 /** @addtogroup REGISTER Control Register 22 23 @{ 24 25 */ 26 27 28 /*---------------------- Analog Comparator Controller -------------------------*/ 29 /** 30 @addtogroup ACMP Analog Comparator Controller (ACMP) 31 Memory Mapped Structure for ACMP Controller 32 @{ */ 33 34 typedef struct 35 { 36 37 38 /** 39 * @var ACMP_T::CTL0 40 * Offset: 0x00 Analog Comparator 0 Control Register 41 * --------------------------------------------------------------------------------------------------- 42 * |Bits |Field |Descriptions 43 * | :----: | :----: | :---- | 44 * |[0] |ACMPEN |Comparator Enable Bit 45 * | | |0 = Comparator 0 Disabled. 46 * | | |1 = Comparator 0 Enabled. 47 * |[1] |ACMPIE |Comparator Interrupt Enable Bit 48 * | | |0 = Comparator 0 interrupt Disabled. 49 * | | |1 = Comparator 0 interrupt Enabled 50 * | | |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well. 51 * |[2] |HYSEN |Comparator Hysteresis Enable Bit 52 * | | |0 = Comparator 0 hysteresis Disabled. 53 * | | |1 = Comparator 0 hysteresis Enabled. 54 * | | |Note: If HYSEN = 0, user can adjust HYS by HYSSEL. 55 * | | |Note: If HYSEN = 1, HYSSEL is invalid. The Hysterresis is fixed to 30mV. 56 * |[3] |ACMPOINV |Comparator Output Inverse 57 * | | |0 = Comparator 0 output inverse Disabled. 58 * | | |1 = Comparator 0 output inverse Enabled. 59 * |[5:4] |NEGSEL |Comparator Negative Input Selection 60 * | | |00 = ACMP0_N pin. 61 * | | |01 = Internal comparator reference voltage (CRV0). 62 * | | |10 = Band-gap voltage. 63 * | | |11 = DAC0 output. 64 * | | |Note: NEGSEL must select 2'b01 in calibration mode. 65 * |[7:6] |POSSEL |Comparator Positive Input Selection 66 * | | |00 = Input from ACMP0_P0. 67 * | | |01 = Input from ACMP0_P1. 68 * | | |10 = Input from ACMP0_P2. 69 * | | |11 = Input from ACMP0_P3. 70 * |[9:8] |INTPOL |Interrupt Condition Polarity Selection 71 * | | |ACMPIF0 will be set to 1 when comparator output edge condition is detected. 72 * | | |00 = Rising edge or falling edge. 73 * | | |01 = Rising edge. 74 * | | |10 = Falling edge. 75 * | | |11 = Reserved. 76 * |[12] |OUTSEL |Comparator Output Select 77 * | | |0 = Comparator 0 output to ACMP0_O pin is unfiltered comparator output. 78 * | | |1 = Comparator 0 output to ACMP0_O pin is from filter output. 79 * |[15:13] |FILTSEL |Comparator Output Filter Count Selection 80 * | | |000 = Filter function is Disabled. 81 * | | |001 = ACMP0 output is sampled 1 consecutive PCLK. 82 * | | |010 = ACMP0 output is sampled 2 consecutive PCLKs. 83 * | | |011 = ACMP0 output is sampled 4 consecutive PCLKs. 84 * | | |100 = ACMP0 output is sampled 8 consecutive PCLKs. 85 * | | |101 = ACMP0 output is sampled 16 consecutive PCLKs. 86 * | | |110 = ACMP0 output is sampled 32 consecutive PCLKs. 87 * | | |111 = ACMP0 output is sampled 64 consecutive PCLKs. 88 * |[16] |WKEN |Power-down Wake-up Enable Bit 89 * | | |0 = Wake-up function Disabled. 90 * | | |1 = Wake-up function Enabled. 91 * |[17] |WLATEN |Window Latch Mode Enable Bit 92 * | | |0 = Window Latch Mode Disabled. 93 * | | |1 = Window Latch Mode Enabled. 94 * |[18] |WCMPSEL |Window Compare Mode Selection 95 * | | |0 = Window Compare Mode Disabled. 96 * | | |1 = Window Compare Mode is Selected. 97 * |[21:20] |FCLKDIV |Comparator Output Filter Clock Divider 98 * | | |00 = cComparator output filter clock = PCLK 99 * | | |01 = cComparator output filter clock = PCLK/2 100 * | | |10 = cComparator output filter clock = PCLK/4 101 * | | |11 = Reserved 102 * | | |Note: uUse FCLKDIV must under the condition fof FILTSEL = 3u2019h7, then set FCLKDIV canto get the effect of filtering 128,256 consecutive PCLKs. 103 * |[26:24] |HYSSEL |Hysteresis Mode Selection 104 * | | |000 = Hysteresis is 0mV. 105 * | | |001 = Hysteresis is 10mV. 106 * | | |010 = Hysteresis is 20mV. 107 * | | |011 = Hysteresis is 30mV. 108 * | | |100 = Hysteresis is 40mV 109 * | | |101 = Hysteresis is 50mV 110 * | | |Others = rReserved 111 * |[29:28] |MODESEL |Comparator Power Mode Selection 112 * | | |00 = low power mode comparator AVDD current 1uA 113 * | | |01 = low power mode comparator AVDD current 2uA 114 * | | |10 = active mode comparator AVDD current 35uA 115 * | | |11 = active mode comparator AVDD current 70uA 116 * @var ACMP_T::CTL1 117 * Offset: 0x04 Analog Comparator 1 Control Register 118 * --------------------------------------------------------------------------------------------------- 119 * |Bits |Field |Descriptions 120 * | :----: | :----: | :---- | 121 * |[0] |ACMPEN |Comparator Enable Bit 122 * | | |0 = Comparator 1 Disabled. 123 * | | |1 = Comparator 1 Enabled. 124 * |[1] |ACMPIE |Comparator Interrupt Enable Bit 125 * | | |0 = Comparator 1 interrupt Disabled. 126 * | | |1 = Comparator 1 interrupt Enabled 127 * | | |If WKEN (ACMP_CTL1[16]) is set to 1, the wake-up interrupt function will be enabled as well. 128 * |[2] |HYSEN |Comparator Hysteresis Enable Bit 129 * | | |0 = Comparator 1 hysteresis Disabled. 130 * | | |1 = Comparator 1 hysteresis Enabled. 131 * | | |Note: If HYSEN = 0, user can adjust HYS by HYSSEL. 132 * | | |Note: If HYSEN = 1, HYSSEL is invalid. The Hysterresis is fixed to 30mV. 133 * |[3] |ACMPOINV |Comparator Output Inverse Control 134 * | | |0 = Comparator 1 output inverse Disabled. 135 * | | |1 = Comparator 1 output inverse Enabled. 136 * |[5:4] |NEGSEL |Comparator Negative Input Selection 137 * | | |00 = ACMP1_N pin. 138 * | | |01 = Internal comparator reference voltage (CRV1). 139 * | | |10 = Band-gap voltage. 140 * | | |11 = DAC0 output. 141 * | | |Note: NEGSEL must select 2'b01 in calibration mode. 142 * |[7:6] |POSSEL |Comparator Positive Input Selection 143 * | | |00 = Input from ACMP1_P0. 144 * | | |01 = Input from ACMP1_P1. 145 * | | |10 = Input from ACMP1_P2. 146 * | | |11 = Input from ACMP1_P3. 147 * |[9:8] |INTPOL |Interrupt Condition Polarity Selection 148 * | | |ACMPIF1 will be set to 1 when comparator output edge condition is detected. 149 * | | |00 = Rising edge or falling edge. 150 * | | |01 = Rising edge. 151 * | | |10 = Falling edge. 152 * | | |11 = Reserved. 153 * |[12] |OUTSEL |Comparator Output Select 154 * | | |0 = Comparator 1 output to ACMP1_O pin is unfiltered comparator output. 155 * | | |1 = Comparator 1 output to ACMP1_O pin is from filter output. 156 * |[15:13] |FILTSEL |Comparator Output Filter Count Selection 157 * | | |000 = Filter function is Disabled. 158 * | | |001 = ACMP1 output is sampled 1 consecutive PCLK. 159 * | | |010 = ACMP1 output is sampled 2 consecutive PCLKs. 160 * | | |011 = ACMP1 output is sampled 4 consecutive PCLKs. 161 * | | |100 = ACMP1 output is sampled 8 consecutive PCLKs. 162 * | | |101 = ACMP1 output is sampled 16 consecutive PCLKs. 163 * | | |110 = ACMP1 output is sampled 32 consecutive PCLKs. 164 * | | |111 = ACMP1 output is sampled 64 consecutive PCLKs. 165 * |[16] |WKEN |Power-down Wakeup Enable Bit 166 * | | |0 = Wake-up function Disabled. 167 * | | |1 = Wake-up function Enabled. 168 * |[17] |WLATEN |Window Latch Mode Enable Bit 169 * | | |0 = Window Latch Mode Disabled. 170 * | | |1 = Window Latch Mode Enabled. 171 * |[18] |WCMPSEL |Window Compare Mode Selection 172 * | | |0 = Window Compare Mode Disabled. 173 * | | |1 = Window Compare Mode is Selected. 174 * |[21:20] |FCLKDIV |Comparator Output Filter Clock Divider 175 * | | |00 = comparator output filter clock = PCLK 176 * | | |01 = comparator output filter clock = PCLK/2 177 * | | |10 = comparator output filter clock = PCLK/4 178 * | | |11 = Reserved 179 * |[26:24] |HYSSEL |Hysteresis Mode Selection 180 * | | |000 = Hysteresis is 0mV. 181 * | | |001 = Hysteresis is 10mV. 182 * | | |010 = Hysteresis is 20mV. 183 * | | |011 = Hysteresis is 30mV. 184 * | | |100 = Hysteresis is 40mV 185 * | | |101 = Hysteresis is 50mV 186 * | | |Others = rReserved00 = Hysteresis is 0mV. 187 * | | |01 = Hysteresis is 10mV. 188 * | | |10 = Hysteresis is 20mV. 189 * | | |11 = Hysteresis is 30mV. 190 * |[29:28] |MODESEL |Comparator Power Mode Selection 191 * | | |00 = low power mode comparator AVDD current 1uA 192 * | | |01 = low power mode comparator AVDD current 2uA 193 * | | |10 = active mode comparator AVDD current 35uA 194 * | | |11 = active mode comparator AVDD current 70uA 195 * @var ACMP_T::STATUS 196 * Offset: 0x08 Analog Comparator Status Register 197 * --------------------------------------------------------------------------------------------------- 198 * |Bits |Field |Descriptions 199 * | :----: | :----: | :---- | 200 * |[0] |ACMPIF0 |Comparator 0 Interrupt Flag 201 * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output 202 * | | |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1. 203 * | | |Note: Write 1 to clear this bit to 0. 204 * |[1] |ACMPIF1 |Comparator 1 Interrupt Flag 205 * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output 206 * | | |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1. 207 * | | |Note: Write 1 to clear this bit to 0. 208 * |[4] |ACMPO0 |Comparator 0 Output 209 * | | |Synchronized to the PCLK to allow reading by software 210 * | | |Cleared when the comparator 0 is disabled, i.e 211 * | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0. 212 * |[5] |ACMPO1 |Comparator 1 Output 213 * | | |Synchronized to the PCLK to allow reading by software 214 * | | |Cleared when the comparator 1 is disabled, i.e 215 * | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0. 216 * |[8] |WKIF0 |Comparator 0 Power-down Wake-up Interrupt Flag 217 * | | |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs. 218 * | | |0 = No power-down wake-up occurred. 219 * | | |1 = Power-down wake-up occurred. 220 * | | |Note: Write 1 to clear this bit to 0. 221 * |[9] |WKIF1 |Comparator 1 Power-down Wake-up Interrupt Flag 222 * | | |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs. 223 * | | |0 = No power-down wake-up occurred. 224 * | | |1 = Power-down wake-up occurred. 225 * | | |Note: Write 1 to clear this bit to 0. 226 * |[12] |ACMPS0 |Comparator 0 Status 227 * | | |Synchronized to the PCLK to allow reading by software 228 * | | |Cleared when the comparator 0 is disabled, i.e 229 * | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0. 230 * |[13] |ACMPS1 |Comparator 1 Status 231 * | | |Synchronized to the PCLK to allow reading by software 232 * | | |Cleared when the comparator 1 is disabled, i.e 233 * | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0. 234 * |[16] |ACMPWO |Comparator Window Output 235 * | | |This bit shows the output status of window compare mode 236 * | | |0 = The positive input voltage is outside the window. 237 * | | |1 = The positive input voltage is in the window. 238 * @var ACMP_T::VREF 239 * Offset: 0x0C Analog Comparator Reference Voltage Control Register 240 * --------------------------------------------------------------------------------------------------- 241 * |Bits |Field |Descriptions 242 * | :----: | :----: | :---- | 243 * |[5:0] |CRV0SEL |Comparator0Comparator 0 Reference Voltage Setting 244 * | | |CRV0 = CRV0 source voltage * (ACMP_VREF01[5:0] )/ 631/6+CRVCTL/24). 245 * |[6] |CRV0SSEL |CRV0 Source Voltage Selection 246 * | | |0 = AVDD is selected as CRV0 source voltage. 247 * | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV0 source voltage. 248 * |[8] |CRV0EN |CRV0 Enable Bit 249 * | | |0 = CRV0 is dDisabled. 250 * | | |1 = CRV0 is eEnabled. 251 * |[21:16] |CRV1SEL |Comparator1Comparator 1 Reference Voltage Setting 252 * | | |CRV1 = CRV1 source voltage * (ACMP_VREF01[21:16] )/ 63. 253 * |[22] |CRV1SSEL |CRV1 Source Voltage Selection 254 * | | |0 = AVDD is selected as CRV1 source voltage. 255 * | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV1 source voltage. 256 * |[24] |CRV1EN |CRV1 Enable Bit 257 * | | |0 = CRV1 is dDisabled. 258 * | | |1 = CRV1 Eis enabled. 259 * |[31] |CLAMPEN |Current Level Control Selection under Speed Up Function 260 * | | |0 = ACMP run on high SPEED mode with high quiescent current 261 * | | |1 = ACMP run on low SPEED mode with high quiescent current 262 * | | |Note: Comparator speed up function only support SPEED[1:0]=2bu201911 & 2bu201910 263 * @var ACMP_T::CALCTL 264 * Offset: 0x10 Analog Comparator Calibration Control Register 265 * --------------------------------------------------------------------------------------------------- 266 * |Bits |Field |Descriptions 267 * | :----: | :----: | :---- | 268 * |[0] |CALTRG0 |Comparator0Comparator 0 Calibration Trigger Bit 269 * | | |0 = Calibration is stopped. 270 * | | |1 = Calibration is triggered. 271 * | | |Note 1: Before this bit is enabled, ACMPEN(ACMP_CTL0[0]) should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance. 272 * | | |Note 2: Hardware will auto clear this bit when the next calibration is triggered by software. 273 * | | |Note 3: If user must trigger calibration twice or more times, the second trigger haves to wait at least 300us after the previous calibration is done. 274 * |[1] |CALTRG1 |Comparator1Comparator 1 Calibration Trigger Bit 275 * | | |0 = Calibration is stopped. 276 * | | |1 = Calibration is triggered. 277 * | | |Note 1: Before this bit is enabled, ACMPEN(ACMP_CTL1[0]) should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance. 278 * | | |Note 2: Hardware will auto clear this bit when the next calibration is triggered by software. 279 * | | |Note 3: If user must trigger calibration twice or more times, the second trigger haves to wait at least 300us after the previous calibration is done. 280 * |[5:4] |CALCLK0 |Comparator0Comparator 0 Calibration Clock Rate Selection 281 * | | |00 = 1.5 kHz. 282 * | | |01 = 6 kHz. 283 * | | |10 = 24kHz. 284 * | | |11 = 95 kHz. 285 * |[7:6] |CALCLK1 |Comparator1Comparator 1 Calibration Clock Rate Selection 286 * | | |00 = 1.5 kHz. 287 * | | |01 = 6 kHz. 288 * | | |10 = 24kHz. 289 * | | |11 = 95 kHz. 290 * |[8] |OFFSETSEL |Comparator Trim Code Selection 291 * | | |0 = calibration trim code will not minus 1 when calibrated done. 292 * | | |1 = calibration trim code will not minus 1 when calibrated done. 293 * |[17:16] |CALRVS |Calibration Reference Voltage Selection 294 * | | |00 = option0 (N-pair calibration: 5V - 80mV, P-pair calibration: 80mV) 295 * | | |01 = option1 296 * | | |10 = option2 (N-pair calibration: 5V - 160mV, P-pair calibration: 160mV) 297 * | | |11 = Reserved 298 * | | |Note: CRV0 and CRV1 must be the same setting in calibration 299 * | | |Note: The details refer to Analog ACMP SPEC 300 * @var ACMP_T::CALSTS 301 * Offset: 0x14 Analog Comparator Calibration Status Register 302 * --------------------------------------------------------------------------------------------------- 303 * |Bits |Field |Descriptions 304 * | :----: | :----: | :---- | 305 * |[0] |DONE0 |Comparator 0 Calibration Done Status 306 * | | |0 = Calibrating. 307 * | | |1 = Calibration Ddone. 308 * | | |NOTE: this bit is write 1 clear 309 * |[4] |DONE1 |Comparator 1 Calibration Done Status 310 * | | |0 = Calibrating. 311 * | | |1 = Calibration Ddone. 312 * | | |NOTE: this bit is write 1 clear 313 * @var ACMP_T::COFF 314 * Offset: 0xFF0 Analog Comparator Calibration Offset Register 315 * --------------------------------------------------------------------------------------------------- 316 * |Bits |Field |Descriptions 317 * | :----: | :----: | :---- | 318 * |[3:0] |NCODE0 |Comparator0Comparator 0 Offset of NMOS 319 * | | |ACMP0 offset canceling trim code of NMOS 320 * | | |Note: 1. Once ACMP0 is enabled, reading these bits will gets initial value from ROMMAP46[19:16] 321 * | | |2. write MODESEL ACMP_CTL0[29:28] will decide NCODE0 load from which ROMMAP 322 * | | | MODESEL = 2'b00, NCODE0 load from ROMMAP46[3:0] 323 * | | | MODESEL = 2'b01, NCODE0 load from ROMMAP46[19:16] 324 * | | | MODESEL = 2'b10, NCODE0 load from ROMMAP47[3:0] 325 * | | | MODESEL = 2'b11, NCODE0 load from ROMMAP47[19:16] 326 * |[7] |NSEL0 |Comparator0Comparator 0 Offset of NMOS 327 * | | |0 = trim NMOS negative offset 328 * | | |1 = trim NMOS positive offset 329 * | | |Note: 1. Once ACMP0 is enabled, reading this bit default will get initial value from ROMMAP46[20] 330 * | | | 2. write MODESEL ACMP_CTL0[29:28] will decide NSEL0 load from which ROMMAP 331 * | | | MODESEL = 2'b00, NSEL0 load from ROMMAP46[4] 332 * | | | MODESEL = 2'b01, NSEL0 load from ROMMAP46[20] 333 * | | | MODESEL = 2'b10, NSEL0 load from ROMMAP47[4] 334 * | | | MODESEL = 2'b11, NSEL0 load from ROMMAP47[20] 335 * | | |2 336 * | | |If ACMP0 is enabled and CALTRG0 (ACMP_CALCTL01[0]]) is set, after calibration done DONE0(ACMP_CALSRTS01[0]) will get NSEL0 value 337 * |[11:8] |PCODE0 |Comparator0Comparator 0 Offset of PMOS 338 * | | |ACMP0 offset canceling trim code of PMOS 339 * | | |Note: 1. Once ACMP0 is enabled, reading these bits default will get initial value from ROMMAP46[27:24] 340 * | | |2. write MODESEL ACMP_CTL0[29:28] will decide PCODE0 load from which ROMMAP 341 * | | | MODESEL = 2'b00, PCODE0 load from ROMMAP46[11:8] 342 * | | | MODESEL = 2'b01, PCODE0 load from ROMMAP46[27:24] 343 * | | | MODESEL = 2'b10, PCODE0 load from ROMMAP47[11:8] 344 * | | | MODESEL = 2'b11, PCODE0 load from ROMMAP47[27:24] 345 * |[15] |PSEL0 |Comparator0Comparator 0 Offset of PMOS 346 * | | |0 = trim PMOS negative offset 347 * | | |1 = trim PMOS positive offset 348 * | | |Note: 1. Once ACMP0 is enabled, reading this bit default will get initial value from ROMMAP46[28]. 349 * | | |2. write MODESEL ACMP_CTL0[29:28] will decide PSEL0 load from which ROMMAP 350 * | | | MODESEL = 2'b00, PSEL0 load from ROMMAP46[12] 351 * | | | MODESEL = 2'b01, PSEL0 load from ROMMAP48[28] 352 * | | | MODESEL = 2'b10, PSEL0 load from ROMMAP47[12] 353 * | | | MODESEL = 2'b11, PSEL0 load from ROMMAP47[28] 354 * | | |3 355 * | | |If ACMP0 is enabled and CALTRG0 (ACMP_CALCTL01[0]]) is set, after calibration done DONE0(ACMP_CALSACMP_CALSTS01R[0]) will get PSEL0 value 356 * |[19:16] |NCODE1 |Comparator 1 Offset of NMOS 357 * | | |ACMP1 offset canceling trim code of PMOS 358 * | | |Note: 1. Once ACMP1 is enabled, reading these bits default will get initial value from ROMMAP48[19:16] 359 * | | |2. write MODESEL ACMP_CTL1[29:28] will decide NCODE1 load from which ROMMAP 360 * | | | MODESEL = 2'b00, NCODE1load from ROMMAP48[3:0] 361 * | | | MODESEL = 2'b01, NCODE1 load from ROMMAP48[19:16] 362 * | | | MODESEL = 2'b10, NCODE1 load from ROMMAP49[3:0] 363 * | | | MODESEL = 2'b11, NCODE1 load from ROMMAP49[19:16] 364 * |[23] |NSEL1 |Comparator 1 Offset of NMOS 365 * | | |0 = trim NMOS negative offset 366 * | | |1 = trim NMOS positive offset 367 * | | |Note: 1. Once ACMP1 is enabled, reading this bit default will get initial value from ROMMAP48[20] 368 * | | | 2. write MODESEL ACMP_CTL1[29:28] will decide NSEL1 load from which ROMMAP 369 * | | | MODESEL = 2'b00, NSEL1 load from ROMMAP48[4] 370 * | | | MODESEL = 2'b01, NSEL1 load from ROMMAP48[20] 371 * | | | MODESEL = 2'b10, NSEL1 load from ROMMAP49[4] 372 * | | | MODESEL = 2'b11, NSEL1 load from ROMMAP49[20] 373 * | | |3 374 * | | |If ACMP1 is enabled and CALTRG1 (ACMP_CALCTL01[1]]) is set, after calibration done DONE1(ACMP_CALSRTS01[4]) will get NSEL1 value 375 * |[27:24] |PCODE1 |Comparator 1 Offset of PMOS 376 * | | |ACMP1 offset canceling trim code of PMOS 377 * | | |Note: 1. Once ACMP1 is enabled, reading these bits default will get initial value from ROMMAP48[27:24] 378 * | | |2. write MODESEL ACMP_CTL1[29:28] will decide PCODE1 load from which ROMMAP 379 * | | | MODESEL = 2'b00, PCODE1 load from ROMMAP48[11:8] 380 * | | | MODESEL = 2'b01, PCODE1 load from ROMMAP48[27:24] 381 * | | | MODESEL = 2'b10, PCODE1 load from ROMMAP49[11:8] 382 * | | | MODESEL = 2'b11, PCODE1 load from ROMMAP49[27:24] 383 * |[31] |PSEL1 |Comparator 1 Offset of PMOS 384 * | | |0 = trim PMOS negative offset 385 * | | |1 = trim PMOS positive offset 386 * | | |Note: 1. Once ACMP1 is enabled, reading this bit default will get initial value from ROMMAP48[28] 387 * | | | 2. write MODESEL ACMP_CTL1[29:28] will decide PSEL1 load from which ROMMAP 388 * | | | MODESEL = 2'b00, PSEL1 load from ROMMAP48[12] 389 * | | | MODESEL = 2'b01, PSEL1 load from ROMMAP48[28] 390 * | | | MODESEL = 2'b10, PSEL1 load from ROMMAP49[12] 391 * | | | MODESEL = 2'b11, PSEL1 load from ROMMAP49[28] 392 * | | |3 393 * | | |If ACMP1 is enabled and CALTRG1 (ACMP_CALCTL01[1]]) is set, after calibration done DONE1(ACMP_CALSRTS01[4]) will get PSEL1 value 394 * @var ACMP_T::TEST 395 * Offset: 0xFF8 Analog Comparator Test Control Register 396 * --------------------------------------------------------------------------------------------------- 397 * |Bits |Field |Descriptions 398 * | :----: | :----: | :---- | 399 * |[0] |CRV0TEST |CRV0 Test Mode Enable Bit (Write Protect) 400 * | | |0 = No effect. 401 * | | |1 = CRV voltage output to ACMP0_N pin for voltage measure. 402 * | | |This bit is designed for Nuvoton Lab use only. 403 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 404 * | | |Note: NEGSEL (ACMP_CTL0[5:4]) or NEGSEL (ACMP_CTL1[5:4]) must select to 2'b01 in CRV test mode 405 * |[1] |CRV1TEST |CRV1 Test Mode Enable Bit (Write Protect) 406 * | | |0 = No effect. 407 * | | |1 = CRV voltage output to ACMP0_N pin for voltage measure. 408 * | | |This bit is designed for Nuvoton Lab use only. 409 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 410 * | | |Note: NEGSEL (ACMP_CTL0[5:4]) or NEGSEL (ACMP_CTL1[5:4]) must select to 2'b01 in CRV test mode 411 * |[4] |OUTSEL |Comparator CRV Output Source Selection 412 * | | |0 = CRV output from resistor string 413 * | | |1 = CRV output from bandgap voltage 414 * |[8] |HYSBYPASS |Hysteresis Adjust Function Selection 415 * | | |0 = Enable adjust function 416 * | | |1 = Bypass adjust function 417 * @var ACMP_T::VERSION 418 * Offset: 0xFFC Analog Comparator RTL Design Version Number 419 * --------------------------------------------------------------------------------------------------- 420 * |Bits |Field |Descriptions 421 * | :----: | :----: | :---- | 422 * |[15:0] |MINOR |Comp RTL Design MINOR Version Number 423 * | | |Minor version number is dependent on module ECO version control. 424 * |[23:16] |SUB |Comp RTL Design SUB Version Number 425 * | | |Major version number is correlated to Product Line. 426 * |[31:24] |MAJOR |Comp RTL Design MAJOR Version Number 427 * | | |Major version number is correlated to Product Line. 428 */ 429 __IO uint32_t CTL[2]; /*!< [0x0000-0x0004] Analog Comparator 0/1 Control Register */ 430 __IO uint32_t STATUS; /*!< [0x0008] Analog Comparator Status Register */ 431 __IO uint32_t VREF; /*!< [0x000c] Analog Comparator Reference Voltage Control Register */ 432 __IO uint32_t CALCTL; /*!< [0x0010] Analog Comparator Calibration Control Register */ 433 __IO uint32_t CALSTS; /*!< [0x0014] Analog Comparator Calibration Status Register */ 434 __I uint32_t RESERVE0[1014]; 435 __IO uint32_t COFF; /*!< [0x0ff0] Analog Comparator Calibration Offset Register */ 436 __I uint32_t RESERVE1[1]; 437 __IO uint32_t TEST; /*!< [0x0ff8] Analog Comparator Test Control Register */ 438 __I uint32_t VERSION; /*!< [0x0ffc] Analog Comparator RTL Design Version Number */ 439 440 } ACMP_T; 441 442 /** 443 @addtogroup ACMP_CONST ACMP Bit Field Definition 444 Constant Definitions for ACMP Controller 445 @{ */ 446 447 #define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP_T::CTL0: ACMPEN Position */ 448 #define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP_T::CTL0: ACMPEN Mask */ 449 450 #define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP_T::CTL0: ACMPIE Position */ 451 #define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP_T::CTL0: ACMPIE Mask */ 452 453 #define ACMP_CTL_HYSEN_Pos (2) /*!< ACMP_T::CTL0: HYSEN Position */ 454 #define ACMP_CTL_HYSEN_Msk (0x1ul << ACMP_CTL_HYSEN_Pos) /*!< ACMP_T::CTL0: HYSEN Mask */ 455 456 #define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP_T::CTL0: ACMPOINV Position */ 457 #define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP_T::CTL0: ACMPOINV Mask */ 458 459 #define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP_T::CTL0: NEGSEL Position */ 460 #define ACMP_CTL_NEGSEL_Msk (0x3ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_T::CTL0: NEGSEL Mask */ 461 462 #define ACMP_CTL_POSSEL_Pos (6) /*!< ACMP_T::CTL0: POSSEL Position */ 463 #define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP_T::CTL0: POSSEL Mask */ 464 465 #define ACMP_CTL_INTPOL_Pos (8) /*!< ACMP_T::CTL0: INTPOL Position */ 466 #define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) /*!< ACMP_T::CTL0: INTPOL Mask */ 467 468 #define ACMP_CTL_OUTSEL_Pos (12) /*!< ACMP_T::CTL0: OUTSEL Position */ 469 #define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) /*!< ACMP_T::CTL0: OUTSEL Mask */ 470 471 #define ACMP_CTL_FILTSEL_Pos (13) /*!< ACMP_T::CTL0: FILTSEL Position */ 472 #define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_T::CTL0: FILTSEL Mask */ 473 474 #define ACMP_CTL_WKEN_Pos (16) /*!< ACMP_T::CTL0: WKEN Position */ 475 #define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) /*!< ACMP_T::CTL0: WKEN Mask */ 476 477 #define ACMP_CTL_WLATEN_Pos (17) /*!< ACMP_T::CTL0: WLATEN Position */ 478 #define ACMP_CTL_WLATEN_Msk (0x1ul << ACMP_CTL_WLATEN_Pos) /*!< ACMP_T::CTL0: WLATEN Mask */ 479 480 #define ACMP_CTL_WCMPSEL_Pos (18) /*!< ACMP_T::CTL0: WCMPSEL Position */ 481 #define ACMP_CTL_WCMPSEL_Msk (0x1ul << ACMP_CTL_WCMPSEL_Pos) /*!< ACMP_T::CTL0: WCMPSEL Mask */ 482 483 #define ACMP_CTL_FCLKDIV_Pos (20) /*!< ACMP_T::CTL0: FCLKDIV Position */ 484 #define ACMP_CTL_FCLKDIV_Msk (0x3ul << ACMP_CTL_FCLKDIV_Pos) /*!< ACMP_T::CTL0: FCLKDIV Mask */ 485 486 #define ACMP_CTL_HYSSEL_Pos (24) /*!< ACMP_T::CTL0: HYSSEL Position */ 487 #define ACMP_CTL_HYSSEL_Msk (0x7ul << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_T::CTL0: HYSSEL Mask */ 488 489 #define ACMP_CTL_MODESEL_Pos (28) /*!< ACMP_T::CTL0: MODESEL Position */ 490 #define ACMP_CTL_MODESEL_Msk (0x3ul << ACMP_CTL_MODESEL_Pos) /*!< ACMP_T::CTL0: MODESEL Mask */ 491 492 #define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP_T::STATUS: ACMPIF0 Position */ 493 #define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP_T::STATUS: ACMPIF0 Mask */ 494 495 #define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP_T::STATUS: ACMPIF1 Position */ 496 #define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP_T::STATUS: ACMPIF1 Mask */ 497 498 #define ACMP_STATUS_ACMPO0_Pos (4) /*!< ACMP_T::STATUS: ACMPO0 Position */ 499 #define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP_T::STATUS: ACMPO0 Mask */ 500 501 #define ACMP_STATUS_ACMPO1_Pos (5) /*!< ACMP_T::STATUS: ACMPO1 Position */ 502 #define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP_T::STATUS: ACMPO1 Mask */ 503 504 #define ACMP_STATUS_WKIF0_Pos (8) /*!< ACMP_T::STATUS: WKIF0 Position */ 505 #define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) /*!< ACMP_T::STATUS: WKIF0 Mask */ 506 507 #define ACMP_STATUS_WKIF1_Pos (9) /*!< ACMP_T::STATUS: WKIF1 Position */ 508 #define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) /*!< ACMP_T::STATUS: WKIF1 Mask */ 509 510 #define ACMP_STATUS_ACMPS0_Pos (12) /*!< ACMP_T::STATUS: ACMPS0 Position */ 511 #define ACMP_STATUS_ACMPS0_Msk (0x1ul << ACMP_STATUS_ACMPS0_Pos) /*!< ACMP_T::STATUS: ACMPS0 Mask */ 512 513 #define ACMP_STATUS_ACMPS1_Pos (13) /*!< ACMP_T::STATUS: ACMPS1 Position */ 514 #define ACMP_STATUS_ACMPS1_Msk (0x1ul << ACMP_STATUS_ACMPS1_Pos) /*!< ACMP_T::STATUS: ACMPS1 Mask */ 515 516 #define ACMP_STATUS_ACMPWO_Pos (16) /*!< ACMP_T::STATUS: ACMPWO Position */ 517 #define ACMP_STATUS_ACMPWO_Msk (0x1ul << ACMP_STATUS_ACMPWO_Pos) /*!< ACMP_T::STATUS: ACMPWO Mask */ 518 519 #define ACMP_VREF_CRV0SEL_Pos (0) /*!< ACMP_T::VREF: CRV0SEL Position */ 520 #define ACMP_VREF_CRV0SEL_Msk (0x3ful << ACMP_VREF_CRV0SEL_Pos) /*!< ACMP_T::VREF: CRV0SEL Mask */ 521 522 #define ACMP_VREF_CRV0SSEL_Pos (6) /*!< ACMP_T::VREF: CRV0SSEL Position */ 523 #define ACMP_VREF_CRV0SSEL_Msk (0x1ul << ACMP_VREF_CRV0SSEL_Pos) /*!< ACMP_T::VREF: CRV0SSEL Mask */ 524 525 #define ACMP_VREF_CRV0EN_Pos (8) /*!< ACMP_T::VREF: CRV0EN Position */ 526 #define ACMP_VREF_CRV0EN_Msk (0x1ul << ACMP_VREF_CRV0EN_Pos) /*!< ACMP_T::VREF: CRV0EN Mask */ 527 528 #define ACMP_VREF_CRV1SEL_Pos (16) /*!< ACMP_T::VREF: CRV1SEL Position */ 529 #define ACMP_VREF_CRV1SEL_Msk (0x3ful << ACMP_VREF_CRV1SEL_Pos) /*!< ACMP_T::VREF: CRV1SEL Mask */ 530 531 #define ACMP_VREF_CRV1SSEL_Pos (22) /*!< ACMP_T::VREF: CRV1SSEL Position */ 532 #define ACMP_VREF_CRV1SSEL_Msk (0x1ul << ACMP_VREF_CRV1SSEL_Pos) /*!< ACMP_T::VREF: CRV1SSEL Mask */ 533 534 #define ACMP_VREF_CRV1EN_Pos (24) /*!< ACMP_T::VREF: CRV1EN Position */ 535 #define ACMP_VREF_CRV1EN_Msk (0x1ul << ACMP_VREF_CRV1EN_Pos) /*!< ACMP_T::VREF: CRV1EN Mask */ 536 537 #define ACMP_VREF_CLAMPEN_Pos (31) /*!< ACMP_T::VREF: CLAMPEN Position */ 538 #define ACMP_VREF_CLAMPEN_Msk (0x1ul << ACMP_VREF_CLAMPEN_Pos) /*!< ACMP_T::VREF: CLAMPEN Mask */ 539 540 #define ACMP_CALCTL_CALTRG0_Pos (0) /*!< ACMP_T::CALCTL: CALTRG0 Position */ 541 #define ACMP_CALCTL_CALTRG0_Msk (0x1ul << ACMP_CALCTL_CALTRG0_Pos) /*!< ACMP_T::CALCTL: CALTRG0 Mask */ 542 543 #define ACMP_CALCTL_CALTRG1_Pos (1) /*!< ACMP_T::CALCTL: CALTRG1 Position */ 544 #define ACMP_CALCTL_CALTRG1_Msk (0x1ul << ACMP_CALCTL_CALTRG1_Pos) /*!< ACMP_T::CALCTL: CALTRG1 Mask */ 545 546 #define ACMP_CALCTL_CALCLK0_Pos (4) /*!< ACMP_T::CALCTL: CALCLK0 Position */ 547 #define ACMP_CALCTL_CALCLK0_Msk (0x3ul << ACMP_CALCTL_CALCLK0_Pos) /*!< ACMP_T::CALCTL: CALCLK0 Mask */ 548 549 #define ACMP_CALCTL_CALCLK1_Pos (6) /*!< ACMP_T::CALCTL: CALCLK1 Position */ 550 #define ACMP_CALCTL_CALCLK1_Msk (0x3ul << ACMP_CALCTL_CALCLK1_Pos) /*!< ACMP_T::CALCTL: CALCLK1 Mask */ 551 552 #define ACMP_CALCTL_OFFSETSEL_Pos (8) /*!< ACMP_T::CALCTL: OFFSETSEL Position */ 553 #define ACMP_CALCTL_OFFSETSEL_Msk (0x1ul << ACMP_CALCTL_OFFSETSEL_Pos) /*!< ACMP_T::CALCTL: OFFSETSEL Mask */ 554 555 #define ACMP_CALCTL_CALRVS_Pos (16) /*!< ACMP_T::CALCTL: CALRVS Position */ 556 #define ACMP_CALCTL_CALRVS_Msk (0x3ul << ACMP_CALCTL_CALRVS_Pos) /*!< ACMP_T::CALCTL: CALRVS Mask */ 557 558 #define ACMP_CALSTS_DONE0_Pos (0) /*!< ACMP_T::CALSTS: DONE0 Position */ 559 #define ACMP_CALSTS_DONE0_Msk (0x1ul << ACMP_CALSTS_DONE0_Pos) /*!< ACMP_T::CALSTS: DONE0 Mask */ 560 561 #define ACMP_CALSTS_DONE1_Pos (4) /*!< ACMP_T::CALSTS: DONE1 Position */ 562 #define ACMP_CALSTS_DONE1_Msk (0x1ul << ACMP_CALSTS_DONE1_Pos) /*!< ACMP_T::CALSTS: DONE1 Mask */ 563 564 #define ACMP_COFF_NCODE0_Pos (0) /*!< ACMP_T::COFF: NCODE0 Position */ 565 #define ACMP_COFF_NCODE0_Msk (0xful << ACMP_COFF_NCODE0_Pos) /*!< ACMP_T::COFF: NCODE0 Mask */ 566 567 #define ACMP_COFF_NSEL0_Pos (7) /*!< ACMP_T::COFF: NSEL0 Position */ 568 #define ACMP_COFF_NSEL0_Msk (0x1ul << ACMP_COFF_NSEL0_Pos) /*!< ACMP_T::COFF: NSEL0 Mask */ 569 570 #define ACMP_COFF_PCODE0_Pos (8) /*!< ACMP_T::COFF: PCODE0 Position */ 571 #define ACMP_COFF_PCODE0_Msk (0xful << ACMP_COFF_PCODE0_Pos) /*!< ACMP_T::COFF: PCODE0 Mask */ 572 573 #define ACMP_COFF_PSEL0_Pos (15) /*!< ACMP_T::COFF: PSEL0 Position */ 574 #define ACMP_COFF_PSEL0_Msk (0x1ul << ACMP_COFF_PSEL0_Pos) /*!< ACMP_T::COFF: PSEL0 Mask */ 575 576 #define ACMP_COFF_NCODE1_Pos (16) /*!< ACMP_T::COFF: NCODE1 Position */ 577 #define ACMP_COFF_NCODE1_Msk (0xful << ACMP_COFF_NCODE1_Pos) /*!< ACMP_T::COFF: NCODE1 Mask */ 578 579 #define ACMP_COFF_NSEL1_Pos (23) /*!< ACMP_T::COFF: NSEL1 Position */ 580 #define ACMP_COFF_NSEL1_Msk (0x1ul << ACMP_COFF_NSEL1_Pos) /*!< ACMP_T::COFF: NSEL1 Mask */ 581 582 #define ACMP_COFF_PCODE1_Pos (24) /*!< ACMP_T::COFF: PCODE1 Position */ 583 #define ACMP_COFF_PCODE1_Msk (0xful << ACMP_COFF_PCODE1_Pos) /*!< ACMP_T::COFF: PCODE1 Mask */ 584 585 #define ACMP_COFF_PSEL1_Pos (31) /*!< ACMP_T::COFF: PSEL1 Position */ 586 #define ACMP_COFF_PSEL1_Msk (0x1ul << ACMP_COFF_PSEL1_Pos) /*!< ACMP_T::COFF: PSEL1 Mask */ 587 588 #define ACMP_TEST_CRV0TEST_Pos (0) /*!< ACMP_T::TEST: CRV0TEST Position */ 589 #define ACMP_TEST_CRV0TEST_Msk (0x1ul << ACMP_TEST_CRV0TEST_Pos) /*!< ACMP_T::TEST: CRV0TEST Mask */ 590 591 #define ACMP_TEST_CRV1TEST_Pos (1) /*!< ACMP_T::TEST: CRV1TEST Position */ 592 #define ACMP_TEST_CRV1TEST_Msk (0x1ul << ACMP_TEST_CRV1TEST_Pos) /*!< ACMP_T::TEST: CRV1TEST Mask */ 593 594 #define ACMP_TEST_OUTSEL_Pos (4) /*!< ACMP_T::TEST: OUTSEL Position */ 595 #define ACMP_TEST_OUTSEL_Msk (0x1ul << ACMP_TEST_OUTSEL_Pos) /*!< ACMP_T::TEST: OUTSEL Mask */ 596 597 #define ACMP_TEST_HYSBYPASS_Pos (8) /*!< ACMP_T::TEST: HYSBYPASS Position */ 598 #define ACMP_TEST_HYSBYPASS_Msk (0x1ul << ACMP_TEST_HYSBYPASS_Pos) /*!< ACMP_T::TEST: HYSBYPASS Mask */ 599 600 #define ACMP_VERSION_MINOR_Pos (0) /*!< ACMP_T::VERSION: MINOR Position */ 601 #define ACMP_VERSION_MINOR_Msk (0xfffful << ACMP_VERSION_MINOR_Pos) /*!< ACMP_T::VERSION: MINOR Mask */ 602 603 #define ACMP_VERSION_SUB_Pos (16) /*!< ACMP_T::VERSION: SUB Position */ 604 #define ACMP_VERSION_SUB_Msk (0xfful << ACMP_VERSION_SUB_Pos) /*!< ACMP_T::VERSION: SUB Mask */ 605 606 #define ACMP_VERSION_MAJOR_Pos (24) /*!< ACMP_T::VERSION: MAJOR Position */ 607 #define ACMP_VERSION_MAJOR_Msk (0xfful << ACMP_VERSION_MAJOR_Pos) /*!< ACMP_T::VERSION: MAJOR Mask */ 608 609 /**@}*/ /* ACMP_CONST */ 610 /**@}*/ /* end of ACMP register group */ 611 /**@}*/ /* end of REGISTER group */ 612 613 #if defined ( __CC_ARM ) 614 #pragma no_anon_unions 615 #endif 616 617 #endif /* __ACMP_REG_H__ */ 618
