1 /**************************************************************************//** 2 * @file pwm.h 3 * @version V3.00 4 * $Revision: 1 $ 5 * $Date: 19/02/14 4:03p $ 6 * @brief M2L31 series PWM driver header file 7 * 8 * @note 9 * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. 10 *****************************************************************************/ 11 #ifndef __PWM_H__ 12 #define __PWM_H__ 13 14 #ifdef __cplusplus 15 extern "C" 16 { 17 #endif 18 19 20 /** @addtogroup Standard_Driver Standard Driver 21 @{ 22 */ 23 24 /** @addtogroup PWM_Driver PWM Driver 25 @{ 26 */ 27 28 /** @addtogroup PWM_EXPORTED_CONSTANTS PWM Exported Constants 29 @{ 30 */ 31 #define PWM_CHANNEL_NUM (6) /*!< PWM channel number */ 32 #define PWM_CH_0_MASK (0x1UL) /*!< PWM channel 0 mask \hideinitializer */ 33 #define PWM_CH_1_MASK (0x2UL) /*!< PWM channel 1 mask \hideinitializer */ 34 #define PWM_CH_2_MASK (0x4UL) /*!< PWM channel 2 mask \hideinitializer */ 35 #define PWM_CH_3_MASK (0x8UL) /*!< PWM channel 3 mask \hideinitializer */ 36 #define PWM_CH_4_MASK (0x10UL) /*!< PWM channel 4 mask \hideinitializer */ 37 #define PWM_CH_5_MASK (0x20UL) /*!< PWM channel 5 mask \hideinitializer */ 38 39 /*---------------------------------------------------------------------------------------------------------*/ 40 /* Counter Type Constant Definitions */ 41 /*---------------------------------------------------------------------------------------------------------*/ 42 #define PWM_UP_COUNTER (0UL) /*!< Up counter type */ 43 #define PWM_DOWN_COUNTER (1UL) /*!< Down counter type */ 44 #define PWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type */ 45 46 /*---------------------------------------------------------------------------------------------------------*/ 47 /* Aligned Type Constant Definitions */ 48 /*---------------------------------------------------------------------------------------------------------*/ 49 #define PWM_EDGE_ALIGNED (1UL) /*!< PWM working in edge aligned type(down count) */ 50 #define PWM_CENTER_ALIGNED (2UL) /*!< PWM working in center aligned type */ 51 52 /*---------------------------------------------------------------------------------------------------------*/ 53 /* Output Level Constant Definitions */ 54 /*---------------------------------------------------------------------------------------------------------*/ 55 #define PWM_OUTPUT_NOTHING (0UL) /*!< PWM output nothing */ 56 #define PWM_OUTPUT_LOW (1UL) /*!< PWM output low */ 57 #define PWM_OUTPUT_HIGH (2UL) /*!< PWM output high */ 58 #define PWM_OUTPUT_TOGGLE (3UL) /*!< PWM output toggle */ 59 60 /*---------------------------------------------------------------------------------------------------------*/ 61 /* Synchronous Start Function Control Constant Definitions */ 62 /*---------------------------------------------------------------------------------------------------------*/ 63 #define PWM_SSCTL_SSRC_EPWM0 (0UL<<PWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from EPWM0 */ 64 #define PWM_SSCTL_SSRC_EPWM1 (1UL<<PWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from EPWM1 */ 65 #define PWM_SSCTL_SSRC_PWM0 (2UL<<PWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from PWM0 */ 66 #define PWM_SSCTL_SSRC_PWM1 (31UL<<PWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from PWM1 */ 67 68 /*---------------------------------------------------------------------------------------------------------*/ 69 /* Trigger Source Select Constant Definitions */ 70 /*---------------------------------------------------------------------------------------------------------*/ 71 #define PWM_TRIGGER_ADC_EVEN_ZERO_POINT (0UL) /*!< PWM trigger ADC while counter of even channel matches zero point */ 72 #define PWM_TRIGGER_ADC_EVEN_PERIOD_POINT (1UL) /*!< PWM trigger ADC while counter of even channel matches period point */ 73 #define PWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT (2UL) /*!< PWM trigger ADC while counter of even channel matches zero or period point */ 74 #define PWM_TRIGGER_ADC_EVEN_COMPARE_UP_COUNT_POINT (3UL) /*!< PWM trigger ADC while counter of even channel matches up count to comparator point */ 75 #define PWM_TRIGGER_ADC_EVEN_COMPARE_DOWN_COUNT_POINT (4UL) /*!< PWM trigger ADC while counter of even channel matches down count to comparator point */ 76 #define PWM_TRIGGER_ADC_ODD_ZERO_POINT (5UL) /*!< PWM trigger ADC while counter of odd channel matches zero point */ 77 #define PWM_TRIGGER_ADC_ODD_PERIOD_POINT (6UL) /*!< PWM trigger ADC while counter of odd channel matches period point */ 78 #define PWM_TRIGGER_ADC_ODD_ZERO_OR_PERIOD_POINT (7UL) /*!< PWM trigger ADC while counter of odd channel matches zero or period point */ 79 #define PWM_TRIGGER_ADC_ODD_COMPARE_UP_COUNT_POINT (8UL) /*!< PWM trigger ADC while counter of odd channel matches up count to comparator point */ 80 #define PWM_TRIGGER_ADC_ODD_COMPARE_DOWN_COUNT_POINT (9UL) /*!< PWM trigger ADC while counter of odd channel matches down count to comparator point */ 81 #define PWM_TRIGGER_ADC_CH_0_FREE_COMPARE_UP_COUNT_POINT (10UL) /*!< PWM trigger ADC while counter of channel 0 matches up count to free comparator point */ 82 #define PWM_TRIGGER_ADC_CH_0_FREE_COMPARE_DOWN_COUNT_POINT (11UL) /*!< PWM trigger ADC while counter of channel 0 matches down count to free comparator point */ 83 #define PWM_TRIGGER_ADC_CH_2_FREE_COMPARE_UP_COUNT_POINT (12UL) /*!< PWM trigger ADC while counter of channel 2 matches up count to free comparator point */ 84 #define PWM_TRIGGER_ADC_CH_2_FREE_COMPARE_DOWN_COUNT_POINT (13UL) /*!< PWM trigger ADC while counter of channel 2 matches down count to free comparator point */ 85 #define PWM_TRIGGER_ADC_CH_4_FREE_COMPARE_UP_COUNT_POINT (14UL) /*!< PWM trigger ADC while counter of channel 4 matches up count to free comparator point */ 86 #define PWM_TRIGGER_ADC_CH_4_FREE_COMPARE_DOWN_COUNT_POINT (15UL) /*!< PWM trigger ADC while counter of channel 4 matches down count to free comparator point */ 87 88 /*---------------------------------------------------------------------------------------------------------*/ 89 /* Fail brake Control Constant Definitions */ 90 /*---------------------------------------------------------------------------------------------------------*/ 91 #define PWM_FB_EDGE_ACMP0 (PWM_BRKCTL0_1_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source */ 92 #define PWM_FB_EDGE_ACMP1 (PWM_BRKCTL0_1_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source */ 93 #define PWM_FB_EDGE_BKP0 (PWM_BRKCTL0_1_BRKP0EEN_Msk) /*!< BKP0 pin as edge-detect fault brake source */ 94 #define PWM_FB_EDGE_BKP1 (PWM_BRKCTL0_1_BRKP1EEN_Msk) /*!< BKP1 pin as edge-detect fault brake source */ 95 #define PWM_FB_EDGE_ADCRM (PWM_BRKCTL0_1_ADCEBEN_Msk) /*!< ADC Result Monitor (ADCRM) as edge-detect fault brake source */ 96 #define PWM_FB_EDGE_SYS_CSS (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as edge-detect fault brake source */ 97 #define PWM_FB_EDGE_SYS_BOD (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as edge-detect fault brake source */ 98 #define PWM_FB_EDGE_SYS_COR (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as edge-detect fault brake source */ 99 100 #define PWM_FB_LEVEL_ACMP0 (PWM_BRKCTL0_1_CPO0LBEN_Msk) /*!< Comparator 0 as level-detect fault brake source */ 101 #define PWM_FB_LEVEL_ACMP1 (PWM_BRKCTL0_1_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source */ 102 #define PWM_FB_LEVEL_BKP0 (PWM_BRKCTL0_1_BRKP0LEN_Msk) /*!< BKP0 pin as level-detect fault brake source */ 103 #define PWM_FB_LEVEL_BKP1 (PWM_BRKCTL0_1_BRKP1LEN_Msk) /*!< BKP1 pin as level-detect fault brake source */ 104 #define PWM_FB_LEVEL_ADCRM (PWM_BRKCTL0_1_ADCLBEN_Msk) /*!< ADC Result Monitor (ADCRM) as level-detect fault brake source */ 105 #define PWM_FB_LEVEL_SYS_CSS (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as level-detect fault brake source */ 106 #define PWM_FB_LEVEL_SYS_BOD (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as level-detect fault brake source */ 107 #define PWM_FB_LEVEL_SYS_COR (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as level-detect fault brake source */ 108 109 #define PWM_FB_EDGE (0UL) /*!< edge-detect fault brake */ 110 #define PWM_FB_LEVEL (8UL) /*!< level-detect fault brake */ 111 112 /*---------------------------------------------------------------------------------------------------------*/ 113 /* Leading Edge Blanking Control Constant Definitions */ 114 /*---------------------------------------------------------------------------------------------------------*/ 115 #define PWM_LEBCTL_TRGTYPE_RISING (0UL<<PWM_LEBCTL_TRGTYPE_Pos) /*!< PWM Leading Edge Blanking Trigger Type Is Rising Edge \hideinitializer */ 116 #define PWM_LEBCTL_TRGTYPE_FALLING (1UL<<PWM_LEBCTL_TRGTYPE_Pos) /*!< PWM Leading Edge Blanking Trigger Type Is Falling Edge \hideinitializer */ 117 #define PWM_LEBCTL_TRGTYPE_RISING_OR_FALLING (2UL<<PWM_LEBCTL_TRGTYPE_Pos) /*!< PWM Leading Edge Blanking Trigger Type Is Rising or Falling Edge \hideinitializer */ 118 #define PWM_LEBCTL_SRCEN0 (PWM_LEBCTL_SRCEN0_Msk) /*!< PWM Leading Edge Blanking Source From PWMx_CH0 Enable \hideinitializer */ 119 #define PWM_LEBCTL_SRCEN2 (PWM_LEBCTL_SRCEN2_Msk) /*!< PWM Leading Edge Blanking Source From PWMx_CH2 Enable \hideinitializer */ 120 #define PWM_LEBCTL_SRCEN4 (PWM_LEBCTL_SRCEN4_Msk) /*!< PWM Leading Edge Blanking Source From PWMx_CH4 Enable \hideinitializer */ 121 #define PWM_LEBCTL_SRCEN0_2 (PWM_LEBCTL_SRCEN0_Msk|PWM_LEBCTL_SRCEN2_Msk) /*!< PWM Leading Edge Blanking Source From PWMx_CH0 and PWMx_CH2 Enable \hideinitializer */ 122 #define PWM_LEBCTL_SRCEN0_4 (PWM_LEBCTL_SRCEN0_Msk|PWM_LEBCTL_SRCEN4_Msk) /*!< PWM Leading Edge Blanking Source From PWMx_CH0 and PWMx_CH4 Enable \hideinitializer */ 123 #define PWM_LEBCTL_SRCEN2_4 (PWM_LEBCTL_SRCEN2_Msk|PWM_LEBCTL_SRCEN4_Msk) /*!< PWM Leading Edge Blanking Source From PWMx_CH2 and PWMx_CH4 Enable \hideinitializer */ 124 #define PWM_LEBCTL_SRCEN0_2_4 (PWM_LEBCTL_SRCEN0_Msk|PWM_LEBCTL_SRCEN2_Msk|PWM_LEBCTL_SRCEN4_Msk) /*!< PWM Leading Edge Blanking Source From PWMx_CH0, PWMx_CH2 and PWMx_CH4 Enable \hideinitializer */ 125 126 /*---------------------------------------------------------------------------------------------------------*/ 127 /* Capture Control Constant Definitions */ 128 /*---------------------------------------------------------------------------------------------------------*/ 129 #define PWM_CAPTURE_INT_RISING_LATCH (1UL) /*!< PWM capture interrupt if channel has rising transition */ 130 #define PWM_CAPTURE_INT_FALLING_LATCH (0x100UL) /*!< PWM capture interrupt if channel has falling transition */ 131 132 #define PWM_CAPTURE_PDMA_RISING_LATCH (0x2UL) /*!< PWM capture rising latched data transfer by PDMA */ 133 #define PWM_CAPTURE_PDMA_FALLING_LATCH (0x4UL) /*!< PWM capture falling latched data transfer by PDMA */ 134 #define PWM_CAPTURE_PDMA_RISING_FALLING_LATCH (0x6UL) /*!< PWM capture rising and falling latched data transfer by PDMA */ 135 136 /*---------------------------------------------------------------------------------------------------------*/ 137 /* Duty Interrupt Type Constant Definitions */ 138 /*---------------------------------------------------------------------------------------------------------*/ 139 #define PWM_DUTY_INT_DOWN_COUNT_MATCH_CMP (PWM_INTEN0_CMPDIEN0_Msk) /*!< PWM duty interrupt triggered if down count match comparator */ 140 #define PWM_DUTY_INT_UP_COUNT_MATCH_CMP (PWM_INTEN0_CMPUIEN0_Msk) /*!< PWM duty interrupt triggered if up down match comparator */ 141 142 /*---------------------------------------------------------------------------------------------------------*/ 143 /* Interrupt Flag Accumulator Constant Definitions */ 144 /*---------------------------------------------------------------------------------------------------------*/ 145 #define PWM_IFA_ZERO_POINT (0UL) /*!< PWM counter equal to zero \hideinitializer */ 146 #define PWM_IFA_PERIOD_POINT (1UL) /*!< PWM counter equal to period \hideinitializer */ 147 #define PWM_IFA_COMPARE_UP_COUNT_POINT (2UL) /*!< PWM counter up count to comparator value \hideinitializer */ 148 #define PWM_IFA_COMPARE_DOWN_COUNT_POINT (3UL) /*!< PWM counter down count to comparator value \hideinitializer */ 149 150 /*---------------------------------------------------------------------------------------------------------*/ 151 /* Load Mode Constant Definitions */ 152 /*---------------------------------------------------------------------------------------------------------*/ 153 #define PWM_LOAD_MODE_IMMEDIATE (PWM_CTL0_IMMLDEN0_Msk) /*!< PWM immediately load mode \hideinitializer */ 154 #define PWM_LOAD_MODE_WINDOW (PWM_CTL0_WINLDEN0_Msk) /*!< PWM window load mode \hideinitializer */ 155 #define PWM_LOAD_MODE_CENTER (PWM_CTL0_CTRLD0_Msk) /*!< PWM center load mode \hideinitializer */ 156 157 /*---------------------------------------------------------------------------------------------------------*/ 158 /* Synchronize Control Constant Definitions */ 159 /*---------------------------------------------------------------------------------------------------------*/ 160 #define PWM_SYNC_OUT_FROM_SYNCIN_SWSYNC (0UL) /*!< Synchronize source from SYNC_IN or SWSYNC \hideinitializer */ 161 #define PWM_SYNC_OUT_FROM_COUNT_TO_ZERO (1UL) /*!< Synchronize source from counter equal to 0 \hideinitializer */ 162 #define PWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR (2UL) /*!< Synchronize source from counter equal to CMPDAT1, CMPDAT3, CMPDAT5 \hideinitializer */ 163 #define PWM_SYNC_OUT_DISABLE (3UL) /*!< SYNC_OUT will not be generated \hideinitializer */ 164 #define PWM_PHS_DIR_DECREMENT (0UL) /*!< PWM counter count decrement \hideinitializer */ 165 #define PWM_PHS_DIR_INCREMENT (1UL) /*!< PWM counter count increment \hideinitializer */ 166 167 /*---------------------------------------------------------------------------------------------------------*/ 168 /* Noise Filter Clock Divide Select Constant Definitions */ 169 /*---------------------------------------------------------------------------------------------------------*/ 170 #define PWM_NF_CLK_DIV_1 (0UL) /*!< Noise filter clock is HCLK divide by 1 \hideinitializer */ 171 #define PWM_NF_CLK_DIV_2 (1UL) /*!< Noise filter clock is HCLK divide by 2 \hideinitializer */ 172 #define PWM_NF_CLK_DIV_4 (2UL) /*!< Noise filter clock is HCLK divide by 4 \hideinitializer */ 173 #define PWM_NF_CLK_DIV_8 (3UL) /*!< Noise filter clock is HCLK divide by 8 \hideinitializer */ 174 #define PWM_NF_CLK_DIV_16 (4UL) /*!< Noise filter clock is HCLK divide by 16 \hideinitializer */ 175 #define PWM_NF_CLK_DIV_32 (5UL) /*!< Noise filter clock is HCLK divide by 32 \hideinitializer */ 176 #define PWM_NF_CLK_DIV_64 (6UL) /*!< Noise filter clock is HCLK divide by 64 \hideinitializer */ 177 #define PWM_NF_CLK_DIV_128 (7UL) /*!< Noise filter clock is HCLK divide by 128 \hideinitializer */ 178 179 /*---------------------------------------------------------------------------------------------------------*/ 180 /* Clock Source Select Constant Definitions */ 181 /*---------------------------------------------------------------------------------------------------------*/ 182 #define PWM_CLKSRC_PWM_CLK (0UL) /*!< PWM Clock source selects to PWM0_CLK or PWM1_CLK \hideinitializer */ 183 #define PWM_CLKSRC_TIMER0 (1UL) /*!< PWM Clock source selects to TIMER0 overflow \hideinitializer */ 184 #define PWM_CLKSRC_TIMER1 (2UL) /*!< PWM Clock source selects to TIMER1 overflow \hideinitializer */ 185 #define PWM_CLKSRC_TIMER2 (3UL) /*!< PWM Clock source selects to TIMER2 overflow \hideinitializer */ 186 #define PWM_CLKSRC_TIMER3 (4UL) /*!< PWM Clock source selects to TIMER3 overflow \hideinitializer */ 187 //#define PWM_CLKSRC_TIMER3 (4UL) /*!< PWM Clock source selects to TIMER3 overflow \hideinitializer */ 188 189 190 /*@}*/ /* end of group PWM_EXPORTED_CONSTANTS */ 191 192 193 /** @addtogroup PWM_EXPORTED_FUNCTIONS PWM Exported Functions 194 @{ 195 */ 196 197 /** 198 * @brief This macro enable complementary mode 199 * @param[in] pwm The pointer of the specified PWM module 200 * @return None 201 * @details This macro is used to enable complementary mode of PWM module. 202 * \hideinitializer 203 */ 204 #define PWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL1 = (pwm)->CTL1 | (0x7ul<<PWM_CTL1_OUTMODE0_Pos)) 205 206 /** 207 * @brief This macro disable complementary mode, and enable independent mode. 208 * @param[in] pwm The pointer of the specified PWM module 209 * @return None 210 * @details This macro is used to disable complementary mode of PWM module. 211 * \hideinitializer 212 */ 213 #define PWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL1 = (pwm)->CTL1 & ~(0x7ul<<PWM_CTL1_OUTMODE0_Pos)) 214 215 /** 216 * @brief This macro enable group mode 217 * @param[in] pwm The pointer of the specified PWM module 218 * @return None 219 * @details This macro is used to enable group mode of PWM module. 220 * \hideinitializer 221 */ 222 #define PWM_ENABLE_GROUP_MODE(pwm) ((pwm)->CTL0 = (pwm)->CTL0 | PWM_CTL0_GROUPEN_Msk) 223 224 /** 225 * @brief This macro disable group mode 226 * @param[in] pwm The pointer of the specified PWM module 227 * @return None 228 * @details This macro is used to disable group mode of PWM module. 229 * \hideinitializer 230 */ 231 #define PWM_DISABLE_GROUP_MODE(pwm) ((pwm)->CTL0 = (pwm)->CTL0 & ~PWM_CTL0_GROUPEN_Msk) 232 233 /** 234 * @brief Enable timer synchronous start counting function of specified channel(s) 235 * @param[in] pwm The pointer of the specified PWM module 236 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 237 * Bit 0 represents channel 0, bit 1 represents channel 1... 238 * @param[in] u32SyncSrc Synchronous start source selection, valid values are: 239 * - \ref PWM_SSCTL_SSRC_PWM0 240 * - \ref PWM_SSCTL_SSRC_PWM1 241 * @return None 242 * @details This macro is used to enable timer synchronous start counting function of specified channel(s). 243 * \hideinitializer 244 */ 245 #define PWM_ENABLE_TIMER_SYNC(pwm, u32ChannelMask, u32SyncSrc) ((pwm)->SSCTL = ((pwm)->SSCTL & ~PWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | (u32ChannelMask)) 246 247 /** 248 * @brief Disable timer synchronous start counting function of specified channel(s) 249 * @param[in] pwm The pointer of the specified PWM module 250 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 251 * Bit 0 represents channel 0, bit 1 represents channel 1... 252 * @return None 253 * @details This macro is used to disable timer synchronous start counting function of specified channel(s). 254 * \hideinitializer 255 */ 256 #define PWM_DISABLE_TIMER_SYNC(pwm, u32ChannelMask) \ 257 do{ \ 258 int i;\ 259 for(i = 0; i < 6; i++) { \ 260 if((u32ChannelMask) & (1 << i)) \ 261 (pwm)->SSCTL &= ~(1UL << i); \ 262 } \ 263 }while(0) 264 265 /** 266 * @brief This macro enable PWM counter synchronous start counting function. 267 * @param[in] pwm The pointer of the specified PWM module 268 * @return None 269 * @details This macro is used to make selected PWM0 and PWM1 channel(s) start counting at the same time. 270 * To configure synchronous start counting channel(s) by PWM_ENABLE_TIMER_SYNC() and PWM_DISABLE_TIMER_SYNC(). 271 * \hideinitializer 272 */ 273 #define PWM_TRIGGER_SYNC_START(pwm) ((pwm)->SSTRG = PWM_SSTRG_CNTSEN_Msk) 274 275 /** 276 * @brief This macro enable output inverter of specified channel(s) 277 * @param[in] pwm The pointer of the specified PWM module 278 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 279 * Bit 0 represents channel 0, bit 1 represents channel 1... 280 * @return None 281 * @details This macro is used to enable output inverter of specified channel(s). 282 * \hideinitializer 283 */ 284 #define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) ((pwm)->POLCTL = (u32ChannelMask)) 285 286 /** 287 * @brief This macro get captured rising data 288 * @param[in] pwm The pointer of the specified PWM module 289 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 290 * @return None 291 * @details This macro is used to get captured rising data of specified channel. 292 * \hideinitializer 293 */ 294 #define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&((pwm)->RCAPDAT0) + ((u32ChannelNum) << 1))) 295 296 /** 297 * @brief This macro get captured falling data 298 * @param[in] pwm The pointer of the specified PWM module 299 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 300 * @return None 301 * @details This macro is used to get captured falling data of specified channel. 302 * \hideinitializer 303 */ 304 #define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&((pwm)->FCAPDAT0) + ((u32ChannelNum) << 1))) 305 306 /** 307 * @brief This macro mask output logic to high or low 308 * @param[in] pwm The pointer of the specified PWM module 309 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 310 * Bit 0 represents channel 0, bit 1 represents channel 1... 311 * @param[in] u32LevelMask Output logic to high or low 312 * @return None 313 * @details This macro is used to mask output logic to high or low of specified channel(s). 314 * @note If u32ChannelMask parameter is 0, then mask function will be disabled. 315 * \hideinitializer 316 */ 317 #define PWM_MASK_OUTPUT(pwm, u32ChannelMask, u32LevelMask) \ 318 { \ 319 (pwm)->MSKEN = (u32ChannelMask); \ 320 (pwm)->MSK = (u32LevelMask); \ 321 } 322 323 /** 324 * @brief This macro set the prescaler of the selected channel 325 * @param[in] pwm The pointer of the specified PWM module 326 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 327 * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF 328 * @return None 329 * @details This macro is used to set the prescaler of specified channel. 330 * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected. 331 * The clock of PWM counter is divided by (u32Prescaler + 1). 332 * \hideinitializer 333 */ 334 #define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) (*(__IO uint32_t *) (&((pwm)->CLKPSC0_1) + ((u32ChannelNum) >> 1)) = (u32Prescaler)) 335 336 /** 337 * @brief This macro get the prescaler of the selected channel 338 * @param[in] pwm The pointer of the specified PWM module 339 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 340 * @return Return Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF 341 * @details This macro is used to get the prescaler of specified channel. 342 * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected. 343 * The clock of PWM counter is divided by (u32Prescaler + 1). 344 * \hideinitializer 345 */ 346 #define PWM_GET_PRESCALER(pwm, u32ChannelNum) (*(__IO uint32_t *) (&((pwm)->CLKPSC0_1) + ((u32ChannelNum) >> 1))) 347 348 /** 349 * @brief This macro set the comparator of the selected channel 350 * @param[in] pwm The pointer of the specified PWM module 351 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 352 * @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF 353 * @return None 354 * @details This macro is used to set the comparator of specified channel. 355 * @note This new setting will take effect on next PWM period. 356 * \hideinitializer 357 */ 358 #define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) ((pwm)->CMPDAT[(u32ChannelNum)]= (u32CMR)) 359 360 /** 361 * @brief This macro get the comparator of the selected channel 362 * @param[in] pwm The pointer of the specified PWM module 363 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 364 * @return Return the comparator of specified channel. Valid values are between 0~0xFFFF 365 * @details This macro is used to get the comparator of specified channel. 366 * \hideinitializer 367 */ 368 #define PWM_GET_CMR(pwm, u32ChannelNum) ((pwm)->CMPDAT[(u32ChannelNum)]) 369 370 /** 371 * @brief This macro set the free trigger comparator of the selected channel 372 * @param[in] pwm The pointer of the specified PWM module 373 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 374 * @param[in] u32FTCMR Free trigger comparator of specified channel. Valid values are between 0~0xFFFF 375 * @return None 376 * @details This macro is used to set the free trigger comparator of specified channel. 377 * @note This new setting will take effect on next PWM period. 378 * \hideinitializer 379 */ 380 #define PWM_SET_FTCMR(pwm, u32ChannelNum, u32FTCMR) (*(__IO uint32_t *) (&((pwm)->FTCMPDAT0_1) + ((u32ChannelNum) >> 1)) = (u32FTCMR)) 381 382 /** 383 * @brief This macro set the period of the selected channel 384 * @param[in] pwm The pointer of the specified PWM module 385 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 386 * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF 387 * @return None 388 * @details This macro is used to set the period of specified channel. 389 * @note This new setting will take effect on next PWM period. 390 * @note PWM counter will stop if period length set to 0. 391 * \hideinitializer 392 */ 393 #define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) ((pwm)->PERIOD[((u32ChannelNum>>1)<<1)] = (u32CNR)) 394 395 /** 396 * @brief This macro get the period of the selected channel 397 * @param[in] pwm The pointer of the specified PWM module 398 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 399 * @return Return the period of specified channel. Valid values are between 0~0xFFFF 400 * @details This macro is used to get the period of specified channel. 401 * \hideinitializer 402 */ 403 #define PWM_GET_CNR(pwm, u32ChannelNum) ((pwm)->PERIOD[((u32ChannelNum>>1)<<1)]) 404 405 /** 406 * @brief This macro set the PWM aligned type 407 * @param[in] pwm The pointer of the specified PWM module 408 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 409 * Bit 0 represents channel 0, bit 1 represents channel 1... 410 * @param[in] u32AlignedType PWM aligned type, valid values are: 411 * - \ref PWM_EDGE_ALIGNED 412 * - \ref PWM_CENTER_ALIGNED 413 * @return None 414 * @details This macro is used to set the PWM aligned type of specified channel(s). 415 * \hideinitializer 416 */ 417 #define PWM_SET_ALIGNED_TYPE(pwm, u32ChannelMask, u32AlignedType) \ 418 do{ \ 419 int i; \ 420 for(i = 0; i < 6; i++) { \ 421 if((u32ChannelMask) & (1 << i)) \ 422 (pwm)->CTL1 = (((pwm)->CTL1 & ~(3UL << (i << 1))) | ((u32AlignedType) << (i << 1))); \ 423 } \ 424 }while(0) 425 426 /** 427 * @brief Set load window of window loading mode for specified channel(s) 428 * @param[in] pwm The pointer of the specified PWM module 429 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 430 * Bit 0 represents channel 0, bit 1 represents channel 1... 431 * @return None 432 * @details This macro is used to set load window of window loading mode for specified channel(s). 433 * \hideinitializer 434 */ 435 #define PWM_SET_LOAD_WINDOW(pwm, u32ChannelMask) ((pwm)->LOAD |= (u32ChannelMask)) 436 437 /** 438 * @brief Trigger synchronous event from specified channel(s) 439 * @param[in] pwm The pointer of the specified PWM module 440 * @param[in] u32ChannelNum PWM channel number. Valid values are 0, 2, 4 441 * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 442 * @return None 443 * @details This macro is used to trigger synchronous event from specified channel(s). 444 * \hideinitializer 445 */ 446 #define PWM_TRIGGER_SYNC(pwm, u32ChannelNum) ((pwm)->SWSYNC |= (1 << ((u32ChannelNum) >> 1))) 447 448 /** 449 * @brief Clear counter of specified channel(s) 450 * @param[in] pwm The pointer of the specified PWM module 451 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 452 * Bit 0 represents channel 0, bit 1 represents channel 1... 453 * @return None 454 * @details This macro is used to clear counter of specified channel(s). 455 * \hideinitializer 456 */ 457 #define PWM_CLR_COUNTER(pwm, u32ChannelMask) ((pwm)->CNTCLR |= (u32ChannelMask)) 458 459 /** 460 * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s) 461 * @param[in] pwm The pointer of the specified PWM module 462 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 463 * Bit 0 represents channel 0, bit 1 represents channel 1... 464 * @param[in] u32ZeroLevel output level at zero point, valid values are: 465 * - \ref PWM_OUTPUT_NOTHING 466 * - \ref PWM_OUTPUT_LOW 467 * - \ref PWM_OUTPUT_HIGH 468 * - \ref PWM_OUTPUT_TOGGLE 469 * @param[in] u32CmpUpLevel output level at compare up point, valid values are: 470 * - \ref PWM_OUTPUT_NOTHING 471 * - \ref PWM_OUTPUT_LOW 472 * - \ref PWM_OUTPUT_HIGH 473 * - \ref PWM_OUTPUT_TOGGLE 474 * @param[in] u32PeriodLevel output level at period(center) point, valid values are: 475 * - \ref PWM_OUTPUT_NOTHING 476 * - \ref PWM_OUTPUT_LOW 477 * - \ref PWM_OUTPUT_HIGH 478 * - \ref PWM_OUTPUT_TOGGLE 479 * @param[in] u32CmpDownLevel output level at compare down point, valid values are: 480 * - \ref PWM_OUTPUT_NOTHING 481 * - \ref PWM_OUTPUT_LOW 482 * - \ref PWM_OUTPUT_HIGH 483 * - \ref PWM_OUTPUT_TOGGLE 484 * @return None 485 * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s). 486 * \hideinitializer 487 */ 488 #define PWM_SET_OUTPUT_LEVEL(pwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \ 489 do{ \ 490 int i; \ 491 for(i = 0; i < 6; i++) { \ 492 if((u32ChannelMask) & (1 << i)) { \ 493 (pwm)->WGCTL0 = (((pwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1))); \ 494 (pwm)->WGCTL0 = (((pwm)->WGCTL0 & ~(3UL << (PWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))) | ((u32PeriodLevel) << (PWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))); \ 495 (pwm)->WGCTL1 = (((pwm)->WGCTL1 & ~(3UL << (i << 1))) | ((u32CmpUpLevel) << (i << 1))); \ 496 (pwm)->WGCTL1 = (((pwm)->WGCTL1 & ~(3UL << (PWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))) | ((u32CmpDownLevel) << (PWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))); \ 497 } \ 498 } \ 499 }while(0) 500 501 /** 502 * @brief Trigger brake event from specified channel(s) 503 * @param[in] pwm The pointer of the specified PWM module 504 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 505 * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 506 * @param[in] u32BrakeType Type of brake trigger. PWM_FB_EDGE of this macro is only supported in M45xD/M45xC. 507 * - \ref PWM_FB_EDGE 508 * - \ref PWM_FB_LEVEL 509 * @return None 510 * @details This macro is used to trigger brake event from specified channel(s). 511 * \hideinitializer 512 */ 513 #define PWM_TRIGGER_BRAKE(pwm, u32ChannelMask, u32BrakeType) ((pwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType))) 514 515 /** 516 * @brief Set Dead zone clock source 517 * @param[in] pwm The pointer of the specified PWM module 518 * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 519 * @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler). 520 * @return None 521 * @details This macro is used to set Dead zone clock source. Every two channels share the same setting. 522 * @note The write-protection function should be disabled before using this function. 523 * @note This function is only supported in M45xD/M45xC. 524 * \hideinitializer 525 */ 526 #define PWM_SET_DEADZONE_CLK_SRC(pwm, u32ChannelNum, u32AfterPrescaler) \ 527 (*(__IO uint32_t *) (&((pwm)->DTCTL0_1) + ((u32ChannelNum) >> 1)) = (*(__IO uint32_t *) (&((pwm)->DTCTL0_1) + ((u32ChannelNum) >> 1)) & ~PWM_DTCTL0_1_DTCKSEL_Msk) | \ 528 ((u32AfterPrescaler) << PWM_DTCTL0_1_DTCKSEL_Pos)) 529 530 /*---------------------------------------------------------------------------------------------------------*/ 531 /* Define PWM functions prototype */ 532 /*---------------------------------------------------------------------------------------------------------*/ 533 uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge); 534 uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle); 535 void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask); 536 void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask); 537 void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask); 538 void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition); 539 void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum); 540 void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition); 541 uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum); 542 void PWM_EnableFaultBrake(PWM_T *pwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource); 543 void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask); 544 void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask); 545 void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask); 546 void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask); 547 void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode); 548 void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum); 549 void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration); 550 void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum); 551 void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge); 552 void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge); 553 void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge); 554 uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); 555 void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType); 556 void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum); 557 void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); 558 uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); 559 void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource); 560 void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource); 561 void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource); 562 uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource); 563 void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType); 564 void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum); 565 void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); 566 uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); 567 void PWM_EnableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum); 568 void PWM_DisableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum); 569 void PWM_ClearZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); 570 uint32_t PWM_GetZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); 571 void PWM_EnableAcc(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc); 572 void PWM_DisableAcc(PWM_T *pwm, uint32_t u32ChannelNum); 573 void PWM_EnableAccInt(PWM_T *pwm, uint32_t u32ChannelNum); 574 void PWM_DisableAccInt(PWM_T *pwm, uint32_t u32ChannelNum); 575 void PWM_ClearAccInt(PWM_T *pwm, uint32_t u32ChannelNum); 576 uint32_t PWM_GetAccInt(PWM_T *pwm, uint32_t u32ChannelNum); 577 void PWM_EnableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); 578 void PWM_DisableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); 579 void PWM_SetClockSource(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel); 580 void PWM_EnableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel); 581 void PWM_DisableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum); 582 void PWM_EnableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum); 583 void PWM_DisableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum); 584 void PWM_SetBrakePinSource(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule); 585 uint32_t PWM_GetWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum); 586 void PWM_ClearWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum); 587 void PWM_EnableAcc(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc); 588 void PWM_DisableAcc(PWM_T *pwm, uint32_t u32ChannelNum); 589 void PWM_EnableAccInt(PWM_T *pwm, uint32_t u32ChannelNum); 590 void PWM_DisableAccInt(PWM_T *pwm, uint32_t u32ChannelNum); 591 void PWM_ClearAccInt(PWM_T *pwm, uint32_t u32ChannelNum); 592 uint32_t PWM_GetAccInt(PWM_T *pwm, uint32_t u32ChannelNum); 593 void PWM_EnableAccPDMA(PWM_T *pwm, uint32_t u32ChannelNum); 594 void PWM_DisableAccPDMA(PWM_T *pwm, uint32_t u32ChannelNum); 595 void PWM_EnableAccStopMode(PWM_T *pwm, uint32_t u32ChannelNum); 596 void PWM_DisableAccStopMode(PWM_T *pwm, uint32_t u32ChannelNum); 597 598 /*@}*/ /* end of group PWM_EXPORTED_FUNCTIONS */ 599 600 /*@}*/ /* end of group PWM_Driver */ 601 602 /*@}*/ /* end of group Standard_Driver */ 603 604 #ifdef __cplusplus 605 } 606 #endif 607 608 #endif //__PWM_H__ 609 610 /*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ 611
