1 /**************************************************************************//** 2 * @file pdma.h 3 * @version V1.00 4 * @brief M2L31 series PDMA driver header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2023 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __PDMA_H__ 10 #define __PDMA_H__ 11 12 #ifdef __cplusplus 13 extern "C" 14 { 15 #endif 16 17 18 /** @addtogroup Standard_Driver Standard Driver 19 @{ 20 */ 21 22 /** @addtogroup PDMA_Driver PDMA Driver 23 @{ 24 */ 25 26 /** @addtogroup PDMA_EXPORTED_CONSTANTS PDMA Exported Constants 27 @{ 28 */ 29 #define PDMA_CH_MAX 16UL /*!< Specify Maximum Channels of PDMA \hideinitializer */ 30 31 /*---------------------------------------------------------------------------------------------------------*/ 32 /* Operation Mode Constant Definitions */ 33 /*---------------------------------------------------------------------------------------------------------*/ 34 #define PDMA_OP_STOP 0x00000000UL /*!<DMA Stop Mode \hideinitializer */ 35 #define PDMA_OP_BASIC 0x00000001UL /*!<DMA Basic Mode \hideinitializer */ 36 #define PDMA_OP_SCATTER 0x00000002UL /*!<DMA Scatter-gather Mode \hideinitializer */ 37 38 /*---------------------------------------------------------------------------------------------------------*/ 39 /* Data Width Constant Definitions */ 40 /*---------------------------------------------------------------------------------------------------------*/ 41 #define PDMA_WIDTH_8 0x00000000UL /*!<DMA Transfer Width 8-bit \hideinitializer */ 42 #define PDMA_WIDTH_16 0x00001000UL /*!<DMA Transfer Width 16-bit \hideinitializer */ 43 #define PDMA_WIDTH_32 0x00002000UL /*!<DMA Transfer Width 32-bit \hideinitializer */ 44 45 /*---------------------------------------------------------------------------------------------------------*/ 46 /* Address Attribute Constant Definitions */ 47 /*---------------------------------------------------------------------------------------------------------*/ 48 #define PDMA_SAR_INC 0x00000000UL /*!<DMA SAR increment \hideinitializer */ 49 #define PDMA_SAR_FIX 0x00000300UL /*!<DMA SAR fix address \hideinitializer */ 50 #define PDMA_DAR_INC 0x00000000UL /*!<DMA DAR increment \hideinitializer */ 51 #define PDMA_DAR_FIX 0x00000C00UL /*!<DMA DAR fix address \hideinitializer */ 52 53 /*---------------------------------------------------------------------------------------------------------*/ 54 /* Burst Mode Constant Definitions */ 55 /*---------------------------------------------------------------------------------------------------------*/ 56 #define PDMA_REQ_SINGLE 0x00000004UL /*!<DMA Single Request \hideinitializer */ 57 #define PDMA_REQ_BURST 0x00000000UL /*!<DMA Burst Request \hideinitializer */ 58 59 #define PDMA_BURST_128 0x00000000UL /*!<DMA Burst 128 Transfers \hideinitializer */ 60 #define PDMA_BURST_64 0x00000010UL /*!<DMA Burst 64 Transfers \hideinitializer */ 61 #define PDMA_BURST_32 0x00000020UL /*!<DMA Burst 32 Transfers \hideinitializer */ 62 #define PDMA_BURST_16 0x00000030UL /*!<DMA Burst 16 Transfers \hideinitializer */ 63 #define PDMA_BURST_8 0x00000040UL /*!<DMA Burst 8 Transfers \hideinitializer */ 64 #define PDMA_BURST_4 0x00000050UL /*!<DMA Burst 4 Transfers \hideinitializer */ 65 #define PDMA_BURST_2 0x00000060UL /*!<DMA Burst 2 Transfers \hideinitializer */ 66 #define PDMA_BURST_1 0x00000070UL /*!<DMA Burst 1 Transfers \hideinitializer */ 67 68 /*---------------------------------------------------------------------------------------------------------*/ 69 /* Table Interrupt Disable Constant Definitions */ 70 /*---------------------------------------------------------------------------------------------------------*/ 71 #define PDMA_TBINTDIS_ENABLE (0x0UL<<PDMA_DSCT_CTL_TBINTDIS_Pos) /*!<DMA Table Interrupt Enabled \hideinitializer */ 72 #define PDMA_TBINTDIS_DISABLE (0x1UL<<PDMA_DSCT_CTL_TBINTDIS_Pos) /*!<DMA Table Interrupt Disabled \hideinitializer */ 73 74 /*---------------------------------------------------------------------------------------------------------*/ 75 /* Peripheral Transfer Mode Constant Definitions */ 76 /*---------------------------------------------------------------------------------------------------------*/ 77 #define PDMA_MEM 0UL /*!<DMA Connect to Memory \hideinitializer */ 78 #define PDMA_USB_TX 2UL /*!<DMA Connect to USB_TX \hideinitializer */ 79 #define PDMA_USB_RX 3UL /*!<DMA Connect to USB_RX \hideinitializer */ 80 #define PDMA_UART0_TX 4UL /*!<DMA Connect to UART0_TX \hideinitializer */ 81 #define PDMA_UART0_RX 5UL /*!<DMA Connect to UART0_RX \hideinitializer */ 82 #define PDMA_UART1_TX 6UL /*!<DMA Connect to UART1_TX \hideinitializer */ 83 #define PDMA_UART1_RX 7UL /*!<DMA Connect to UART1_RX \hideinitializer */ 84 #define PDMA_UART2_TX 8UL /*!<DMA Connect to UART2_TX \hideinitializer */ 85 #define PDMA_UART2_RX 9UL /*!<DMA Connect to UART2_RX \hideinitializer */ 86 #define PDMA_UART3_TX 10UL /*!<DMA Connect to UART3_TX \hideinitializer */ 87 #define PDMA_UART3_RX 11UL /*!<DMA Connect to UART3_RX \hideinitializer */ 88 #define PDMA_UART4_TX 12UL /*!<DMA Connect to UART4_TX \hideinitializer */ 89 #define PDMA_UART4_RX 13UL /*!<DMA Connect to UART4_RX \hideinitializer */ 90 #define PDMA_UART5_TX 14UL /*!<DMA Connect to UART5_TX \hideinitializer */ 91 #define PDMA_UART5_RX 15UL /*!<DMA Connect to UART5_RX \hideinitializer */ 92 #define PDMA_USCI0_TX 16UL /*!<DMA Connect to USCI0_TX \hideinitializer */ 93 #define PDMA_USCI0_RX 17UL /*!<DMA Connect to USCI0_RX \hideinitializer */ 94 #define PDMA_USCI1_TX 18UL /*!<DMA Connect to USCI1_TX \hideinitializer */ 95 #define PDMA_USCI1_RX 19UL /*!<DMA Connect to USCI1_RX \hideinitializer */ 96 #define PDMA_QSPI0_TX 20UL /*!<DMA Connect to QSPI0_TX \hideinitializer */ 97 #define PDMA_QSPI0_RX 21UL /*!<DMA Connect to QSPI0_RX \hideinitializer */ 98 #define PDMA_SPI0_TX 22UL /*!<DMA Connect to SPI0_TX \hideinitializer */ 99 #define PDMA_SPI0_RX 23UL /*!<DMA Connect to SPI0_RX \hideinitializer */ 100 #define PDMA_SPI1_TX 24UL /*!<DMA Connect to SPI1_TX \hideinitializer */ 101 #define PDMA_SPI1_RX 25UL /*!<DMA Connect to SPI1_RX \hideinitializer */ 102 #define PDMA_SPI2_TX 26UL /*!<DMA Connect to SPI2_TX \hideinitializer */ 103 #define PDMA_SPI2_RX 27UL /*!<DMA Connect to SPI2_RX \hideinitializer */ 104 #define PDMA_SPI3_TX 28UL /*!<DMA Connect to SPI3_TX \hideinitializer */ 105 #define PDMA_SPI3_RX 29UL /*!<DMA Connect to SPI3_RX \hideinitializer */ 106 #define PDMA_ACMP0 30UL /*!<DMA Connect to ACMP0 \hideinitializer */ 107 #define PDMA_ACMP1 31UL /*!<DMA Connect to ACMP1 \hideinitializer */ 108 #define PDMA_EPWM0_P1_RX 32UL /*!<DMA Connect to EPWM0_P1_RX \hideinitializer */ 109 #define PDMA_EPWM0_P2_RX 33UL /*!<DMA Connect to EPWM0_P2_RX \hideinitializer */ 110 #define PDMA_EPWM0_P3_RX 34UL /*!<DMA Connect to EPWM0_P3_RX \hideinitializer */ 111 #define PDMA_EPWM1_P1_RX 35UL /*!<DMA Connect to EPWM1_P1_RX \hideinitializer */ 112 #define PDMA_EPWM1_P2_RX 36UL /*!<DMA Connect to EPWM1_P2_RX \hideinitializer */ 113 #define PDMA_EPWM1_P3_RX 37UL /*!<DMA Connect to EPWM1_P3_RX \hideinitializer */ 114 #define PDMA_I2C0_TX 38UL /*!<DMA Connect to I2C0_TX \hideinitializer */ 115 #define PDMA_I2C0_RX 39UL /*!<DMA Connect to I2C0_RX \hideinitializer */ 116 #define PDMA_I2C1_TX 40UL /*!<DMA Connect to I2C1_TX \hideinitializer */ 117 #define PDMA_I2C1_RX 41UL /*!<DMA Connect to I2C1_RX \hideinitializer */ 118 #define PDMA_I2C2_TX 42UL /*!<DMA Connect to I2C2_TX \hideinitializer */ 119 #define PDMA_I2C2_RX 43UL /*!<DMA Connect to I2C2_RX \hideinitializer */ 120 #define PDMA_I2C3_TX 44UL /*!<DMA Connect to I2C3_TX \hideinitializer */ 121 #define PDMA_I2C3_RX 45UL /*!<DMA Connect to I2C3_RX \hideinitializer */ 122 #define PDMA_TMR0 46UL /*!<DMA Connect to TMR0 \hideinitializer */ 123 #define PDMA_TMR1 47UL /*!<DMA Connect to TMR1 \hideinitializer */ 124 #define PDMA_TMR2 48UL /*!<DMA Connect to TMR2 \hideinitializer */ 125 #define PDMA_TMR3 49UL /*!<DMA Connect to TMR3 \hideinitializer */ 126 #define PDMA_DAC0_TX 50UL /*!<DMA Connect to DAC0_TX \hideinitializer */ 127 #define PDMA_DAC1_TX 51UL /*!<DMA Connect to DAC1_TX \hideinitializer */ 128 #define PDMA_EPWM0_CH0_TX 52UL /*!<DMA Connect to EPWM0_CH0_TX \hideinitializer */ 129 #define PDMA_EPWM0_CH1_TX 53UL /*!<DMA Connect to EPWM0_CH1_TX \hideinitializer */ 130 #define PDMA_EPWM0_CH2_TX 54UL /*!<DMA Connect to EPWM0_CH2_TX \hideinitializer */ 131 #define PDMA_EPWM0_CH3_TX 55UL /*!<DMA Connect to EPWM0_CH3_TX \hideinitializer */ 132 #define PDMA_EPWM0_CH4_TX 56UL /*!<DMA Connect to EPWM0_CH4_TX \hideinitializer */ 133 #define PDMA_EPWM0_CH5_TX 57UL /*!<DMA Connect to EPWM0_CH5_TX \hideinitializer */ 134 #define PDMA_EPWM1_CH0_TX 58UL /*!<DMA Connect to EPWM1_CH0_TX \hideinitializer */ 135 #define PDMA_EPWM1_CH1_TX 59UL /*!<DMA Connect to EPWM1_CH1_TX \hideinitializer */ 136 #define PDMA_EPWM1_CH2_TX 60UL /*!<DMA Connect to EPWM1_CH2_TX \hideinitializer */ 137 #define PDMA_EPWM1_CH3_TX 61UL /*!<DMA Connect to EPWM1_CH3_TX \hideinitializer */ 138 #define PDMA_EPWM1_CH4_TX 62UL /*!<DMA Connect to EPWM1_CH4_TX \hideinitializer */ 139 #define PDMA_EPWM1_CH5_TX 63UL /*!<DMA Connect to EPWM1_CH5_TX \hideinitializer */ 140 #define PDMA_EADC0_RX 64UL /*!<DMA Connect to EADC0_RX \hideinitializer */ 141 #define PDMA_EADC1_RX 65UL /*!<DMA Connect to EADC1_RX \hideinitializer */ 142 #define PDMA_UART6_TX 66UL /*!<DMA Connect to UART6_TX \hideinitializer */ 143 #define PDMA_UART6_RX 67UL /*!<DMA Connect to UART6_RX \hideinitializer */ 144 #define PDMA_UART7_TX 68UL /*!<DMA Connect to UART7_TX \hideinitializer */ 145 #define PDMA_UART7_RX 69UL /*!<DMA Connect to UART7_RX \hideinitializer */ 146 #define PDMA_PWM0_P1_RX 70UL /*!<DMA Connect to PWM0_P1_RX \hideinitializer */ 147 #define PDMA_PWM0_P2_RX 71UL /*!<DMA Connect to PWM0_P2_RX \hideinitializer */ 148 #define PDMA_PWM0_P3_RX 72UL /*!<DMA Connect to PWM0_P3_RX \hideinitializer */ 149 #define PDMA_PWM1_P1_RX 73UL /*!<DMA Connect to PWM1_P1_RX \hideinitializer */ 150 #define PDMA_PWM1_P2_RX 74UL /*!<DMA Connect to PWM1_P2_RX \hideinitializer */ 151 #define PDMA_PWM1_P3_RX 75UL /*!<DMA Connect to PWM1_P3_RX \hideinitializer */ 152 #define PDMA_PWM0_CH0_TX 76UL /*!<DMA Connect to PWM0_CH0_TX \hideinitializer */ 153 #define PDMA_PWM0_CH2_TX 77UL /*!<DMA Connect to PWM0_CH2_TX \hideinitializer */ 154 #define PDMA_PWM0_CH4_TX 78UL /*!<DMA Connect to PWM0_CH4_TX \hideinitializer */ 155 #define PDMA_PWM1_CH0_TX 79UL /*!<DMA Connect to PWM1_CH0_TX \hideinitializer */ 156 #define PDMA_PWM1_CH2_TX 80UL /*!<DMA Connect to PWM1_CH2_TX \hideinitializer */ 157 #define PDMA_PWM1_CH4_TX 81UL /*!<DMA Connect to PWM1_CH4_TX \hideinitializer */ 158 #define PDMA_EINT0 82UL /*!<DMA Connect to EINT0 \hideinitializer */ 159 #define PDMA_EINT1 83UL /*!<DMA Connect to EINT1 \hideinitializer */ 160 #define PDMA_EINT2 84UL /*!<DMA Connect to EINT2 \hideinitializer */ 161 #define PDMA_EINT3 85UL /*!<DMA Connect to EINT3 \hideinitializer */ 162 #define PDMA_EINT4 86UL /*!<DMA Connect to EINT4 \hideinitializer */ 163 #define PDMA_EINT5 87UL /*!<DMA Connect to EINT5 \hideinitializer */ 164 #define PDMA_EINT6 88UL /*!<DMA Connect to EINT6 \hideinitializer */ 165 #define PDMA_EINT7 89UL /*!<DMA Connect to EINT7 \hideinitializer */ 166 #define PDMA_ACMP2 90UL /*!<DMA Connect to ACMP2 \hideinitializer */ 167 /*---------------------------------------------------------------------------------------------------------*/ 168 /* Interrupt Type Constant Definitions */ 169 /*---------------------------------------------------------------------------------------------------------*/ 170 #define PDMA_INT_TRANS_DONE 0x00000000UL /*!<Transfer Done Interrupt \hideinitializer */ 171 #define PDMA_INT_TEMPTY 0x00000001UL /*!<Table Empty Interrupt \hideinitializer */ 172 #define PDMA_INT_TIMEOUT 0x00000002UL /*!<Timeout Interrupt \hideinitializer */ 173 174 175 /*@}*/ /* end of group PDMA_EXPORTED_CONSTANTS */ 176 177 /** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions 178 @{ 179 */ 180 181 /** 182 * @brief Get PDMA Interrupt Status 183 * 184 * @param[in] pdma The pointer of the specified PDMA module 185 * 186 * @return None 187 * 188 * @details This macro gets the interrupt status. 189 * \hideinitializer 190 */ 191 #define PDMA_GET_INT_STATUS(pdma) ((uint32_t)(pdma->INTSTS)) 192 193 /** 194 * @brief Get Transfer Done Interrupt Status 195 * 196 * @param[in] pdma The pointer of the specified PDMA module 197 * 198 * @return None 199 * 200 * @details Get the transfer done Interrupt status. 201 * \hideinitializer 202 */ 203 #define PDMA_GET_TD_STS(pdma) ((uint32_t)(pdma->TDSTS)) 204 205 /** 206 * @brief Clear Transfer Done Interrupt Status 207 * 208 * @param[in] pdma The pointer of the specified PDMA module 209 * 210 * @param[in] u32Mask The channel mask 211 * 212 * @return None 213 * 214 * @details Clear the transfer done Interrupt status. 215 * \hideinitializer 216 */ 217 #define PDMA_CLR_TD_FLAG(pdma,u32Mask) ((uint32_t)(pdma->TDSTS = (u32Mask))) 218 219 /** 220 * @brief Get Target Abort Interrupt Status 221 * 222 * @param[in] pdma The pointer of the specified PDMA module 223 * 224 * @return None 225 * 226 * @details Get the target abort Interrupt status. 227 * \hideinitializer 228 */ 229 #define PDMA_GET_ABORT_STS(pdma) ((uint32_t)(pdma->ABTSTS)) 230 231 /** 232 * @brief Clear Target Abort Interrupt Status 233 * 234 * @param[in] pdma The pointer of the specified PDMA module 235 * 236 * @param[in] u32Mask The channel mask 237 * 238 * @return None 239 * 240 * @details Clear the target abort Interrupt status. 241 * \hideinitializer 242 */ 243 #define PDMA_CLR_ABORT_FLAG(pdma,u32Mask) ((uint32_t)(pdma->ABTSTS = (u32Mask))) 244 245 /** 246 * @brief Get Alignment Interrupt Status 247 * 248 * @param[in] pdma The pointer of the specified PDMA module 249 * 250 * @return None 251 * 252 * @details Get Alignment Interrupt status. 253 * \hideinitializer 254 */ 255 #define PDMA_GET_ALIGN_STS(pdma) ((uint32_t)(pdma->ALIGN)) 256 257 /** 258 * @brief Clear Alignment Interrupt Status 259 * 260 * @param[in] pdma The pointer of the specified PDMA module 261 * @param[in] u32Mask The channel mask 262 * 263 * @return None 264 * 265 * @details Clear the Alignment Interrupt status. 266 * \hideinitializer 267 */ 268 #define PDMA_CLR_ALIGN_FLAG(pdma,u32Mask) ((uint32_t)(pdma->ALIGN = (u32Mask))) 269 270 /** 271 * @brief Clear Timeout Interrupt Status 272 * 273 * @param[in] pdma The pointer of the specified PDMA module 274 * @param[in] u32Ch The selected channel 275 * 276 * @return None 277 * 278 * @details Clear the selected channel timeout interrupt status. 279 * \hideinitializer 280 */ 281 #define PDMA_CLR_TMOUT_FLAG(pdma,u32Ch) ((uint32_t)(pdma->INTSTS = (1UL << ((u32Ch) + 8UL)))) 282 283 /** 284 * @brief Check Channel Status 285 * 286 * @param[in] pdma The pointer of the specified PDMA module 287 * @param[in] u32Ch The selected channel 288 * 289 * @retval 0 Idle state 290 * @retval 1 Busy state 291 * 292 * @details Check the selected channel is busy or not. 293 * \hideinitializer 294 */ 295 #define PDMA_IS_CH_BUSY(pdma,u32Ch) ((uint32_t)(pdma->TRGSTS & (1UL << (u32Ch)))? 1 : 0) 296 297 /** 298 * @brief Set Source Address 299 * 300 * @param[in] pdma The pointer of the specified PDMA module 301 * @param[in] u32Ch The selected channel 302 * @param[in] u32Addr The selected address 303 * 304 * @return None 305 * 306 * @details This macro set the selected channel source address. 307 * \hideinitializer 308 */ 309 #define PDMA_SET_SRC_ADDR(pdma,u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].SA = (u32Addr))) 310 311 /** 312 * @brief Set Destination Address 313 * 314 * @param[in] pdma The pointer of the specified PDMA module 315 * @param[in] u32Ch The selected channel 316 * @param[in] u32Addr The selected address 317 * 318 * @return None 319 * 320 * @details This macro set the selected channel destination address. 321 * \hideinitializer 322 */ 323 #define PDMA_SET_DST_ADDR(pdma,u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].DA = (u32Addr))) 324 325 /** 326 * @brief Set Transfer Count 327 * 328 * @param[in] pdma The pointer of the specified PDMA module 329 * @param[in] u32Ch The selected channel 330 * @param[in] u32TransCount Transfer Count 331 * 332 * @return None 333 * 334 * @details This macro set the selected channel transfer count. 335 * \hideinitializer 336 */ 337 #define PDMA_SET_TRANS_CNT(pdma,u32Ch, u32TransCount) ((uint32_t)(pdma->DSCT[(u32Ch)].CTL=(pdma->DSCT[(u32Ch)].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|(((u32TransCount)-1UL) << PDMA_DSCT_CTL_TXCNT_Pos))) 338 339 /** 340 * @brief Set Scatter-gather descriptor Address 341 * 342 * @param[in] pdma The pointer of the specified PDMA module 343 * @param[in] u32Ch The selected channel 344 * @param[in] u32Addr The descriptor address 345 * 346 * @return None 347 * 348 * @details This macro set the selected channel scatter-gather descriptor address. 349 * \hideinitializer 350 */ 351 #define PDMA_SET_SCATTER_DESC(pdma,u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].NEXT = (u32Addr) - (pdma->SCATBA))) 352 353 /** 354 * @brief Stop the channel 355 * 356 * @param[in] pdma The pointer of the specified PDMA module 357 * 358 * @param[in] u32Ch The selected channel 359 * 360 * @return None 361 * 362 * @details This macro stop the selected channel. 363 * \hideinitializer 364 */ 365 #define PDMA_STOP(pdma,u32Ch) ((uint32_t)(pdma->PAUSE = (1UL << (u32Ch)))) 366 367 /** 368 * @brief Pause the channel 369 * 370 * @param[in] pdma The pointer of the specified PDMA module 371 * 372 * @param[in] u32Ch The selected channel 373 * 374 * @return None 375 * 376 * @details This macro pause the selected channel. 377 * \hideinitializer 378 */ 379 #define PDMA_PAUSE(pdma,u32Ch) ((uint32_t)(pdma->PAUSE = (1UL << (u32Ch)))) 380 381 /*---------------------------------------------------------------------------------------------------------*/ 382 /* Define PDMA functions prototype */ 383 /*---------------------------------------------------------------------------------------------------------*/ 384 void PDMA_Open(PDMA_T * pdma,uint32_t u32Mask); 385 void PDMA_Close(PDMA_T * pdma); 386 void PDMA_SetTransferCnt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount); 387 void PDMA_SetTransferAddr(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl); 388 void PDMA_SetTransferMode(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr); 389 void PDMA_SetBurstType(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize); 390 void PDMA_EnableTimeout(PDMA_T * pdma,uint32_t u32Mask); 391 void PDMA_DisableTimeout(PDMA_T * pdma,uint32_t u32Mask); 392 void PDMA_SetTimeOut(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt); 393 void PDMA_Trigger(PDMA_T * pdma,uint32_t u32Ch); 394 void PDMA_EnableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask); 395 void PDMA_DisableInt(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32Mask); 396 397 398 /*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */ 399 400 /*@}*/ /* end of group PDMA_Driver */ 401 402 /*@}*/ /* end of group Standard_Driver */ 403 404 #ifdef __cplusplus 405 } 406 #endif 407 408 #endif /* __PDMA_H__ */ 409 410 /*** (C) COPYRIGHT 2023 Nuvoton Technology Corp. ***/ 411
