1 /**************************************************************************//** 2 * @file epwm.h 3 * @version V3.00 4 * @brief M2L31 series EPWM driver header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __EPWM_H__ 10 #define __EPWM_H__ 11 12 #ifdef __cplusplus 13 extern "C" 14 { 15 #endif 16 17 18 /** @addtogroup Standard_Driver Standard Driver 19 @{ 20 */ 21 22 /** @addtogroup EPWM_Driver EPWM Driver 23 @{ 24 */ 25 26 /** @addtogroup EPWM_EXPORTED_CONSTANTS EPWM Exported Constants 27 @{ 28 */ 29 #define EPWM_CHANNEL_NUM (6U) /*!< EPWM channel number \hideinitializer */ 30 #define EPWM_CH_0_MASK (0x1U) /*!< EPWM channel 0 mask \hideinitializer */ 31 #define EPWM_CH_1_MASK (0x2U) /*!< EPWM channel 1 mask \hideinitializer */ 32 #define EPWM_CH_2_MASK (0x4U) /*!< EPWM channel 2 mask \hideinitializer */ 33 #define EPWM_CH_3_MASK (0x8U) /*!< EPWM channel 3 mask \hideinitializer */ 34 #define EPWM_CH_4_MASK (0x10U) /*!< EPWM channel 4 mask \hideinitializer */ 35 #define EPWM_CH_5_MASK (0x20U) /*!< EPWM channel 5 mask \hideinitializer */ 36 37 /*---------------------------------------------------------------------------------------------------------*/ 38 /* Counter Type Constant Definitions */ 39 /*---------------------------------------------------------------------------------------------------------*/ 40 #define EPWM_UP_COUNTER (0U) /*!< Up counter type \hideinitializer */ 41 #define EPWM_DOWN_COUNTER (1U) /*!< Down counter type \hideinitializer */ 42 #define EPWM_UP_DOWN_COUNTER (2U) /*!< Up-Down counter type \hideinitializer */ 43 44 /*---------------------------------------------------------------------------------------------------------*/ 45 /* Aligned Type Constant Definitions */ 46 /*---------------------------------------------------------------------------------------------------------*/ 47 #define EPWM_EDGE_ALIGNED (1U) /*!< EPWM working in edge aligned type(down count) \hideinitializer */ 48 #define EPWM_CENTER_ALIGNED (2U) /*!< EPWM working in center aligned type \hideinitializer */ 49 50 /*---------------------------------------------------------------------------------------------------------*/ 51 /* Output Level Constant Definitions */ 52 /*---------------------------------------------------------------------------------------------------------*/ 53 #define EPWM_OUTPUT_NOTHING (0U) /*!< EPWM output nothing \hideinitializer */ 54 #define EPWM_OUTPUT_LOW (1U) /*!< EPWM output low \hideinitializer */ 55 #define EPWM_OUTPUT_HIGH (2U) /*!< EPWM output high \hideinitializer */ 56 #define EPWM_OUTPUT_TOGGLE (3U) /*!< EPWM output toggle \hideinitializer */ 57 58 /*---------------------------------------------------------------------------------------------------------*/ 59 /* Synchronous Start Function Control Constant Definitions */ 60 /*---------------------------------------------------------------------------------------------------------*/ 61 #define EPWM_SSCTL_SSRC_EPWM0 (0U<<EPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from EPWM0 \hideinitializer */ 62 #define EPWM_SSCTL_SSRC_EPWM1 (1U<<EPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from EPWM0 \hideinitializer */ 63 #define EPWM_SSCTL_SSRC_PWM0 (2U<<EPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from PWM0 \hideinitializer */ 64 #define EPWM_SSCTL_SSRC_PWM1 (3U<<EPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from PWM1 \hideinitializer */ 65 66 /*---------------------------------------------------------------------------------------------------------*/ 67 /* Trigger Source Select Constant Definitions */ 68 /*---------------------------------------------------------------------------------------------------------*/ 69 #define EPWM_TRG_ADC_EVEN_ZERO (0U) /*!< EPWM trigger ADC while counter of even channel matches zero point \hideinitializer */ 70 #define EPWM_TRG_ADC_EVEN_PERIOD (1U) /*!< EPWM trigger ADC while counter of even channel matches period point \hideinitializer */ 71 #define EPWM_TRG_ADC_EVEN_ZERO_PERIOD (2U) /*!< EPWM trigger ADC while counter of even channel matches zero or period point \hideinitializer */ 72 #define EPWM_TRG_ADC_EVEN_COMPARE_UP (3U) /*!< EPWM trigger ADC while counter of even channel matches up count to comparator point \hideinitializer */ 73 #define EPWM_TRG_ADC_EVEN_COMPARE_DOWN (4U) /*!< EPWM trigger ADC while counter of even channel matches down count to comparator point \hideinitializer */ 74 #define EPWM_TRG_ADC_ODD_ZERO (5U) /*!< EPWM trigger ADC while counter of odd channel matches zero point \hideinitializer */ 75 #define EPWM_TRG_ADC_ODD_PERIOD (6U) /*!< EPWM trigger ADC while counter of odd channel matches period point \hideinitializer */ 76 #define EPWM_TRG_ADC_ODD_ZERO_PERIOD (7U) /*!< EPWM trigger ADC while counter of odd channel matches zero or period point \hideinitializer */ 77 #define EPWM_TRG_ADC_ODD_COMPARE_UP (8U) /*!< EPWM trigger ADC while counter of odd channel matches up count to comparator point \hideinitializer */ 78 #define EPWM_TRG_ADC_ODD_COMPARE_DOWN (9U) /*!< EPWM trigger ADC while counter of odd channel matches down count to comparator point \hideinitializer */ 79 #define EPWM_TRG_ADC_CH_0_FREE_CMP_UP (10U) /*!< EPWM trigger ADC while counter of channel 0 matches up count to free comparator point \hideinitializer */ 80 #define EPWM_TRG_ADC_CH_0_FREE_CMP_DOWN (11U) /*!< EPWM trigger ADC while counter of channel 0 matches down count to free comparator point \hideinitializer */ 81 #define EPWM_TRG_ADC_CH_2_FREE_CMP_UP (12U) /*!< EPWM trigger ADC while counter of channel 2 matches up count to free comparator point \hideinitializer */ 82 #define EPWM_TRG_ADC_CH_2_FREE_CMP_DOWN (13U) /*!< EPWM trigger ADC while counter of channel 2 matches down count to free comparator point \hideinitializer */ 83 #define EPWM_TRG_ADC_CH_4_FREE_CMP_UP (14U) /*!< EPWM trigger ADC while counter of channel 4 matches up count to free comparator point \hideinitializer */ 84 #define EPWM_TRG_ADC_CH_4_FREE_CMP_DOWN (15U) /*!< EPWM trigger ADC while counter of channel 4 matches down count to free comparator point \hideinitializer */ 85 86 #define EPWM_TRIGGER_DAC_ZERO (0x1U) /*!< EPWM trigger DAC while counter down count to 0 \hideinitializer */ 87 #define EPWM_TRIGGER_DAC_PERIOD (0x100U) /*!< EPWM trigger DAC while counter matches (PERIOD + 1) \hideinitializer */ 88 #define EPWM_TRIGGER_DAC_COMPARE_UP (0x10000U) /*!< EPWM trigger DAC while counter up count to CMPDAT \hideinitializer */ 89 #define EPWM_TRIGGER_DAC_COMPARE_DOWN (0x1000000U) /*!< EPWM trigger DAC while counter down count to CMPDAT \hideinitializer */ 90 91 /*---------------------------------------------------------------------------------------------------------*/ 92 /* Fail brake Control Constant Definitions */ 93 /*---------------------------------------------------------------------------------------------------------*/ 94 #define EPWM_FB_EDGE_ACMP0 (EPWM_BRKCTL0_1_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source \hideinitializer */ 95 #define EPWM_FB_EDGE_ACMP1 (EPWM_BRKCTL0_1_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source \hideinitializer */ 96 #define EPWM_FB_EDGE_BKP0 (EPWM_BRKCTL0_1_BRKP0EEN_Msk) /*!< BKP0 pin as edge-detect fault brake source \hideinitializer */ 97 #define EPWM_FB_EDGE_BKP1 (EPWM_BRKCTL0_1_BRKP1EEN_Msk) /*!< BKP1 pin as edge-detect fault brake source \hideinitializer */ 98 #define EPWM_FB_EDGE_ADCRM (EPWM_BRKCTL0_1_EADCEBEN_Msk) /*!< ADC Result Monitor (ADCRM) as edge-detect fault brake source \hideinitializer */ 99 #define EPWM_FB_EDGE_SYS_CSS (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as edge-detect fault brake source \hideinitializer */ 100 #define EPWM_FB_EDGE_SYS_BOD (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as edge-detect fault brake source \hideinitializer */ 101 #define EPWM_FB_EDGE_SYS_RAM (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source \hideinitializer */ 102 #define EPWM_FB_EDGE_SYS_COR (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as edge-detect fault brake source \hideinitializer */ 103 104 #define EPWM_FB_LEVEL_ACMP0 (EPWM_BRKCTL0_1_CPO0LBEN_Msk) /*!< Comparator 0 as level-detect fault brake source \hideinitializer */ 105 #define EPWM_FB_LEVEL_ACMP1 (EPWM_BRKCTL0_1_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source \hideinitializer */ 106 #define EPWM_FB_LEVEL_BKP0 (EPWM_BRKCTL0_1_BRKP0LEN_Msk) /*!< BKP0 pin as level-detect fault brake source \hideinitializer */ 107 #define EPWM_FB_LEVEL_BKP1 (EPWM_BRKCTL0_1_BRKP1LEN_Msk) /*!< BKP1 pin as level-detect fault brake source \hideinitializer */ 108 #define EPWM_FB_LEVEL_ADCRM (EPWM_BRKCTL0_1_EADCLBEN_Msk) /*!< ADC Result Monitor (ADCRM) as level-detect fault brake source \hideinitializer */ 109 #define EPWM_FB_LEVEL_SYS_CSS (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as level-detect fault brake source \hideinitializer */ 110 #define EPWM_FB_LEVEL_SYS_BOD (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as level-detect fault brake source \hideinitializer */ 111 #define EPWM_FB_LEVEL_SYS_RAM (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as level-detect fault brake source \hideinitializer */ 112 #define EPWM_FB_LEVEL_SYS_COR (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as level-detect fault brake source \hideinitializer */ 113 114 #define EPWM_FB_EDGE (0U) /*!< edge-detect fault brake \hideinitializer */ 115 #define EPWM_FB_LEVEL (8U) /*!< level-detect fault brake \hideinitializer */ 116 117 /*---------------------------------------------------------------------------------------------------------*/ 118 /* Leading Edge Blanking Control Constant Definitions */ 119 /*---------------------------------------------------------------------------------------------------------*/ 120 #define EPWM_LEBCTL_TRGTYPE_RISING (0U<<EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM Leading Edge Blanking Trigger Type Is Rising Edge \hideinitializer */ 121 #define EPWM_LEBCTL_TRGTYPE_FALLING (1U<<EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM Leading Edge Blanking Trigger Type Is Falling Edge \hideinitializer */ 122 #define EPWM_LEBCTL_TRGTYPE_RISING_OR_FALLING (2U<<EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM Leading Edge Blanking Trigger Type Is Rising or Falling Edge \hideinitializer */ 123 #define EPWM_LEBCTL_SRCEN0 (EPWM_LEBCTL_SRCEN0_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0 Enable \hideinitializer */ 124 #define EPWM_LEBCTL_SRCEN2 (EPWM_LEBCTL_SRCEN2_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH2 Enable \hideinitializer */ 125 #define EPWM_LEBCTL_SRCEN4 (EPWM_LEBCTL_SRCEN4_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH4 Enable \hideinitializer */ 126 #define EPWM_LEBCTL_SRCEN0_2 (EPWM_LEBCTL_SRCEN0_Msk|EPWM_LEBCTL_SRCEN2_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0 and EPWMx_CH2 Enable \hideinitializer */ 127 #define EPWM_LEBCTL_SRCEN0_4 (EPWM_LEBCTL_SRCEN0_Msk|EPWM_LEBCTL_SRCEN4_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0 and EPWMx_CH4 Enable \hideinitializer */ 128 #define EPWM_LEBCTL_SRCEN2_4 (EPWM_LEBCTL_SRCEN2_Msk|EPWM_LEBCTL_SRCEN4_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH2 and EPWMx_CH4 Enable \hideinitializer */ 129 #define EPWM_LEBCTL_SRCEN0_2_4 (EPWM_LEBCTL_SRCEN0_Msk|EPWM_LEBCTL_SRCEN2_Msk|EPWM_LEBCTL_SRCEN4_Msk) /*!< EPWM Leading Edge Blanking Source From EPWMx_CH0, EPWMx_CH2 and EPWMx_CH4 Enable \hideinitializer */ 130 131 /*---------------------------------------------------------------------------------------------------------*/ 132 /* Capture Control Constant Definitions */ 133 /*---------------------------------------------------------------------------------------------------------*/ 134 #define EPWM_CAPTURE_INT_RISING_LATCH (1U) /*!< EPWM capture interrupt if channel has rising transition \hideinitializer */ 135 #define EPWM_CAPTURE_INT_FALLING_LATCH (0x100U) /*!< EPWM capture interrupt if channel has falling transition \hideinitializer */ 136 137 #define EPWM_CAPTURE_PDMA_RISING_LATCH (0x2U) /*!< EPWM capture rising latched data transfer by PDMA \hideinitializer */ 138 #define EPWM_CAPTURE_PDMA_FALLING_LATCH (0x4U) /*!< EPWM capture falling latched data transfer by PDMA \hideinitializer */ 139 #define EPWM_CAPTURE_PDMA_RISING_FALLING_LATCH (0x6U) /*!< EPWM capture rising and falling latched data transfer by PDMA \hideinitializer */ 140 141 /*---------------------------------------------------------------------------------------------------------*/ 142 /* Duty Interrupt Type Constant Definitions */ 143 /*---------------------------------------------------------------------------------------------------------*/ 144 #define EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP (1U << EPWM_INTEN0_CMPDIEN0_Pos) /*!< EPWM duty interrupt triggered if down count match comparator \hideinitializer */ 145 #define EPWM_DUTY_INT_UP_COUNT_MATCH_CMP (1U << EPWM_INTEN0_CMPUIEN0_Pos) /*!< EPWM duty interrupt triggered if up down match comparator \hideinitializer */ 146 147 /*---------------------------------------------------------------------------------------------------------*/ 148 /* Interrupt Flag Accumulator Constant Definitions */ 149 /*---------------------------------------------------------------------------------------------------------*/ 150 #define EPWM_IFA_ZERO_POINT (0U) /*!< EPWM counter equal to zero \hideinitializer */ 151 #define EPWM_IFA_PERIOD_POINT (1U) /*!< EPWM counter equal to period \hideinitializer */ 152 #define EPWM_IFA_COMPARE_UP_COUNT_POINT (2U) /*!< EPWM counter up count to comparator value \hideinitializer */ 153 #define EPWM_IFA_COMPARE_DOWN_COUNT_POINT (3U) /*!< EPWM counter down count to comparator value \hideinitializer */ 154 155 /*---------------------------------------------------------------------------------------------------------*/ 156 /* Load Mode Constant Definitions */ 157 /*---------------------------------------------------------------------------------------------------------*/ 158 #define EPWM_LOAD_MODE_IMMEDIATE (1U << EPWM_CTL0_IMMLDEN0_Pos) /*!< EPWM immediately load mode \hideinitializer */ 159 #define EPWM_LOAD_MODE_WINDOW (1U << EPWM_CTL0_WINLDEN0_Pos) /*!< EPWM window load mode \hideinitializer */ 160 #define EPWM_LOAD_MODE_CENTER (1U << EPWM_CTL0_CTRLD0_Pos) /*!< EPWM center load mode \hideinitializer */ 161 162 /*---------------------------------------------------------------------------------------------------------*/ 163 /* Synchronize Control Constant Definitions */ 164 /*---------------------------------------------------------------------------------------------------------*/ 165 #define EPWM_SYNC_OUT_FROM_SYNCIN_SWSYNC (0U) /*!< Synchronize source from SYNC_IN or SWSYNC \hideinitializer */ 166 #define EPWM_SYNC_OUT_FROM_COUNT_TO_ZERO (1U) /*!< Synchronize source from counter equal to 0 \hideinitializer */ 167 #define EPWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR (2U) /*!< Synchronize source from counter equal to CMPDAT1, CMPDAT3, CMPDAT5 \hideinitializer */ 168 #define EPWM_SYNC_OUT_DISABLE (3U) /*!< SYNC_OUT will not be generated \hideinitializer */ 169 #define EPWM_PHS_DIR_DECREMENT (0U) /*!< EPWM counter count decrement \hideinitializer */ 170 #define EPWM_PHS_DIR_INCREMENT (1U) /*!< EPWM counter count increment \hideinitializer */ 171 172 /*---------------------------------------------------------------------------------------------------------*/ 173 /* Noise Filter Clock Divide Select Constant Definitions */ 174 /*---------------------------------------------------------------------------------------------------------*/ 175 #define EPWM_NF_CLK_DIV_1 (0U) /*!< Noise filter clock is HCLK divide by 1 \hideinitializer */ 176 #define EPWM_NF_CLK_DIV_2 (1U) /*!< Noise filter clock is HCLK divide by 2 \hideinitializer */ 177 #define EPWM_NF_CLK_DIV_4 (2U) /*!< Noise filter clock is HCLK divide by 4 \hideinitializer */ 178 #define EPWM_NF_CLK_DIV_8 (3U) /*!< Noise filter clock is HCLK divide by 8 \hideinitializer */ 179 #define EPWM_NF_CLK_DIV_16 (4U) /*!< Noise filter clock is HCLK divide by 16 \hideinitializer */ 180 #define EPWM_NF_CLK_DIV_32 (5U) /*!< Noise filter clock is HCLK divide by 32 \hideinitializer */ 181 #define EPWM_NF_CLK_DIV_64 (6U) /*!< Noise filter clock is HCLK divide by 64 \hideinitializer */ 182 #define EPWM_NF_CLK_DIV_128 (7U) /*!< Noise filter clock is HCLK divide by 128 \hideinitializer */ 183 184 /*---------------------------------------------------------------------------------------------------------*/ 185 /* Clock Source Select Constant Definitions */ 186 /*---------------------------------------------------------------------------------------------------------*/ 187 #define EPWM_CLKSRC_EPWM_CLK (0U) /*!< EPWM Clock source selects to EPWM0_CLK or EPWM1_CLK \hideinitializer */ 188 #define EPWM_CLKSRC_TIMER0 (1U) /*!< EPWM Clock source selects to TIMER0 overflow \hideinitializer */ 189 #define EPWM_CLKSRC_TIMER1 (2U) /*!< EPWM Clock source selects to TIMER1 overflow \hideinitializer */ 190 #define EPWM_CLKSRC_TIMER2 (3U) /*!< EPWM Clock source selects to TIMER2 overflow \hideinitializer */ 191 #define EPWM_CLKSRC_TIMER3 (4U) /*!< EPWM Clock source selects to TIMER3 overflow \hideinitializer */ 192 193 /*---------------------------------------------------------------------------------------------------------*/ 194 /* Fault Detect Clock Source Select Constant Definitions */ 195 /*---------------------------------------------------------------------------------------------------------*/ 196 #define EPWM_FDCTL_FDCKSEL_CLK_DIV_1 (0UL << EPWM_FDCTL0_FDCKSEL_Pos) /*!< Fault detect clock selects to fault detect clock divided by 1 \hideinitializer */ 197 #define EPWM_FDCTL_FDCKSEL_CLK_DIV_2 (1UL << EPWM_FDCTL0_FDCKSEL_Pos) /*!< Fault detect clock selects to fault detect clock divided by 2 \hideinitializer */ 198 #define EPWM_FDCTL_FDCKSEL_CLK_DIV_4 (2UL << EPWM_FDCTL0_FDCKSEL_Pos) /*!< Fault detect clock selects to fault detect clock divided by 4 \hideinitializer */ 199 #define EPWM_FDCTL_FDCKSEL_CLK_DIV_8 (3UL << EPWM_FDCTL0_FDCKSEL_Pos) /*!< Fault detect clock selects to fault detect clock divided by 8 \hideinitializer */ 200 201 202 /*@}*/ /* end of group EPWM_EXPORTED_CONSTANTS */ 203 204 205 /** @addtogroup EPWM_EXPORTED_FUNCTIONS EPWM Exported Functions 206 @{ 207 */ 208 209 /** 210 * @brief This macro enable complementary mode 211 * @param[in] epwm The pointer of the specified EPWM module 212 * @return None 213 * @details This macro is used to enable complementary mode of EPWM module. 214 * \hideinitializer 215 */ 216 #define EPWM_ENABLE_COMPLEMENTARY_MODE(epwm) ((epwm)->CTL1 = (epwm)->CTL1 | (0x7ul<<EPWM_CTL1_OUTMODE0_Pos)) 217 218 /** 219 * @brief This macro disable complementary mode, and enable independent mode. 220 * @param[in] epwm The pointer of the specified EPWM module 221 * @return None 222 * @details This macro is used to disable complementary mode of EPWM module. 223 * \hideinitializer 224 */ 225 #define EPWM_DISABLE_COMPLEMENTARY_MODE(epwm) ((epwm)->CTL1 = (epwm)->CTL1 & ~(0x7ul<<EPWM_CTL1_OUTMODE0_Pos)) 226 227 /** 228 * @brief This macro enable group mode 229 * @param[in] epwm The pointer of the specified EPWM module 230 * @return None 231 * @details This macro is used to enable group mode of EPWM module. 232 * \hideinitializer 233 */ 234 #define EPWM_ENABLE_GROUP_MODE(epwm) ((epwm)->CTL0 = (epwm)->CTL0 | EPWM_CTL0_GROUPEN_Msk) 235 236 /** 237 * @brief This macro disable group mode 238 * @param[in] epwm The pointer of the specified EPWM module 239 * @return None 240 * @details This macro is used to disable group mode of EPWM module. 241 * \hideinitializer 242 */ 243 #define EPWM_DISABLE_GROUP_MODE(epwm) ((epwm)->CTL0 = (epwm)->CTL0 & ~EPWM_CTL0_GROUPEN_Msk) 244 245 /** 246 * @brief Enable timer synchronous start counting function of specified channel(s) 247 * @param[in] epwm The pointer of the specified EPWM module 248 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 249 * Bit 0 represents channel 0, bit 1 represents channel 1... 250 * @param[in] u32SyncSrc Synchronous start source selection, valid values are: 251 * - \ref EPWM_SSCTL_SSRC_EPWM0 252 * - \ref EPWM_SSCTL_SSRC_EPWM1 253 * - \ref EPWM_SSCTL_SSRC_PWM0 254 * - \ref EPWM_SSCTL_SSRC_PWM1 255 * @return None 256 * @details This macro is used to enable timer synchronous start counting function of specified channel(s). 257 * \hideinitializer 258 */ 259 #define EPWM_ENABLE_TIMER_SYNC(epwm, u32ChannelMask, u32SyncSrc) ((epwm)->SSCTL = ((epwm)->SSCTL & ~EPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | (u32ChannelMask)) 260 261 /** 262 * @brief Disable timer synchronous start counting function of specified channel(s) 263 * @param[in] epwm The pointer of the specified EPWM module 264 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 265 * Bit 0 represents channel 0, bit 1 represents channel 1... 266 * @return None 267 * @details This macro is used to disable timer synchronous start counting function of specified channel(s). 268 * \hideinitializer 269 */ 270 #define EPWM_DISABLE_TIMER_SYNC(epwm, u32ChannelMask) \ 271 do{ \ 272 int i;\ 273 for(i = 0; i < 6; i++) { \ 274 if((u32ChannelMask) & (1 << i)) \ 275 (epwm)->SSCTL &= ~(1UL << i); \ 276 } \ 277 }while(0) 278 279 /** 280 * @brief This macro enable EPWM counter synchronous start counting function. 281 * @param[in] epwm The pointer of the specified EPWM module 282 * @return None 283 * @details This macro is used to make selected EPWM0 and EPWM1 channel(s) start counting at the same time. 284 * To configure synchronous start counting channel(s) by EPWM_ENABLE_TIMER_SYNC() and EPWM_DISABLE_TIMER_SYNC(). 285 * \hideinitializer 286 */ 287 #define EPWM_TRIGGER_SYNC_START(epwm) ((epwm)->SSTRG = EPWM_SSTRG_CNTSEN_Msk) 288 289 /** 290 * @brief This macro enable output inverter of specified channel(s) 291 * @param[in] epwm The pointer of the specified EPWM module 292 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 293 * Bit 0 represents channel 0, bit 1 represents channel 1... 294 * @return None 295 * @details This macro is used to enable output inverter of specified channel(s). 296 * \hideinitializer 297 */ 298 #define EPWM_ENABLE_OUTPUT_INVERTER(epwm, u32ChannelMask) ((epwm)->POLCTL = (u32ChannelMask)) 299 300 /** 301 * @brief This macro get captured rising data 302 * @param[in] epwm The pointer of the specified EPWM module 303 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 304 * @return None 305 * @details This macro is used to get captured rising data of specified channel. 306 * \hideinitializer 307 */ 308 #define EPWM_GET_CAPTURE_RISING_DATA(epwm, u32ChannelNum) (*(__IO uint32_t *) (&((epwm)->RCAPDAT0) + 2 * (u32ChannelNum))) 309 310 /** 311 * @brief This macro get captured falling data 312 * @param[in] epwm The pointer of the specified EPWM module 313 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 314 * @return None 315 * @details This macro is used to get captured falling data of specified channel. 316 * \hideinitializer 317 */ 318 #define EPWM_GET_CAPTURE_FALLING_DATA(epwm, u32ChannelNum) (*(__IO uint32_t *) (&((epwm)->FCAPDAT0) + 2 * (u32ChannelNum))) 319 320 /** 321 * @brief This macro mask output logic to high or low 322 * @param[in] epwm The pointer of the specified EPWM module 323 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 324 * Bit 0 represents channel 0, bit 1 represents channel 1... 325 * @param[in] u32LevelMask Output logic to high or low 326 * @return None 327 * @details This macro is used to mask output logic to high or low of specified channel(s). 328 * @note If u32ChannelMask parameter is 0, then mask function will be disabled. 329 * \hideinitializer 330 */ 331 #define EPWM_MASK_OUTPUT(epwm, u32ChannelMask, u32LevelMask) \ 332 { \ 333 (epwm)->MSKEN = (u32ChannelMask); \ 334 (epwm)->MSK = (u32LevelMask); \ 335 } 336 337 /** 338 * @brief This macro set the prescaler of the selected channel 339 * @param[in] epwm The pointer of the specified EPWM module 340 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 341 * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF 342 * @return None 343 * @details This macro is used to set the prescaler of specified channel. 344 * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected. 345 * The clock of EPWM counter is divided by (u32Prescaler + 1). 346 * \hideinitializer 347 */ 348 #define EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescaler) ((epwm)->CLKPSC[(u32ChannelNum) >> 1] = (u32Prescaler)) 349 350 /** 351 * @brief This macro get the prescaler of the selected channel 352 * @param[in] epwm The pointer of the specified EPWM module 353 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 354 * @return Return Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF 355 * @details This macro is used to get the prescaler of specified channel. 356 * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected. 357 * The clock of EPWM counter is divided by (u32Prescaler + 1). 358 * \hideinitializer 359 */ 360 #define EPWM_GET_PRESCALER(epwm, u32ChannelNum) ((epwm)->CLKPSC[(u32ChannelNum) >> 1U]) 361 362 /** 363 * @brief This macro set the comparator of the selected channel 364 * @param[in] epwm The pointer of the specified EPWM module 365 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 366 * @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF 367 * @return None 368 * @details This macro is used to set the comparator of specified channel. 369 * @note This new setting will take effect on next EPWM period. 370 * \hideinitializer 371 */ 372 #define EPWM_SET_CMR(epwm, u32ChannelNum, u32CMR) ((epwm)->CMPDAT[(u32ChannelNum)]= (u32CMR)) 373 374 /** 375 * @brief This macro get the comparator of the selected channel 376 * @param[in] epwm The pointer of the specified EPWM module 377 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 378 * @return Return the comparator of specified channel. Valid values are between 0~0xFFFF 379 * @details This macro is used to get the comparator of specified channel. 380 * \hideinitializer 381 */ 382 #define EPWM_GET_CMR(epwm, u32ChannelNum) ((epwm)->CMPDAT[(u32ChannelNum)]) 383 384 /** 385 * @brief This macro set the free trigger comparator of the selected channel 386 * @param[in] epwm The pointer of the specified EPWM module 387 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 388 * @param[in] u32FTCMR Free trigger comparator of specified channel. Valid values are between 0~0xFFFF 389 * @return None 390 * @details This macro is used to set the free trigger comparator of specified channel. 391 * @note This new setting will take effect on next EPWM period. 392 * \hideinitializer 393 */ 394 #define EPWM_SET_FTCMR(epwm, u32ChannelNum, u32FTCMR) (((epwm)->FTCMPDAT[((u32ChannelNum) >> 1U)]) = (u32FTCMR)) 395 396 /** 397 * @brief This macro set the period of the selected channel 398 * @param[in] epwm The pointer of the specified EPWM module 399 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 400 * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF 401 * @return None 402 * @details This macro is used to set the period of specified channel. 403 * @note This new setting will take effect on next EPWM period. 404 * @note EPWM counter will stop if period length set to 0. 405 * \hideinitializer 406 */ 407 #define EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR) ((epwm)->PERIOD[(u32ChannelNum)] = (u32CNR)) 408 409 /** 410 * @brief This macro get the period of the selected channel 411 * @param[in] epwm The pointer of the specified EPWM module 412 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 413 * @return Return the period of specified channel. Valid values are between 0~0xFFFF 414 * @details This macro is used to get the period of specified channel. 415 * \hideinitializer 416 */ 417 #define EPWM_GET_CNR(epwm, u32ChannelNum) ((epwm)->PERIOD[(u32ChannelNum)]) 418 419 /** 420 * @brief This macro set the EPWM aligned type 421 * @param[in] epwm The pointer of the specified EPWM module 422 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 423 * Bit 0 represents channel 0, bit 1 represents channel 1... 424 * @param[in] u32AlignedType EPWM aligned type, valid values are: 425 * - \ref EPWM_EDGE_ALIGNED 426 * - \ref EPWM_CENTER_ALIGNED 427 * @return None 428 * @details This macro is used to set the EPWM aligned type of specified channel(s). 429 * \hideinitializer 430 */ 431 #define EPWM_SET_ALIGNED_TYPE(epwm, u32ChannelMask, u32AlignedType) \ 432 do{ \ 433 int i; \ 434 for(i = 0; i < 6; i++) { \ 435 if((u32ChannelMask) & (1 << i)) \ 436 (epwm)->CTL1 = (((epwm)->CTL1 & ~(3UL << (i << 1))) | ((u32AlignedType) << (i << 1))); \ 437 } \ 438 }while(0) 439 440 /** 441 * @brief Set load window of window loading mode for specified channel(s) 442 * @param[in] epwm The pointer of the specified EPWM module 443 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 444 * Bit 0 represents channel 0, bit 1 represents channel 1... 445 * @return None 446 * @details This macro is used to set load window of window loading mode for specified channel(s). 447 * \hideinitializer 448 */ 449 #define EPWM_SET_LOAD_WINDOW(epwm, u32ChannelMask) ((epwm)->LOAD |= (u32ChannelMask)) 450 451 /** 452 * @brief Trigger synchronous event from specified channel(s) 453 * @param[in] epwm The pointer of the specified EPWM module 454 * @param[in] u32ChannelNum EPWM channel number. Valid values are 0, 2, 4 455 * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 456 * @return None 457 * @details This macro is used to trigger synchronous event from specified channel(s). 458 * \hideinitializer 459 */ 460 #define EPWM_TRIGGER_SYNC(epwm, u32ChannelNum) ((epwm)->SWSYNC |= (1 << ((u32ChannelNum) >> 1))) 461 462 /** 463 * @brief Clear counter of specified channel(s) 464 * @param[in] epwm The pointer of the specified EPWM module 465 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 466 * Bit 0 represents channel 0, bit 1 represents channel 1... 467 * @return None 468 * @details This macro is used to clear counter of specified channel(s). 469 * \hideinitializer 470 */ 471 #define EPWM_CLR_COUNTER(epwm, u32ChannelMask) ((epwm)->CNTCLR |= (u32ChannelMask)) 472 473 /** 474 * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s) 475 * @param[in] epwm The pointer of the specified EPWM module 476 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 477 * Bit 0 represents channel 0, bit 1 represents channel 1... 478 * @param[in] u32ZeroLevel output level at zero point, valid values are: 479 * - \ref EPWM_OUTPUT_NOTHING 480 * - \ref EPWM_OUTPUT_LOW 481 * - \ref EPWM_OUTPUT_HIGH 482 * - \ref EPWM_OUTPUT_TOGGLE 483 * @param[in] u32CmpUpLevel output level at compare up point, valid values are: 484 * - \ref EPWM_OUTPUT_NOTHING 485 * - \ref EPWM_OUTPUT_LOW 486 * - \ref EPWM_OUTPUT_HIGH 487 * - \ref EPWM_OUTPUT_TOGGLE 488 * @param[in] u32PeriodLevel output level at period(center) point, valid values are: 489 * - \ref EPWM_OUTPUT_NOTHING 490 * - \ref EPWM_OUTPUT_LOW 491 * - \ref EPWM_OUTPUT_HIGH 492 * - \ref EPWM_OUTPUT_TOGGLE 493 * @param[in] u32CmpDownLevel output level at compare down point, valid values are: 494 * - \ref EPWM_OUTPUT_NOTHING 495 * - \ref EPWM_OUTPUT_LOW 496 * - \ref EPWM_OUTPUT_HIGH 497 * - \ref EPWM_OUTPUT_TOGGLE 498 * @return None 499 * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s). 500 * \hideinitializer 501 */ 502 #define EPWM_SET_OUTPUT_LEVEL(epwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \ 503 do{ \ 504 int i; \ 505 for(i = 0; i < 6; i++) { \ 506 if((u32ChannelMask) & (1 << i)) { \ 507 (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1))); \ 508 (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))) | ((u32PeriodLevel) << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))); \ 509 (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (i << 1))) | ((u32CmpUpLevel) << (i << 1))); \ 510 (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))) | ((u32CmpDownLevel) << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))); \ 511 } \ 512 } \ 513 }while(0) 514 515 /** 516 * @brief Trigger brake event from specified channel(s) 517 * @param[in] epwm The pointer of the specified EPWM module 518 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel 519 * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 520 * @param[in] u32BrakeType Type of brake trigger. 521 * - \ref EPWM_FB_EDGE 522 * - \ref EPWM_FB_LEVEL 523 * @return None 524 * @details This macro is used to trigger brake event from specified channel(s). 525 * \hideinitializer 526 */ 527 #define EPWM_TRIGGER_BRAKE(epwm, u32ChannelMask, u32BrakeType) ((epwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType))) 528 529 /** 530 * @brief Set Dead zone clock source 531 * @param[in] epwm The pointer of the specified EPWM module 532 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 533 * @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler). 534 * @return None 535 * @details This macro is used to set Dead zone clock source. Every two channels share the same setting. 536 * @note The write-protection function should be disabled before using this function. 537 * \hideinitializer 538 */ 539 #define EPWM_SET_DEADZONE_CLK_SRC(epwm, u32ChannelNum, u32AfterPrescaler) \ 540 ((epwm)->DTCTL[(u32ChannelNum) >> 1] = (((epwm)->DTCTL[(u32ChannelNum) >> 1] & ~EPWM_DTCTL0_1_DTCKSEL_Msk) | \ 541 ((u32AfterPrescaler) << EPWM_DTCTL0_1_DTCKSEL_Pos))) 542 543 /*---------------------------------------------------------------------------------------------------------*/ 544 /* Define EPWM functions prototype */ 545 /*---------------------------------------------------------------------------------------------------------*/ 546 uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge); 547 uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle); 548 void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask); 549 void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask); 550 void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask); 551 void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); 552 void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum); 553 int32_t EPWM_EnableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Prescale, uint32_t u32PrescaleCnt); 554 void EPWM_DisableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum); 555 void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); 556 uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 557 void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); 558 void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum); 559 void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); 560 uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 561 void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource); 562 void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask); 563 void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask); 564 void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask); 565 void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask); 566 void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode); 567 void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum); 568 void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration); 569 void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum); 570 void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); 571 void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); 572 void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); 573 uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 574 void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType); 575 void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum); 576 void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 577 uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 578 void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource); 579 void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource); 580 void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource); 581 uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource); 582 void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType); 583 void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum); 584 void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 585 uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 586 void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum); 587 void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum); 588 void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 589 uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 590 void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc); 591 void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum); 592 void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); 593 void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); 594 void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); 595 uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); 596 void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum); 597 void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum); 598 void EPWM_EnableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum); 599 void EPWM_DisableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum); 600 void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 601 uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 602 void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); 603 void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); 604 void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase); 605 void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask); 606 void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask); 607 void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel); 608 void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm); 609 void EPWM_EnableSyncPinInverse(EPWM_T *epwm); 610 void EPWM_DisableSyncPinInverse(EPWM_T *epwm); 611 void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel); 612 void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel); 613 void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum); 614 void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum); 615 void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum); 616 void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule); 617 void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable); 618 uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 619 void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum); 620 void EPWM_EnableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32AfterPrescaler, uint32_t u32ClkSel); 621 void EPWM_DisableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum); 622 void EPWM_EnableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum); 623 void EPWM_DisableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum); 624 void EPWM_EnableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32DeglitchSmpCycle); 625 void EPWM_DisableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum); 626 void EPWM_EnableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32MaskCnt); 627 void EPWM_DisableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum); 628 void EPWM_EnableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); 629 void EPWM_DisableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); 630 void EPWM_ClearFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); 631 uint32_t EPWM_GetFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); 632 633 /*@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */ 634 635 /*@}*/ /* end of group EPWM_Driver */ 636 637 /*@}*/ /* end of group Standard_Driver */ 638 639 #ifdef __cplusplus 640 } 641 #endif 642 643 #endif /* __EPWM_H__ */ 644 645 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ 646
