1 /**************************************************************************//** 2 * @file eadc.h 3 * @version V1.0 4 * @brief M2L31 series EADC driver header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2023 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __EADC_H__ 10 #define __EADC_H__ 11 12 #ifdef __cplusplus 13 extern "C" 14 { 15 #endif 16 17 18 /** @addtogroup Standard_Driver Standard Driver 19 @{ 20 */ 21 22 /** @addtogroup EADC_Driver EADC Driver 23 @{ 24 */ 25 26 /** @addtogroup EADC_EXPORTED_CONSTANTS EADC Exported Constants 27 @{ 28 */ 29 30 /*---------------------------------------------------------------------------------------------------------*/ 31 /* EADC_CTL Constant Definitions */ 32 /*---------------------------------------------------------------------------------------------------------*/ 33 #define EADC_CTL_DIFFEN_SINGLE_END (0UL<<EADC_CTL_DIFFEN_Pos) /*!< Single-end input mode \hideinitializer */ 34 #define EADC_CTL_DIFFEN_DIFFERENTIAL (1UL<<EADC_CTL_DIFFEN_Pos) /*!< Differential input mode \hideinitializer */ 35 36 #define EADC_CTL_DMOF_STRAIGHT_BINARY (0UL<<EADC_CTL_DMOF_Pos) /*!< Select the straight binary format as the output format of the conversion result \hideinitializer */ 37 #define EADC_CTL_DMOF_TWOS_COMPLEMENT (1UL<<EADC_CTL_DMOF_Pos) /*!< Select the 2's complement format as the output format of the conversion result \hideinitializer */ 38 39 /*---------------------------------------------------------------------------------------------------------*/ 40 /* EADC_SCTL Constant Definitions */ 41 /*---------------------------------------------------------------------------------------------------------*/ 42 #define EADC_SCTL_CHSEL(x) ((x) << EADC_SCTL_CHSEL_Pos) /*!< A/D sample module channel selection \hideinitializer */ 43 #define EADC_SCTL_TRGDLYDIV(x) ((x) << EADC_SCTL_TRGDLYDIV_Pos) /*!< A/D sample module start of conversion trigger delay clock divider selection \hideinitializer */ 44 #define EADC_SCTL_TRGDLYCNT(x) ((x) << EADC_SCTL_TRGDLYCNT_Pos) /*!< A/D sample module start of conversion trigger delay time \hideinitializer */ 45 46 #define EADC_SOFTWARE_TRIGGER (0UL<<EADC_SCTL_TRGSEL_Pos) /*!< Software trigger \hideinitializer */ 47 #define EADC_FALLING_EDGE_TRIGGER (EADC_SCTL_EXTFEN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin falling edge trigger \hideinitializer */ 48 #define EADC_RISING_EDGE_TRIGGER (EADC_SCTL_EXTREN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin rising edge trigger \hideinitializer */ 49 #define EADC_FALLING_RISING_EDGE_TRIGGER (EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin both falling and rising edge trigger \hideinitializer */ 50 #define EADC_ADINT0_TRIGGER (2UL<<EADC_SCTL_TRGSEL_Pos) /*!< EADC ADINT0 interrupt EOC pulse trigger \hideinitializer */ 51 #define EADC_ADINT1_TRIGGER (3UL<<EADC_SCTL_TRGSEL_Pos) /*!< EADC ADINT1 interrupt EOC pulse trigger \hideinitializer */ 52 #define EADC_TIMER0_TRIGGER (4UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer0 overflow pulse trigger \hideinitializer */ 53 #define EADC_TIMER1_TRIGGER (5UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer1 overflow pulse trigger \hideinitializer */ 54 #define EADC_TIMER2_TRIGGER (6UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer2 overflow pulse trigger \hideinitializer */ 55 #define EADC_TIMER3_TRIGGER (7UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer3 overflow pulse trigger \hideinitializer */ 56 #define EADC_EPWM0TG0_TRIGGER (8UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG0 trigger \hideinitializer */ 57 #define EADC_EPWM0TG1_TRIGGER (9UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG1 trigger \hideinitializer */ 58 #define EADC_EPWM0TG2_TRIGGER (0xAUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG2 trigger \hideinitializer */ 59 #define EADC_EPWM0TG3_TRIGGER (0xBUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG3 trigger \hideinitializer */ 60 #define EADC_EPWM0TG4_TRIGGER (0xCUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG4 trigger \hideinitializer */ 61 #define EADC_EPWM0TG5_TRIGGER (0xDUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG5 trigger \hideinitializer */ 62 #define EADC_EPWM1TG0_TRIGGER (0xEUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG0 trigger \hideinitializer */ 63 #define EADC_EPWM1TG1_TRIGGER (0xFUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG1 trigger \hideinitializer */ 64 #define EADC_EPWM1TG2_TRIGGER (0x10UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG2 trigger \hideinitializer */ 65 #define EADC_EPWM1TG3_TRIGGER (0x11UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG3 trigger \hideinitializer */ 66 #define EADC_EPWM1TG4_TRIGGER (0x12UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG4 trigger \hideinitializer */ 67 #define EADC_EPWM1TG5_TRIGGER (0x13UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG5 trigger \hideinitializer */ 68 #define EADC_PWM0TG0_TRIGGER (0x14UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG0 trigger \hideinitializer */ 69 #define EADC_PWM0TG1_TRIGGER (0x15UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG1 trigger \hideinitializer */ 70 #define EADC_PWM0TG2_TRIGGER (0x16UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG2 trigger \hideinitializer */ 71 #define EADC_PWM0TG3_TRIGGER (0x17UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG3 trigger \hideinitializer */ 72 #define EADC_PWM0TG4_TRIGGER (0x18UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG4 trigger \hideinitializer */ 73 #define EADC_PWM0TG5_TRIGGER (0x19UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG5 trigger \hideinitializer */ 74 #define EADC_PWM1TG0_TRIGGER (0x1AUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG0 trigger \hideinitializer */ 75 #define EADC_PWM1TG1_TRIGGER (0x1BUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG1 trigger \hideinitializer */ 76 #define EADC_PWM1TG2_TRIGGER (0x1CUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG2 trigger \hideinitializer */ 77 #define EADC_PWM1TG3_TRIGGER (0x1DUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG3 trigger \hideinitializer */ 78 #define EADC_PWM1TG4_TRIGGER (0x1EUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG4 trigger \hideinitializer */ 79 #define EADC_PWM1TG5_TRIGGER (0x1FUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG5 trigger \hideinitializer */ 80 #define EADC_ACMP0_TRIGGER (0x20UL<<EADC_SCTL_TRGSEL_Pos) /*!< ACMP0 trigger \hideinitializer */ 81 #define EADC_ACMP1_TRIGGER (0x21UL<<EADC_SCTL_TRGSEL_Pos) /*!< ACMP1 trigger \hideinitializer */ 82 #define EADC_ACMP2_TRIGGER (0x22UL<<EADC_SCTL_TRGSEL_Pos) /*!< ACMP2 trigger \hideinitializer */ 83 84 #define EADC_SCTL_TRGDLYDIV_DIVIDER_1 (0x0UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/1 \hideinitializer */ 85 #define EADC_SCTL_TRGDLYDIV_DIVIDER_2 (0x1UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/2 \hideinitializer */ 86 #define EADC_SCTL_TRGDLYDIV_DIVIDER_4 (0x2UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/4 \hideinitializer */ 87 #define EADC_SCTL_TRGDLYDIV_DIVIDER_16 (0x3UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/16 \hideinitializer */ 88 89 /*---------------------------------------------------------------------------------------------------------*/ 90 /* EADC_CMP Constant Definitions */ 91 /*---------------------------------------------------------------------------------------------------------*/ 92 #define EADC_CMP_CMPCOND_LESS_THAN (0UL<<EADC_CMP_CMPCOND_Pos) /*!< The compare condition is "less than" \hideinitializer */ 93 #define EADC_CMP_CMPCOND_GREATER_OR_EQUAL (1UL<<EADC_CMP_CMPCOND_Pos) /*!< The compare condition is "greater than or equal to" \hideinitializer */ 94 #define EADC_CMP_CMPWEN_ENABLE (EADC_CMP_CMPWEN_Msk) /*!< Compare window mode enable \hideinitializer */ 95 #define EADC_CMP_CMPWEN_DISABLE (~EADC_CMP_CMPWEN_Msk) /*!< Compare window mode disable \hideinitializer */ 96 #define EADC_CMP_ADCMPIE_ENABLE (EADC_CMP_ADCMPIE_Msk) /*!< A/D result compare interrupt enable \hideinitializer */ 97 #define EADC_CMP_ADCMPIE_DISABLE (~EADC_CMP_ADCMPIE_Msk) /*!< A/D result compare interrupt disable \hideinitializer */ 98 99 /*---------------------------------------------------------------------------------------------------------*/ 100 /* EADC_MnCTL1 Constant Definitions */ 101 /*---------------------------------------------------------------------------------------------------------*/ 102 #define EADC_MCTL1_ACU_1 (0x0UL<<EADC_MCTL1_ACU_Pos) /*!< Accumulated 1 time \hideinitializer */ 103 #define EADC_MCTL1_ACU_2 (0x1UL<<EADC_MCTL1_ACU_Pos) /*!< Accumulated 2 times \hideinitializer */ 104 #define EADC_MCTL1_ACU_4 (0x2UL<<EADC_MCTL1_ACU_Pos) /*!< Accumulated 4 times \hideinitializer */ 105 #define EADC_MCTL1_ACU_8 (0x3UL<<EADC_MCTL1_ACU_Pos) /*!< Accumulated 8 times \hideinitializer */ 106 #define EADC_MCTL1_ACU_16 (0x4UL<<EADC_MCTL1_ACU_Pos) /*!< Accumulated 16 times \hideinitializer */ 107 #define EADC_MCTL1_ACU_32 (0x5UL<<EADC_MCTL1_ACU_Pos) /*!< Accumulated 32 times \hideinitializer */ 108 #define EADC_MCTL1_ACU_64 (0x6UL<<EADC_MCTL1_ACU_Pos) /*!< Accumulated 64 times \hideinitializer */ 109 #define EADC_MCTL1_ACU_128 (0x7UL<<EADC_MCTL1_ACU_Pos) /*!< Accumulated 128 times \hideinitializer */ 110 #define EADC_MCTL1_ACU_256 (0x8UL<<EADC_MCTL1_ACU_Pos) /*!< Accumulated 256 times \hideinitializer */ 111 112 /*@}*/ /* end of group EADC_EXPORTED_CONSTANTS */ 113 114 /** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions 115 @{ 116 */ 117 /*---------------------------------------------------------------------------------------------------------*/ 118 /* EADC Macro Definitions */ 119 /*---------------------------------------------------------------------------------------------------------*/ 120 121 /** 122 * @brief A/D Converter Control Circuits Reset. 123 * @param[in] eadc The pointer of the specified EADC module. 124 * @return None 125 * @details ADCRST bit remains 1 during EADC reset, when EADC reset end, the ADCRST bit is automatically cleared to 0. 126 * \hideinitializer 127 */ 128 #define EADC_CONV_RESET(eadc) ((eadc)->CTL |= EADC_CTL_ADCRST_Msk) 129 130 /** 131 * @brief Enable Sample Module PDMA transfer. 132 * @param[in] eadc The pointer of the specified EADC module. 133 * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. 134 * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFFFFF. 135 * @return None 136 * @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 30) register, 137 * user can enable this bit to generate a PDMA data transfer request. 138 * \hideinitializer 139 */ 140 #define EADC_ENABLE_SAMPLE_MODULE_PDMA(eadc, u32ModuleMask) ((eadc)->PDMACTL |= u32ModuleMask) 141 142 /** 143 * @brief Disable Sample Module PDMA transfer. 144 * @param[in] eadc The pointer of the specified EADC module. 145 * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. 146 * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFFFFF. 147 * @return None 148 * @details This macro is used to disable sample module PDMA transfer. 149 * \hideinitializer 150 */ 151 #define EADC_DISABLE_SAMPLE_MODULE_PDMA(eadc, u32ModuleMask) ((eadc)->PDMACTL &= (~u32ModuleMask)) 152 153 /** 154 * @brief Enable double buffer mode. 155 * @param[in] eadc The pointer of the specified EADC module. 156 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3. 157 * @return None 158 * @details The EADC controller supports a double buffer mode in sample module 0~3. 159 * If user enable DBMEN, the double buffer mode will enable. 160 * \hideinitializer 161 */ 162 #define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->MCTL1[(u32ModuleNum)] |= EADC_MCTL1_DBMEN_Msk) 163 164 /** 165 * @brief Disable double buffer mode. 166 * @param[in] eadc The pointer of the specified EADC module. 167 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3. 168 * @return None 169 * @details Sample has one sample result register. 170 * \hideinitializer 171 */ 172 #define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->MCTL1[(u32ModuleNum)] &= ~EADC_MCTL1_DBMEN_Msk) 173 174 /** 175 * @brief Set ADIFn at A/D end of conversion. 176 * @param[in] eadc The pointer of the specified EADC module. 177 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 30. 178 * @return None 179 * @details The A/D converter generates ADIFn at the start of conversion. 180 * \hideinitializer 181 */ 182 #define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) (((u32ModuleNum)<19) ? ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk) : ((eadc)->SCTL19[(u32ModuleNum)-19] |= EADC_SCTL_INTPOS_Msk)) 183 184 /** 185 * @brief Set ADIFn at A/D start of conversion. 186 * @param[in] eadc The pointer of the specified EADC module. 187 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 30. 188 * @return None 189 * @details The A/D converter generates ADIFn at the end of conversion. 190 * \hideinitializer 191 */ 192 #define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) (((u32ModuleNum)<19) ? ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk) : ((eadc)->SCTL19[(u32ModuleNum)-19] &= ~EADC_SCTL_INTPOS_Msk)) 193 194 /** 195 * @brief Enable the interrupt. 196 * @param[in] eadc The pointer of the specified EADC module. 197 * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. 198 * This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. 199 * @return None 200 * @details The A/D converter generates a conversion end ADIFn upon the end of specific sample module A/D conversion. 201 * If ADCIENn bit is set then conversion end interrupt request ADINTn is generated (n=0~3). 202 * \hideinitializer 203 */ 204 #define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos)) 205 206 /** 207 * @brief Disable the interrupt. 208 * @param[in] eadc The pointer of the specified EADC module. 209 * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. 210 * This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. 211 * @return None 212 * @details Specific sample module A/D ADINT0 interrupt function Disabled. 213 * \hideinitializer 214 */ 215 #define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos)) 216 217 /** 218 * @brief Enable the sample module interrupt. 219 * @param[in] eadc The pointer of the specified EADC module. 220 * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. 221 * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. 222 * This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFFFFF. 223 * @return None 224 * @details There are 4 EADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address. 225 * \hideinitializer 226 */ 227 #define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask)) 228 229 /** 230 * @brief Disable the sample module interrupt. 231 * @param[in] eadc The pointer of the specified EADC module. 232 * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. 233 * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. 234 * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFFFFF. 235 * @return None 236 * @details There are 4 EADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address. 237 * \hideinitializer 238 */ 239 #define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= ~(u32ModuleMask)) 240 241 /** 242 * @brief Set the input mode output format. 243 * @param[in] eadc The pointer of the specified EADC module. 244 * @param[in] u32Format Decides the output format. Valid values are: 245 * - EADC_CTL_DMOF_STRAIGHT_BINARY :Select the straight binary format as the output format of the conversion result. 246 * - EADC_CTL_DMOF_TWOS_COMPLEMENT :Select the 2's complement format as the output format of the conversion result. 247 * @return None 248 * @details The macro is used to set A/D input mode output format. 249 * \hideinitializer 250 */ 251 #define EADC_SET_DMOF(eadc, u32Format) ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format)) 252 253 /** 254 * @brief Start the A/D conversion. 255 * @param[in] eadc The pointer of the specified EADC module. 256 * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module. 257 * This parameter decides which sample module will be conversion, valid range are between 1~0x7FFFFFFF. 258 * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 30 is sample module 30. 259 * @return None 260 * @details After write EADC_SWTRG register to start EADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion. 261 * \hideinitializer 262 */ 263 #define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask)) 264 265 /** 266 * @brief Cancel the conversion for sample module. 267 * @param[in] eadc The pointer of the specified EADC module. 268 * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module. 269 * This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFFFFF. 270 * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 30 is sample module 30. 271 * @return None 272 * @details If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. 273 * \hideinitializer 274 */ 275 #define EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask)) 276 277 /** 278 * @brief Get the conversion pending flag. 279 * @param[in] eadc The pointer of the specified EADC module. 280 * @return Return the conversion pending sample module. 281 * @details This STPFn bit remains 1 during pending state, when the respective EADC conversion is end, 282 * the STPFn (n=0~30) bit is automatically cleared to 0. 283 * \hideinitializer 284 */ 285 #define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS) 286 287 /** 288 * @brief Get the conversion data of the user-specified sample module. 289 * @param[in] eadc The pointer of the specified EADC module. 290 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 30. 291 * @return Return the conversion data of the user-specified sample module. 292 * @details This macro is used to read RESULT bit field to get conversion data. 293 * \hideinitializer 294 */ 295 #define EADC_GET_CONV_DATA(eadc, u32ModuleNum) (((u32ModuleNum)<19) ? ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk) : ((eadc)->DAT19[(u32ModuleNum)-19] & EADC_DAT_RESULT_Msk)) 296 297 /** 298 * @brief Get the data overrun flag of the user-specified sample module. 299 * @param[in] eadc The pointer of the specified EADC module. 300 * @param[in] u32ModuleMask The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFFFFF. 301 * @return Return the data overrun flag of the user-specified sample module. 302 * @details This macro is used to read OV bit field to get data overrun status. 303 * \hideinitializer 304 */ 305 #define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask)) 306 307 /** 308 * @brief Get the data valid flag of the user-specified sample module. 309 * @param[in] eadc The pointer of the specified EADC module. 310 * @param[in] u32ModuleMask The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFFFFF. 311 * @return Return the data valid flag of the user-specified sample module. 312 * @details This macro is used to read VALID bit field to get data valid status. 313 * \hideinitializer 314 */ 315 #define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask)) 316 317 /** 318 * @brief Get the double data of the user-specified sample module. 319 * @param[in] eadc The pointer of the specified EADC module. 320 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3. 321 * @return Return the double data of the user-specified sample module. 322 * @details This macro is used to read RESULT bit (EADC_DDATn[15:0], n=0~3) field to get conversion data. 323 * \hideinitializer 324 */ 325 #define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT0_RESULT_Msk) 326 327 /** 328 * @brief Get the user-specified interrupt flags. 329 * @param[in] eadc The pointer of the specified EADC module. 330 * @param[in] u32Mask The combination of interrupt status bits. Each bit corresponds to a interrupt status. 331 * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. 332 * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. 333 * @return Return the user-specified interrupt flags. 334 * @details This macro is used to get the user-specified interrupt flags. 335 * \hideinitializer 336 */ 337 #define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask)) 338 339 /** 340 * @brief Get the user-specified sample module overrun flags. 341 * @param[in] eadc The pointer of the specified EADC module. 342 * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFFFFF. 343 * @return Return the user-specified sample module overrun flags. 344 * @details This macro is used to get the user-specified sample module overrun flags. 345 * \hideinitializer 346 */ 347 #define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask)) 348 349 /** 350 * @brief Clear the selected interrupt status bits. 351 * @param[in] eadc The pointer of the specified EADC module. 352 * @param[in] u32Mask The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status. 353 * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. 354 * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. 355 * @return None 356 * @details This macro is used to clear clear the selected interrupt status bits. 357 * \hideinitializer 358 */ 359 #define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask)) 360 361 /** 362 * @brief Clear the selected sample module overrun status bits. 363 * @param[in] eadc The pointer of the specified EADC module. 364 * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status. 365 * Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 30 is SPOVF30. 366 * @return None 367 * @details This macro is used to clear the selected sample module overrun status bits. 368 * \hideinitializer 369 */ 370 #define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask)) 371 372 /** 373 * @brief Check all sample module A/D result data register overrun flags. 374 * @param[in] eadc The pointer of the specified EADC module. 375 * @retval 0 None of sample module data register overrun flag is set to 1. 376 * @retval 1 Any one of sample module data register overrun flag is set to 1. 377 * @details The AOV bit will keep 1 when any one of sample module data register overrun flag OVn is set to 1. 378 * \hideinitializer 379 */ 380 #define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos) 381 382 /** 383 * @brief Check all sample module A/D result data register valid flags. 384 * @param[in] eadc The pointer of the specified EADC module. 385 * @retval 0 None of sample module data register valid flag is set to 1. 386 * @retval 1 Any one of sample module data register valid flag is set to 1. 387 * @details The AVALID bit will keep 1 when any one of sample module data register valid flag VALIDn is set to 1. 388 * \hideinitializer 389 */ 390 #define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos) 391 392 /** 393 * @brief Check all A/D sample module start of conversion overrun flags. 394 * @param[in] eadc The pointer of the specified EADC module. 395 * @retval 0 None of sample module event overrun flag is set to 1. 396 * @retval 1 Any one of sample module event overrun flag is set to 1. 397 * @details The STOVF bit will keep 1 when any one of sample module event overrun flag SPOVFn is set to 1. 398 * \hideinitializer 399 */ 400 #define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos) 401 402 /** 403 * @brief Check all A/D interrupt flag overrun bits. 404 * @param[in] eadc The pointer of the specified EADC module. 405 * @retval 0 None of ADINT interrupt flag is overwritten to 1. 406 * @retval 1 Any one of ADINT interrupt flag is overwritten to 1. 407 * @details The ADOVIF bit will keep 1 when any one of ADINT interrupt flag ADOVIFn is overwritten to 1. 408 * \hideinitializer 409 */ 410 #define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos) 411 412 /** 413 * @brief Get the busy state of EADC. 414 * @param[in] eadc The pointer of the specified EADC module. 415 * @retval 0 Idle state. 416 * @retval 1 Busy state. 417 * @details This macro is used to read BUSY bit to get busy state. 418 * \hideinitializer 419 */ 420 #define EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos) 421 422 /** 423 * @brief Configure the comparator 0 and enable it. 424 * @param[in] eadc The pointer of the specified EADC module. 425 * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 30. 426 * @param[in] u32Condition specifies the compare condition. Valid values are: 427 * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" 428 * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value 429 * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. 430 * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~16. 431 * @return None 432 * @details For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); 433 * Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or 434 * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. 435 * \hideinitializer 436 */ 437 #define EADC_ENABLE_CMP0(eadc,\ 438 u32ModuleNum,\ 439 u32Condition,\ 440 u16CMPData,\ 441 u32MatchCount) ((eadc)->CMP[0] = (((eadc)->CMP[0] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\ 442 (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ 443 (u32Condition) |\ 444 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ 445 (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ 446 EADC_CMP_ADCMPEN_Msk))) 447 448 /** 449 * @brief Configure the comparator 1 and enable it. 450 * @param[in] eadc The pointer of the specified EADC module. 451 * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 30. 452 * @param[in] u32Condition specifies the compare condition. Valid values are: 453 * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" 454 * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value 455 * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. 456 * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~16. 457 * @return None 458 * @details For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); 459 * Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or 460 * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. 461 * \hideinitializer 462 */ 463 #define EADC_ENABLE_CMP1(eadc,\ 464 u32ModuleNum,\ 465 u32Condition,\ 466 u16CMPData,\ 467 u32MatchCount) ((eadc)->CMP[1] = (((eadc)->CMP[1] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\ 468 (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ 469 (u32Condition) |\ 470 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ 471 (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ 472 EADC_CMP_ADCMPEN_Msk))) 473 474 /** 475 * @brief Configure the comparator 2 and enable it. 476 * @param[in] eadc The pointer of the specified EADC module. 477 * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 30. 478 * @param[in] u32Condition specifies the compare condition. Valid values are: 479 * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" 480 * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value 481 * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. 482 * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~16. 483 * @return None 484 * @details For example, ADC_ENABLE_CMP2(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); 485 * Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or 486 * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. 487 * \hideinitializer 488 */ 489 #define EADC_ENABLE_CMP2(eadc,\ 490 u32ModuleNum,\ 491 u32Condition,\ 492 u16CMPData,\ 493 u32MatchCount) ((eadc)->CMP[2] = (((eadc)->CMP[2] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\ 494 (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ 495 (u32Condition) |\ 496 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ 497 (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ 498 EADC_CMP_ADCMPEN_Msk))) 499 500 /** 501 * @brief Configure the comparator 3 and enable it. 502 * @param[in] eadc The pointer of the specified EADC module. 503 * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 30. 504 * @param[in] u32Condition specifies the compare condition. Valid values are: 505 * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" 506 * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value 507 * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. 508 * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~16. 509 * @return None 510 * @details For example, ADC_ENABLE_CMP3(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); 511 * Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or 512 * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. 513 * \hideinitializer 514 */ 515 #define EADC_ENABLE_CMP3(eadc,\ 516 u32ModuleNum,\ 517 u32Condition,\ 518 u16CMPData,\ 519 u32MatchCount) ((eadc)->CMP[3] = (((eadc)->CMP[3] & ~(EADC_CMP_CMPSPL_Msk|EADC_CMP_CMPCOND_Msk|EADC_CMP_CMPDAT_Msk|EADC_CMP_CMPMCNT_Msk))|\ 520 (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ 521 (u32Condition) |\ 522 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ 523 (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\ 524 EADC_CMP_ADCMPEN_Msk))) 525 526 /** 527 * @brief Enable the compare window mode. 528 * @param[in] eadc The pointer of the specified EADC module. 529 * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2. 530 * @return None 531 * @details ADCMPF0 will be set when both ADCMPF0 and ADCMPF1 compared condition matched. 532 * ADCMPF2 will be set when both ADCMPF2 and ADCMPF3 compared condition matched. 533 * \hideinitializer 534 */ 535 #define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk) 536 537 /** 538 * @brief Disable the compare window mode. 539 * @param[in] eadc The pointer of the specified EADC module. 540 * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2. 541 * @return None 542 * @details ADCMPF0 will be set when both ADCMPF0 and ADCMPF1 compared condition matched. 543 * ADCMPF2 will be set when both ADCMPF2 and ADCMPF3 compared condition matched. 544 * \hideinitializer 545 */ 546 #define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk) 547 548 /** 549 * @brief Enable the compare interrupt. 550 * @param[in] eadc The pointer of the specified EADC module. 551 * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3. 552 * @return None 553 * @details If the compare function is enabled and the compare condition matches the setting of CMPCOND 554 * and CMPMCNT, ADCMPFn will be asserted, in the meanwhile, 555 * if ADCMPIE is set to 1, a compare interrupt request is generated. 556 * \hideinitializer 557 */ 558 #define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk) 559 560 /** 561 * @brief Disable the compare interrupt. 562 * @param[in] eadc The pointer of the specified EADC module. 563 * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3. 564 * @return None 565 * @details This macro is used to disable the compare interrupt. 566 * \hideinitializer 567 */ 568 #define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk) 569 570 /** 571 * @brief Disable comparator 0. 572 * @param[in] eadc The pointer of the specified EADC module. 573 * @return None 574 * @details This macro is used to disable comparator 0. 575 * \hideinitializer 576 */ 577 #define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0) 578 579 /** 580 * @brief Disable comparator 1. 581 * @param[in] eadc The pointer of the specified EADC module. 582 * @return None 583 * @details This macro is used to disable comparator 1. 584 * \hideinitializer 585 */ 586 #define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0) 587 588 /** 589 * @brief Disable comparator 2. 590 * @param[in] eadc The pointer of the specified EADC module. 591 * @return None 592 * @details This macro is used to disable comparator 2. 593 * \hideinitializer 594 */ 595 #define EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] = 0) 596 597 /** 598 * @brief Disable comparator 3. 599 * @param[in] eadc The pointer of the specified EADC module. 600 * @return None 601 * @details This macro is used to disable comparator 3. 602 * \hideinitializer 603 */ 604 #define EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] = 0) 605 606 /** 607 * @brief Enable conversion result left alignment. 608 * @param[in] eadc The pointer of the specified EADC module. 609 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 26. 610 * @return None 611 * @details The 12-bit conversion result will be left aligned and stored in EADC_DATn[15:4] (n=0~23). 612 * \hideinitializer 613 */ 614 #define EADC_ENABLE_LEFT_ALIGN(eadc, u32ModuleNum) (((u32ModuleNum)<19) ? ((eadc)->MCTL1[(u32ModuleNum)] |= EADC_MCTL1_ALIGN_Msk) : ((eadc)->M19CTL1[(u32ModuleNum)-19] |= EADC_MCTL1_ALIGN_Msk)) 615 616 /** 617 * @brief Disable conversion result left alignment. 618 * @param[in] eadc The pointer of the specified EADC module. 619 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 26. 620 * @return None 621 * @details The 12-bit conversion result will be right aligned and stored in EADC_DATn[11:0] (n=0~23). 622 * \hideinitializer 623 */ 624 #define EADC_DISABLE_LEFT_ALIGN(eadc, u32ModuleNum) (((u32ModuleNum)<19) ? ((eadc)->MCTL1[(u32ModuleNum)] &= (~EADC_MCTL1_ALIGN_Msk)) : ((eadc)->M19CTL1[(u32ModuleNum)-19] &= (~EADC_MCTL1_ALIGN_Msk))) 625 626 /** 627 * @brief Enable average mode. 628 * @param[in] eadc The pointer of the specified EADC module. 629 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 26. 630 * @return None 631 * @details Conversion results in data register will be averaged. 632 * @note This average mode needs to work with accumulated mode that configured by ACU bit field. 633 * \hideinitializer 634 */ 635 #define EADC_ENABLE_AVG(eadc, u32ModuleNum) (((u32ModuleNum)<19) ? ((eadc)->MCTL1[(u32ModuleNum)] |= EADC_MCTL1_AVG_Msk) : ((eadc)->M19CTL1[(u32ModuleNum)-19] |= EADC_MCTL1_AVG_Msk)) 636 637 /** 638 * @brief Disable average mode. 639 * @param[in] eadc The pointer of the specified EADC module. 640 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 26. 641 * @return None 642 * @details Conversion results in data register will not be averaged. 643 * \hideinitializer 644 */ 645 #define EADC_DISABLE_AVG(eadc, u32ModuleNum) (((u32ModuleNum)<19) ? ((eadc)->MCTL1[(u32ModuleNum)] &= (~EADC_MCTL1_AVG_Msk)) : ((eadc)->M19CTL1[(u32ModuleNum)-19] &= (~EADC_MCTL1_AVG_Msk))) 646 647 /** 648 * @brief Configure the Accumulation feature and enable it. 649 * @param[in] eadc The pointer of the specified EADC module. 650 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 26. 651 * @param[in] u16ACUNum specifies the number of accumulation, valid values are 652 * - \ref EADC_MCTL1_ACU_1 : 1 conversion result will be accumulated. 653 * - \ref EADC_MCTL1_ACU_2 : 2 conversion result will be accumulated. 654 * - \ref EADC_MCTL1_ACU_4 : 4 conversion result will be accumulated. 655 * - \ref EADC_MCTL1_ACU_8 : 8 conversion result will be accumulated. 656 * - \ref EADC_MCTL1_ACU_16 : 16 conversion result will be accumulated. 657 * - \ref EADC_MCTL1_ACU_32 : 32 conversion result will be accumulated. The result is right shift 1 bit to fit within the available 16-bit register size. 658 * - \ref EADC_MCTL1_ACU_64 : 64 conversion result will be accumulated. The result is right shift 2 bits to fit within the available 16-bit register size. 659 * - \ref EADC_MCTL1_ACU_128 : 128 conversion result will be accumulated. The result is right shift 3 bits to fit within the available 16-bit register size. 660 * - \ref EADC_MCTL1_ACU_256 : 256 conversion result will be accumulated. The result is right shift 4 bits to fit within the available 16-bit register size. 661 * @return None 662 * @details When accumulating more than 16 samples, the result will be too large to match the 663 * 16-bit RESULT register size (EADC_DATn[15:0]. To avoid overflow, the result is 664 * right shifted automatically to fit within the available 16-bit register size. 665 * The number of automatic right shifts is specified in parameter list above. 666 * \hideinitializer 667 */ 668 #define EADC_ENABLE_ACU(eadc,\ 669 u32ModuleNum,\ 670 u16ACUNum) (((u32ModuleNum)<19) ? \ 671 (((eadc)->MCTL1[(u32ModuleNum)]) = ((((eadc)->MCTL1[(u32ModuleNum)]) & (~EADC_MCTL1_ACU_Msk)) | (u16ACUNum))) : \ 672 (((eadc)->M19CTL1[(u32ModuleNum)-19]) = ((((eadc)->M19CTL1[(u32ModuleNum)-19]) & (~EADC_MCTL1_ACU_Msk)) | (u16ACUNum))) \ 673 ) 674 675 /** 676 * @brief Disable the Accumulation feature. 677 * @param[in] eadc The pointer of the specified EADC module. 678 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 26. 679 * @return None 680 * \hideinitializer 681 */ 682 #define EADC_DISABLE_ACU(eadc, u32ModuleNum) (((u32ModuleNum)<19) ? ((eadc)->MCTL1[(u32ModuleNum)] &= (~EADC_MCTL1_ACU_Msk)) : ((eadc)->M19CTL1[(u32ModuleNum)-19] &= (~EADC_MCTL1_ACU_Msk))) 683 684 685 /*---------------------------------------------------------------------------------------------------------*/ 686 /* Define EADC functions prototype */ 687 /*---------------------------------------------------------------------------------------------------------*/ 688 void EADC_Open(EADC_T *eadc, uint32_t u32InputMode); 689 void EADC_Close(EADC_T *eadc); 690 void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSrc, uint32_t u32Channel); 691 void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider); 692 void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime); 693 694 /*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */ 695 696 /*@}*/ /* end of group EADC_Driver */ 697 698 /*@}*/ /* end of group Standard_Driver */ 699 700 #ifdef __cplusplus 701 } 702 #endif 703 704 #endif /* __EADC_H__ */ 705 706 /*** (C) COPYRIGHT 2023 Nuvoton Technology Corp. ***/ 707
