1 2 /******************************************************************************/ 3 /* Device Specific Peripheral registers structures */ 4 /******************************************************************************/ 5 6 /** @addtogroup REGISTER Control Register 7 8 @{ 9 10 */ 11 12 13 14 /*---------------------- Window Watchdog Timer -------------------------*/ 15 /** 16 @addtogroup WWDT Window Watchdog Timer(WWDT) 17 Memory Mapped Structure for WWDT Controller 18 @{ */ 19 20 typedef struct 21 { 22 23 24 /** 25 * @var WWDT_T::RLDCNT 26 * Offset: 0x00 WWDT Reload Counter Register 27 * --------------------------------------------------------------------------------------------------- 28 * |Bits |Field |Descriptions 29 * | :----: | :----: | :---- | 30 * |[31:0] |RLDCNT |WWDT Reload Counter Register 31 * | | |Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F. 32 * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]) 33 * | | |If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will be generated immediately. 34 * @var WWDT_T::CTL 35 * Offset: 0x04 WWDT Control Register 36 * --------------------------------------------------------------------------------------------------- 37 * |Bits |Field |Descriptions 38 * | :----: | :----: | :---- | 39 * |[0] |WWDTEN |WWDT Enable Bit 40 * | | |0 = WWDT counter is stopped. 41 * | | |1 = WWDT counter starts counting. 42 * |[1] |INTEN |WWDT Interrupt Enable Bit 43 * | | |If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU. 44 * | | |0 = WWDT counter compare match interrupt Disabled. 45 * | | |1 = WWDT counter compare match interrupt Enabled. 46 * |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection 47 * | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK. 48 * | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK. 49 * | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK. 50 * | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK. 51 * | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK. 52 * | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK. 53 * | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK. 54 * | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK. 55 * | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK. 56 * | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK. 57 * | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK. 58 * | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK. 59 * | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK. 60 * | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK. 61 * | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK. 62 * | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK. 63 * |[21:16] |CMPDAT |WWDT Window Compare 64 * | | |Set this register to adjust the valid reload window. 65 * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT 66 * | | |If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately. 67 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit 68 * | | |0 = ICE debug mode acknowledgement effects WWDT counting. 69 * | | |WWDT down counter will be held while CPU is held by ICE. 70 * | | |1 = ICE debug mode acknowledgement Disabled. 71 * | | |Note: WWDT down counter will keep going no matter CPU is held by ICE or not. 72 * @var WWDT_T::STATUS 73 * Offset: 0x08 WWDT Status Register 74 * --------------------------------------------------------------------------------------------------- 75 * |Bits |Field |Descriptions 76 * | :----: | :----: | :---- | 77 * |[0] |WWDTIF |WWDT Compare Match Interrupt Flag 78 * | | |This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]). 79 * | | |0 = No effect. 80 * | | |1 = WWDT counter value matches CMPDAT. 81 * | | |Note: This bit is cleared by writing 1 to it. 82 * |[1] |WWDTRF |WWDT Timer-out Reset Flag 83 * | | |This bit indicates the system has been reset by WWDT time-out reset or not. 84 * | | |0 = WWDT time-out reset did not occur. 85 * | | |1 = WWDT time-out reset occurred. 86 * | | |Note: This bit is cleared by writing 1 to it. 87 * @var WWDT_T::CNT 88 * Offset: 0x0C WWDT Counter Value Register 89 * --------------------------------------------------------------------------------------------------- 90 * |Bits |Field |Descriptions 91 * | :----: | :----: | :---- | 92 * |[5:0] |CNTDAT |WWDT Counter Value 93 * | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value. 94 */ 95 __O uint32_t RLDCNT; /*!< [0x0000] WWDT Reload Counter Register */ 96 __IO uint32_t CTL; /*!< [0x0004] WWDT Control Register */ 97 __IO uint32_t STATUS; /*!< [0x0008] WWDT Status Register */ 98 __I uint32_t CNT; /*!< [0x000c] WWDT Counter Value Register */ 99 100 } WWDT_T; 101 102 /** 103 @addtogroup WWDT_CONST WWDT Bit Field Definition 104 Constant Definitions for WWDT Controller 105 @{ */ 106 107 #define WWDT_RLDCNT_RLDCNT_Pos (0) /*!< WWDT_T::RLDCNT: RLDCNT Position */ 108 #define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) /*!< WWDT_T::RLDCNT: RLDCNT Mask */ 109 110 #define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT_T::CTL: WWDTEN Position */ 111 #define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT_T::CTL: WWDTEN Mask */ 112 113 #define WWDT_CTL_INTEN_Pos (1) /*!< WWDT_T::CTL: INTEN Position */ 114 #define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT_T::CTL: INTEN Mask */ 115 116 #define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT_T::CTL: PSCSEL Position */ 117 #define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT_T::CTL: PSCSEL Mask */ 118 119 #define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT_T::CTL: CMPDAT Position */ 120 #define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT_T::CTL: CMPDAT Mask */ 121 122 #define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT_T::CTL: ICEDEBUG Position */ 123 #define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT_T::CTL: ICEDEBUG Mask */ 124 125 #define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT_T::STATUS: WWDTIF Position */ 126 #define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT_T::STATUS: WWDTIF Mask */ 127 128 #define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT_T::STATUS: WWDTRF Position */ 129 #define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT_T::STATUS: WWDTRF Mask */ 130 131 #define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT_T::CNT: CNTDAT Position */ 132 #define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT_T::CNT: CNTDAT Mask */ 133 134 /**@}*/ /* WWDT_CONST */ 135 /**@}*/ /* end of WWDT register group */ 136 137 138 /**@}*/ /* end of REGISTER group */ 139
