1 2 /******************************************************************************/ 3 /* Device Specific Peripheral registers structures */ 4 /******************************************************************************/ 5 6 /** @addtogroup REGISTER Control Register 7 8 @{ 9 10 */ 11 12 13 /*---------------------- Watch Dog Timer Controller -------------------------*/ 14 /** 15 @addtogroup WDT Watch Dog Timer Controller(WDT) 16 Memory Mapped Structure for WDT Controller 17 @{ */ 18 19 typedef struct 20 { 21 22 23 /** 24 * @var WDT_T::CTL 25 * Offset: 0x00 WDT Control Register 26 * --------------------------------------------------------------------------------------------------- 27 * |Bits |Field |Descriptions 28 * | :----: | :----: | :---- | 29 * |[1] |RSTEN |WDT Time-out Reset Enable Bit (Write Protect) 30 * | | |Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires. 31 * | | |0 = WDT time-out reset function Disabled. 32 * | | |1 = WDT time-out reset function Enabled. 33 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 34 * |[2] |RSTF |WDT Time-out Reset Flag 35 * | | |This bit indicates the system has been reset by WDT time-out reset or not. 36 * | | |0 = WDT time-out reset did not occur. 37 * | | |1 = WDT time-out reset occurred. 38 * | | |Note: This bit is cleared by writing 1 to it. 39 * |[3] |IF |WDT Time-out Interrupt Flag 40 * | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval. 41 * | | |0 = WDT time-out interrupt did not occur. 42 * | | |1 = WDT time-out interrupt occurred. 43 * | | |Note: This bit is cleared by writing 1 to it. 44 * |[4] |WKEN |WDT Time-out Wake-up Function Control (Write Protect) 45 * | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip. 46 * | | |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated. 47 * | | |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated. 48 * | | |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. 49 * | | |Note 2: Chip can be woken up by WDT time-out interrupt signal generated only if WDT clock source is selected to 32 kHz internal low speed RC oscillator (LIRC) or LXT. 50 * |[5] |WKF |WDT Time-out Wake-up Flag 51 * | | |This bit indicates the interrupt wake-up flag status of WDT 52 * | | |0 = WDT does not cause chip wake-up. 53 * | | |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated. 54 * | | |Note: This bit is cleared by writing 1 to it. 55 * |[6] |INTEN |WDT Time-out Interrupt Enable Bit (Write Protect) 56 * | | |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. 57 * | | |0 = WDT time-out interrupt Disabled. 58 * | | |1 = WDT time-out interrupt Enabled. 59 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 60 * |[7] |WDTEN |WDT Enable Bit (Write Protect) 61 * | | |0 = WDT Disabled (This action will reset the internal up counter value). 62 * | | |1 = WDT Enabled. 63 * | | |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. 64 * | | |Note 2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configured to 111, this bit is forced as 1 and user cannot change this bit to 0. 65 * |[11:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect) 66 * | | |These four bits select the time-out interval period for the WDT. 67 * | | |0000 = 24 * WDT_CLK. 68 * | | |0001 = 26 * WDT_CLK. 69 * | | |0010 = 28 * WDT_CLK. 70 * | | |0011 = 210 * WDT_CLK. 71 * | | |0100 = 212 * WDT_CLK. 72 * | | |0101 = 214 * WDT_CLK. 73 * | | |0110 = 216 * WDT_CLK. 74 * | | |0111 = 218 * WDT_CLK. 75 * | | |1000 = 220 * WDT_CLK. 76 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 77 * |[29] |PDRSTCNT |Reset Counter When Entering Power Down Enable Bit 78 * | | |0 = WDT up counter will keep going no matter CPU enter power down or not. 79 * | | |1 = Reset WDT up counter value to 0 when entering power down. 80 * |[30] |SYNC |WDT Enable Control SYNC Flag Indicator (Read Only) 81 * | | |If user executes enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not. 82 * | | |0 = Setting WDTEN bit is completed and WDT is ready. 83 * | | |1 = Setting WDTEN bit is synchronizing and not become active yet. 84 * | | |Note: Performing enable or disable WDTEN bit needs 4 * WDT_CLK period to become active. 85 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit (Write Protect) 86 * | | |0 = ICE debug mode acknowledgement affects WDT counting. 87 * | | |WDT up counter will be held while CPU is held by ICE. 88 * | | |1 = ICE debug mode acknowledgement Disabled. 89 * | | |WDT up counter will keep going no matter CPU is held by ICE or not. 90 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 91 * @var WDT_T::ALTCTL 92 * Offset: 0x04 WDT Alternative Control Register 93 * --------------------------------------------------------------------------------------------------- 94 * |Bits |Field |Descriptions 95 * | :----: | :----: | :---- | 96 * |[1:0] |RSTDSEL |WDT Reset Delay Selection (Write Protect) 97 * | | |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by programming 0x5AA5 to prevent WDT time-out reset happened 98 * | | |User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period. 99 * | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK. 100 * | | |01 = WDT Reset Delay Period is 130 * WDT_CLK. 101 * | | |10 = WDT Reset Delay Period is 18 * WDT_CLK. 102 * | | |11 = WDT Reset Delay Period is 3 * WDT_CLK. 103 * | | |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. 104 * | | |Note 2: This register will be reset to 0 if WDT time-out reset happened. 105 * @var WDT_T::RSTCNT 106 * Offset: 0x08 WDT Reset Counter Register 107 * --------------------------------------------------------------------------------------------------- 108 * |Bits |Field |Descriptions 109 * | :----: | :----: | :---- | 110 * |[31:0] |RSTCNT |WDT Reset Counter Register 111 * | | |Writing 0x00005AA5 to this field will reset the internal 20-bit WDT up counter value to 0. 112 * | | |Note: Performing RSTCNT to reset counter needs 2 * WDT_CLK period to become active. 113 */ 114 __IO uint32_t CTL; /*!< [0x0000] WDT Control Register */ 115 __IO uint32_t ALTCTL; /*!< [0x0004] WDT Alternative Control Register */ 116 __O uint32_t RSTCNT; /*!< [0x0008] WDT Reset Counter Register */ 117 118 } WDT_T; 119 120 /** 121 @addtogroup WDT_CONST WDT Bit Field Definition 122 Constant Definitions for WDT Controller 123 @{ */ 124 125 #define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */ 126 #define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */ 127 128 #define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */ 129 #define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */ 130 131 #define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */ 132 #define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */ 133 134 #define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */ 135 #define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */ 136 137 #define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */ 138 #define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */ 139 140 #define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */ 141 #define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */ 142 143 #define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */ 144 #define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */ 145 146 #define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */ 147 #define WDT_CTL_TOUTSEL_Msk (0xful << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */ 148 149 #define WDT_CTL_PDRSTCNT_Pos (29) /*!< WDT_T::CTL: PDRSTCNT Position */ 150 #define WDT_CTL_PDRSTCNT_Msk (0x1ul << WDT_CTL_PDRSTCNT_Pos) /*!< WDT_T::CTL: PDRSTCNT Mask */ 151 152 #define WDT_CTL_SYNC_Pos (30) /*!< WDT_T::CTL: SYNC Position */ 153 #define WDT_CTL_SYNC_Msk (0x1ul << WDT_CTL_SYNC_Pos) /*!< WDT_T::CTL: SYNC Mask */ 154 155 #define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */ 156 #define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */ 157 158 #define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */ 159 #define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */ 160 161 #define WDT_RSTCNT_RSTCNT_Pos (0) /*!< WDT_T::RSTCNT: RSTCNT Position */ 162 #define WDT_RSTCNT_RSTCNT_Msk (0xfffffffful << WDT_RSTCNT_RSTCNT_Pos) /*!< WDT_T::RSTCNT: RSTCNT Mask */ 163 164 /**@}*/ /* WDT_CONST */ 165 /**@}*/ /* end of WDT register group */ 166 167 /**@}*/ /* end of REGISTER group */ 168
